1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2025 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1126B_H 8 #define _ASM_ARCH_CRU_RV1126B_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 #define RC_OSC_HZ (125 * MHz) 16 17 #define GPLL_HZ (1188 * MHz) 18 #define AUPLL_HZ (983040000) 19 #define CPLL_HZ (1000 * MHz) 20 21 /* RV1126B pll id */ 22 enum rv1126b_pll_id { 23 GPLL, 24 AUPLL, 25 CPLL, 26 PLL_COUNT, 27 }; 28 29 struct rv1126b_clk_info { 30 unsigned long id; 31 char *name; 32 bool is_cru; 33 }; 34 35 struct rv1126b_clk_priv { 36 struct rv1126b_cru *cru; 37 struct rv1126b_grf *grf; 38 ulong gpll_hz; 39 ulong aupll_hz; 40 ulong cpll_hz; 41 ulong armclk_hz; 42 ulong armclk_enter_hz; 43 ulong armclk_init_hz; 44 bool sync_kernel; 45 bool set_armclk_rate; 46 }; 47 48 struct rv1126b_grf_clk_priv { 49 struct rv1126b_grf *grf; 50 }; 51 52 struct rv1126b_pll { 53 unsigned int con0; 54 unsigned int con1; 55 unsigned int con2; 56 unsigned int con3; 57 unsigned int con4; 58 unsigned int reserved0[3]; 59 }; 60 61 struct rv1126b_cru { 62 struct rv1126b_pll pll[2]; 63 unsigned int reserved0[176]; 64 unsigned int clksel_con[71]; 65 unsigned int reserved1[249]; 66 unsigned int clkgate_con[16]; 67 unsigned int reserved2[112]; 68 unsigned int softrst_con[16]; 69 unsigned int reserved3[112]; 70 unsigned int glb_cnt_th; 71 unsigned int glb_rst_st; 72 unsigned int glb_srst_fst; 73 unsigned int glb_srst_snd; 74 unsigned int glb_rst_con[3]; 75 unsigned int reserved4[41]; 76 unsigned int clk_cm_frac0_div_h; 77 unsigned int clk_cm_frac1_div_h; 78 unsigned int clk_cm_frac2_div_h; 79 unsigned int clk_uart_frac0_div_h; 80 unsigned int clk_uart_frac1_div_h; 81 unsigned int clk_audio_frac0_div_h; 82 unsigned int clk_audio_frac1_div_h; 83 unsigned int reserved5[15753]; 84 unsigned int bus_clksel_con[4]; 85 unsigned int reserved6[316]; 86 unsigned int bus_clkgate_con[7]; 87 unsigned int reserved7[121]; 88 unsigned int bus_softrst_con[8]; 89 unsigned int reserved8[15928]; 90 unsigned int peri_clksel_con[2]; 91 unsigned int reserved9[318]; 92 unsigned int peri_clkgate_con[2]; 93 unsigned int reserved10[126]; 94 unsigned int peri_softrst_con[2]; 95 unsigned int reserved11[15934]; 96 unsigned int core_clksel_con[3]; 97 unsigned int reserved12[317]; 98 unsigned int core_clkgate_con[2]; 99 unsigned int reserved13[126]; 100 unsigned int core_softrst_con[2]; 101 unsigned int reserved14[15934]; 102 unsigned int pmu_clksel_con[9]; 103 unsigned int reserved15[311]; 104 unsigned int pmu_clkgate_con[4]; 105 unsigned int reserved16[124]; 106 unsigned int pmu_softrst_con[4]; 107 unsigned int reserved17[15932]; 108 unsigned int pmu1_clksel_con[2]; 109 unsigned int reserved18[318]; 110 unsigned int pmu1_clkgate_con[2]; 111 unsigned int reserved19[126]; 112 unsigned int pmu1_softrst_con[2]; 113 unsigned int reserved20[32318]; 114 unsigned int vi_clksel_con[1]; 115 unsigned int reserved21[319]; 116 unsigned int vi_clkgate_con[5]; 117 unsigned int reserved22[123]; 118 unsigned int vi_softrst_con[4]; 119 }; 120 121 check_member(rv1126b_cru, clksel_con[0], 0x300); 122 check_member(rv1126b_cru, clkgate_con[0], 0x800); 123 check_member(rv1126b_cru, softrst_con[0], 0xa00); 124 check_member(rv1126b_cru, clk_cm_frac0_div_h, 0xcc0); 125 check_member(rv1126b_cru, bus_clksel_con[0], 0x10300); 126 check_member(rv1126b_cru, bus_clkgate_con[0], 0x10800); 127 check_member(rv1126b_cru, bus_softrst_con[0], 0x10a00); 128 check_member(rv1126b_cru, peri_clksel_con[0], 0x20300); 129 check_member(rv1126b_cru, peri_clkgate_con[0], 0x20800); 130 check_member(rv1126b_cru, peri_softrst_con[0], 0x20a00); 131 check_member(rv1126b_cru, core_clksel_con[0], 0x30300); 132 check_member(rv1126b_cru, core_clkgate_con[0], 0x30800); 133 check_member(rv1126b_cru, core_softrst_con[0], 0x30a00); 134 check_member(rv1126b_cru, pmu_clksel_con[0], 0x40300); 135 check_member(rv1126b_cru, pmu_clkgate_con[0], 0x40800); 136 check_member(rv1126b_cru, pmu_softrst_con[0], 0x40a00); 137 check_member(rv1126b_cru, pmu1_clksel_con[0], 0x50300); 138 check_member(rv1126b_cru, pmu1_clkgate_con[0], 0x50800); 139 check_member(rv1126b_cru, pmu1_softrst_con[0], 0x50a00); 140 check_member(rv1126b_cru, vi_clksel_con[0], 0x70300); 141 check_member(rv1126b_cru, vi_clkgate_con[0], 0x70800); 142 check_member(rv1126b_cru, vi_softrst_con[0], 0x70a00); 143 144 struct pll_rate_table { 145 unsigned long rate; 146 unsigned int fbdiv; 147 unsigned int postdiv1; 148 unsigned int refdiv; 149 unsigned int postdiv2; 150 unsigned int dsmpd; 151 unsigned int frac; 152 }; 153 154 #define RV1126B_CRU_BASE 0x20000000 155 #define RV1126B_TOPCRU_BASE 0x0 156 #define RV1126B_BUSCRU_BASE 0x10000 157 #define RV1126B_PERICRU_BASE 0x20000 158 #define RV1126B_CORECRU_BASE 0x30000 159 #define RV1126B_PMUCRU_BASE 0x40000 160 #define RV1126B_PMU1CRU_BASE 0x50000 161 #define RV1126B_DDRCRU_BASE 0x60000 162 #define RV1126B_SUBDDRCRU_BASE 0x68000 163 #define RV1126B_VICRU_BASE 0x70000 164 #define RV1126B_VEPUCRU_BASE 0x80000 165 #define RV1126B_NPUCRU_BASE 0x90000 166 #define RV1126B_VDOCRU_BASE 0xA0000 167 #define RV1126B_VCPCRU_BASE 0xB0000 168 #define RV1126B_SBUSCRU_BASE 0x200000 169 170 #define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE) 171 #define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE) 172 #define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE) 173 #define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE) 174 #define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE) 175 #define RV1126B_SBUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SBUSCRU_BASE) 176 177 enum { 178 /* CRU_CLK_SEL10_CON */ 179 CLK_AUDIO_FRAC1_SRC_SEL_SHIFT = 12, 180 CLK_AUDIO_FRAC1_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC1_SRC_SEL_SHIFT, 181 CLK_AUDIO_FRAC0_SRC_SEL_SHIFT = 10, 182 CLK_AUDIO_FRAC0_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT, 183 CLK_UART_FRAC1_SRC_SEL_SHIFT = 8, 184 CLK_UART_FRAC1_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC1_SRC_SEL_SHIFT, 185 CLK_UART_FRAC0_SRC_SEL_SHIFT = 6, 186 CLK_UART_FRAC0_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC0_SRC_SEL_SHIFT, 187 CLK_CM_FRAC2_SRC_SEL_SHIFT = 4, 188 CLK_CM_FRAC2_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC2_SRC_SEL_SHIFT, 189 CLK_CM_FRAC1_SRC_SEL_SHIFT = 2, 190 CLK_CM_FRAC1_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC1_SRC_SEL_SHIFT, 191 CLK_CM_FRAC0_SRC_SEL_SHIFT = 0, 192 CLK_CM_FRAC0_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC0_SRC_SEL_SHIFT, 193 CLK_FRAC_SRC_SEL_24M = 0, 194 CLK_FRAC_SRC_SEL_GPLL, 195 CLK_FRAC_SRC_SEL_AUPLL, 196 CLK_FRAC_SRC_SEL_CPLL, 197 198 /* CRU_CLK_SEL12_CON */ 199 SCLK_UART1_SEL_SHIFT = 13, 200 SCLK_UART1_SEL_MASK = 0x7 << SCLK_UART1_SEL_SHIFT, 201 SCLK_UART1_DIV_SHIFT = 8, 202 SCLK_UART1_DIV_MASK = 0x1f << SCLK_UART1_DIV_SHIFT, 203 SCLK_UART0_SRC_SEL_SHIFT = 5, 204 SCLK_UART0_SRC_SEL_MASK = 0x7 << SCLK_UART0_SRC_SEL_SHIFT, 205 SCLK_UART_SEL_OSC = 0, 206 SCLK_UART_SEL_CM_FRAC0, 207 SCLK_UART_SEL_CM_FRAC1, 208 SCLK_UART_SEL_CM_FRAC2, 209 SCLK_UART_SEL_UART_FRAC0, 210 SCLK_UART_SEL_UART_FRAC1, 211 SCLK_UART0_SRC_DIV_SHIFT = 0, 212 SCLK_UART0_SRC_DIV_MASK = 0x1f << SCLK_UART0_SRC_DIV_SHIFT, 213 214 /* CRU_CLK_SEL13_CON */ 215 SCLK_UART3_SEL_SHIFT = 13, 216 SCLK_UART3_SEL_MASK = 0x7 << SCLK_UART3_SEL_SHIFT, 217 SCLK_UART3_DIV_SHIFT = 8, 218 SCLK_UART3_DIV_MASK = 0x1f << SCLK_UART3_DIV_SHIFT, 219 SCLK_UART2_SEL_SHIFT = 5, 220 SCLK_UART2_SEL_MASK = 0x7 << SCLK_UART2_SEL_SHIFT, 221 SCLK_UART2_DIV_SHIFT = 0, 222 SCLK_UART2_DIV_MASK = 0x1f << SCLK_UART2_DIV_SHIFT, 223 224 /* CRU_CLK_SEL14_CON */ 225 SCLK_UART5_SEL_SHIFT = 13, 226 SCLK_UART5_SEL_MASK = 0x7 << SCLK_UART5_SEL_SHIFT, 227 SCLK_UART5_DIV_SHIFT = 8, 228 SCLK_UART5_DIV_MASK = 0x1f << SCLK_UART5_DIV_SHIFT, 229 SCLK_UART4_SEL_SHIFT = 5, 230 SCLK_UART4_SEL_MASK = 0x7 << SCLK_UART4_SEL_SHIFT, 231 SCLK_UART4_DIV_SHIFT = 0, 232 SCLK_UART4_DIV_MASK = 0x1f << SCLK_UART4_DIV_SHIFT, 233 234 /* CRU_CLK_SEL15_CON */ 235 SCLK_UART7_SEL_SHIFT = 13, 236 SCLK_UART7_SEL_MASK = 0x7 << SCLK_UART7_SEL_SHIFT, 237 SCLK_UART7_DIV_SHIFT = 8, 238 SCLK_UART7_DIV_MASK = 0x1f << SCLK_UART7_DIV_SHIFT, 239 SCLK_UART6_SEL_SHIFT = 5, 240 SCLK_UART6_SEL_MASK = 0x7 << SCLK_UART6_SEL_SHIFT, 241 SCLK_UART6_DIV_SHIFT = 0, 242 SCLK_UART6_DIV_MASK = 0x1f << SCLK_UART6_DIV_SHIFT, 243 244 /* CRU_CLK_SEL25_CON */ 245 CLK_FRAC_NUMERATOR_SHIFT = 16, 246 CLK_FRAC_NUMERATOR_MASK = 0xffff << 16, 247 CLK_FRAC_DENOMINATOR_SHIFT = 0, 248 CLK_FRAC_DENOMINATOR_MASK = 0xffff, 249 CLK_FRAC_H_NUMERATOR_SHIFT = 8, 250 CLK_FRAC_H_NUMERATOR_MASK = 0xff << 8, 251 CLK_FRAC_H_DENOMINATOR_SHIFT = 0, 252 CLK_FRAC_H_DENOMINATOR_MASK = 0xff, 253 254 /* CRU_CLK_SEL43_CON */ 255 DCLK_VOP_SEL_SHIFT = 8, 256 DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, 257 DCLK_VOP_SEL_GPLL = 0, 258 DCLK_VOP_SEL_CPLL, 259 DCLK_VOP_DIV_SHIFT = 0, 260 DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT, 261 262 /* CRU_CLK_SEL44_CON */ 263 HCLK_BUS_SEL_SHIFT = 10, 264 HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT, 265 HCLK_BUS_SEL_200M = 0, 266 HCLK_BUS_SEL_100M, 267 ACLK_BUS_SEL_SHIFT = 8, 268 ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 269 ACLK_BUS_SEL_400M = 0, 270 ACLK_BUS_SEL_300M, 271 ACLK_BUS_SEL_200M, 272 ACLK_TOP_SEL_SHIFT = 6, 273 ACLK_TOP_SEL_MASK = 0x3 << ACLK_TOP_SEL_SHIFT, 274 ACLK_TOP_SEL_600M = 0, 275 ACLK_TOP_SEL_400M, 276 ACLK_TOP_SEL_200M, 277 278 /* CRU_CLK_SEL45_CON */ 279 CLK_GMAC_PTP_REF_SRC_DIV_SHIFT = 11, 280 CLK_GMAC_PTP_REF_SRC_DIV_MASK = 0x1f << CLK_GMAC_PTP_REF_SRC_DIV_SHIFT, 281 CLK_GMAC_PTP_REF_SRC_SEL_SHIFT = 10, 282 CLK_GMAC_PTP_REF_SRC_SEL_MASK = 0x1 << CLK_GMAC_PTP_REF_SRC_SEL_SHIFT, 283 CLK_GMAC_PTP_REF_SRC_SEL_CPLL = 0, 284 CLK_GMAC_PTP_REF_SRC_SEL_24M, 285 CLK_SDMMC_SEL_SHIFT = 8, 286 CLK_SDMMC_SEL_MASK = 0x3 << CLK_SDMMC_SEL_SHIFT, 287 CLK_SDMMC_SEL_GPLL = 0, 288 CLK_SDMMC_SEL_CPLL, 289 CLK_SDMMC_SEL_24M, 290 CLK_SDMMC_DIV_SHIFT = 0, 291 CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT, 292 293 /* CRU_CLK_SEL46_CON */ 294 TCLK_WDT_HPMCU_SEL_SHIFT = 14, 295 TCLK_WDT_HPMCU_SEL_MASK = 0x1 << TCLK_WDT_HPMCU_SEL_SHIFT, 296 TCLK_WDT_S_SEL_SHIFT = 13, 297 TCLK_WDT_S_SEL_MASK = 0x1 << TCLK_WDT_S_SEL_SHIFT, 298 TCLK_WDT_NS_SEL_SHIFT = 12, 299 TCLK_WDT_NS_SEL_MASK = 0x1 << TCLK_WDT_NS_SEL_SHIFT, 300 TCLK_WDT_SEL_100M = 0, 301 TCLK_WDT_SEL_OSC, 302 303 /* CRU_CLK_SEL47_CON */ 304 ACLK_PERI_SEL_SHIFT = 13, 305 ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT, 306 ACLK_PERI_SEL_200M = 0, 307 ACLK_PERI_SEL_24M, 308 PCLK_PERI_SEL_SHIFT = 12, 309 PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT, 310 PCLK_PERI_SEL_100M = 0, 311 PCLK_PERI_SEL_24M, 312 313 /* CRU_CLK_SEL50_CON */ 314 ACLK_RKCE_SEL_SHIFT = 13, 315 ACLK_RKCE_SEL_MASK = 0x1 << ACLK_RKCE_SEL_SHIFT, 316 ACLK_RKCE_SEL_200M = 0, 317 ACLK_RKCE_SEL_24M, 318 CLK_PKA_RKCE_SEL_SHIFT = 12, 319 CLK_PKA_RKCE_SEL_MASK = 0x1 << CLK_PKA_RKCE_SEL_SHIFT, 320 CLK_PKA_RKCE_SEL_300M = 0, 321 CLK_PKA_RKCE_SEL_200M, 322 CLK_PWM3_SEL_SHIFT = 11, 323 CLK_PWM3_SEL_MASK = 0x1 << CLK_PWM3_SEL_SHIFT, 324 CLK_PWM2_SEL_SHIFT = 10, 325 CLK_PWM2_SEL_MASK = 0x1 << CLK_PWM2_SEL_SHIFT, 326 CLK_PWM0_SEL_SHIFT = 8, 327 CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT, 328 CLK_PWM_SEL_100M = 0, 329 CLK_PWM_SEL_24M, 330 CLK_SPI1_SEL_SHIFT = 4, 331 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 332 CLK_SPI0_SEL_SHIFT = 2, 333 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 334 CLK_SPI0_SEL_200M = 0, 335 CLK_SPI0_SEL_100M, 336 CLK_SPI0_SEL_50M, 337 CLK_SPI0_SEL_24M, 338 CLK_I2C_SEL_SHIFT = 1, 339 CLK_I2C_SEL_MASK = 0x1 << CLK_I2C_SEL_SHIFT, 340 CLK_I2C_SEL_200M = 0, 341 CLK_I2C_SEL_24M, 342 343 /* CRU_CLK_SEL63_CON */ 344 CLK_SARADC2_SEL_SHIFT = 14, 345 CLK_SARADC2_SEL_MASK = 0x1 << CLK_SARADC2_SEL_SHIFT, 346 CLK_SARADC1_SEL_SHIFT = 13, 347 CLK_SARADC1_SEL_MASK = 0x1 << CLK_SARADC1_SEL_SHIFT, 348 CLK_SARADC0_SEL_SHIFT = 12, 349 CLK_SARADC0_SEL_MASK = 0x1 << CLK_SARADC0_SEL_SHIFT, 350 CLK_SARADC_SEL_200M = 0, 351 CLK_SARADC_SEL_24M, 352 CLK_SARADC2_DIV_SHIFT = 8, 353 CLK_SARADC2_DIV_MASK = 0x7 << CLK_SARADC2_DIV_SHIFT, 354 CLK_SARADC1_DIV_SHIFT = 4, 355 CLK_SARADC1_DIV_MASK = 0x7 << CLK_SARADC1_DIV_SHIFT, 356 CLK_SARADC0_DIV_SHIFT = 0, 357 CLK_SARADC0_DIV_MASK = 0x7 << CLK_SARADC0_DIV_SHIFT, 358 359 /* CRU_CLK_SEL69_CON */ 360 CLK_MAC_OUT2IO_DIV_SHIFT = 8, 361 CLK_MAC_OUT2IO_DIV_MASK = 0x7f << CLK_MAC_OUT2IO_DIV_SHIFT, 362 CLK_MAC_OUT2IO_SEL_SHIFT = 6, 363 CLK_MAC_OUT2IO_SEL_MASK = 0x3 << CLK_MAC_OUT2IO_SEL_SHIFT, 364 CLK_MAC_OUT2IO_SEL_GPLL = 0, 365 CLK_MAC_OUT2IO_SEL_CPLL, 366 CLK_MAC_OUT2IO_SEL_24M, 367 368 /* PMUCRU_CLK_SEL2_CON */ 369 CLK_I2C2_SEL_SHIFT = 14, 370 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 371 CLK_I2C2_SEL_24M = 0, 372 CLK_I2C2_SEL_RCOSC, 373 CLK_I2C2_SEL_100M, 374 CLK_PWM1_SEL_SHIFT = 8, 375 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 376 CLK_PWM1_SEL_24M = 0, 377 CLK_PWM1_SEL_RCOSC, 378 CLK_PWM1_SEL_100M, 379 CLK_PWM1_DIV_SHIFT = 6, 380 CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT, 381 382 /* PMUCRU_CLK_SEL3_CON */ 383 TCLK_WDT_LPMCU_SEL_SHIFT = 6, 384 TCLK_WDT_LPMCU_SEL_MASK = 0x3 << TCLK_WDT_LPMCU_SEL_SHIFT, 385 TCLK_WDT_LPMCU_SEL_OSC = 0, 386 TCLK_WDT_LPMCU_SEL_RCOSC, 387 TCLK_WDT_LPMCU_SEL_100M, 388 TCLK_WDT_LPMCU_SEL_32K, 389 SCLK_UART0_SEL_SHIFT = 0, 390 SCLK_UART0_SEL_MASK = 0x3 << SCLK_UART0_SEL_SHIFT, 391 SCLK_UART0_SEL_UART0_SRC = 0, 392 SCLK_UART0_SEL_OSC, 393 SCLK_UART0_SEL_RCOSC, 394 395 /* PMU1CRU_CLK_SEL0_CON */ 396 SCLK_1X_FSPI1_DIV_SHIFT = 2, 397 SCLK_1X_FSPI1_DIV_MASK = 0x7 << SCLK_1X_FSPI1_DIV_SHIFT, 398 SCLK_1X_FSPI1_SEL_SHIFT = 0, 399 SCLK_1X_FSPI1_SEL_MASK = 0x3 << SCLK_1X_FSPI1_SEL_SHIFT, 400 SCLK_1X_FSPI1_SEL_24M = 0, 401 SCLK_1X_FSPI1_SEL_RCOSC, 402 SCLK_1X_FSPI1_SEL_100M, 403 }; 404 #endif 405