1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip CIF Driver 4 * 5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _RKCIF_REGS_H 9 #define _RKCIF_REGS_H 10 11 struct cif_reg { 12 u32 offset; 13 }; 14 15 #define CIF_REG(_offset) { .offset = (_offset), } 16 17 enum cif_reg_index { 18 /* dvp registers index */ 19 CIF_REG_DVP_CTRL = 0x0, 20 CIF_REG_DVP_INTEN, 21 CIF_REG_DVP_INTSTAT, 22 CIF_REG_DVP_FOR, 23 CIF_REG_DVP_LINE_NUM_ADDR, 24 CIF_REG_DVP_DMA_IDLE_REQ, 25 CIF_REG_DVP_MULTI_ID, 26 CIF_REG_DVP_FRM0_ADDR_Y, 27 CIF_REG_DVP_FRM0_ADDR_UV, 28 CIF_REG_DVP_FRM1_ADDR_Y, 29 CIF_REG_DVP_FRM1_ADDR_UV, 30 CIF_REG_DVP_VIR_LINE_WIDTH, 31 CIF_REG_DVP_SET_SIZE, 32 CIF_REG_DVP_SCM_ADDR_Y, 33 CIF_REG_DVP_SCM_ADDR_U, 34 CIF_REG_DVP_SCM_ADDR_V, 35 CIF_REG_DVP_WB_UP_FILTER, 36 CIF_REG_DVP_WB_LOW_FILTER, 37 CIF_REG_DVP_WBC_CNT, 38 CIF_REG_DVP_LINE_INT_NUM, 39 CIF_REG_DVP_LINE_CNT, 40 CIF_REG_DVP_CROP, 41 CIF_REG_DVP_SCL_CTRL, 42 CIF_REG_DVP_SCL_DST, 43 CIF_REG_DVP_SCL_FCT, 44 CIF_REG_DVP_SCL_VALID_NUM, 45 CIF_REG_DVP_LINE_LOOP_CTRL, 46 CIF_REG_DVP_PATH_SEL, 47 CIF_REG_DVP_FIFO_ENTRY, 48 CIF_REG_DVP_FRAME_STATUS, 49 CIF_REG_DVP_CUR_DST, 50 CIF_REG_DVP_LAST_LINE, 51 CIF_REG_DVP_LAST_PIX, 52 CIF_REG_DVP_FRM0_ADDR_Y_ID1, 53 CIF_REG_DVP_FRM0_ADDR_UV_ID1, 54 CIF_REG_DVP_FRM1_ADDR_Y_ID1, 55 CIF_REG_DVP_FRM1_ADDR_UV_ID1, 56 CIF_REG_DVP_FRM0_ADDR_Y_ID2, 57 CIF_REG_DVP_FRM0_ADDR_UV_ID2, 58 CIF_REG_DVP_FRM1_ADDR_Y_ID2, 59 CIF_REG_DVP_FRM1_ADDR_UV_ID2, 60 CIF_REG_DVP_FRM0_ADDR_Y_ID3, 61 CIF_REG_DVP_FRM0_ADDR_UV_ID3, 62 CIF_REG_DVP_FRM1_ADDR_Y_ID3, 63 CIF_REG_DVP_FRM1_ADDR_UV_ID3, 64 CIF_REG_DVP_SAV_EAV, 65 CIF_REG_DVP_LINE_CNT1, 66 CIF_REG_DVP_LINE_INT_NUM1, 67 /* mipi & lvds registers index */ 68 CIF_REG_MIPI_LVDS_ID0_CTRL0, 69 CIF_REG_MIPI_LVDS_ID0_CTRL1, 70 CIF_REG_MIPI_LVDS_ID1_CTRL0, 71 CIF_REG_MIPI_LVDS_ID1_CTRL1, 72 CIF_REG_MIPI_LVDS_ID2_CTRL0, 73 CIF_REG_MIPI_LVDS_ID2_CTRL1, 74 CIF_REG_MIPI_LVDS_ID3_CTRL0, 75 CIF_REG_MIPI_LVDS_ID3_CTRL1, 76 CIF_REG_MIPI_WATER_LINE, 77 CIF_REG_MIPI_LVDS_CTRL, 78 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0, 79 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0, 80 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0, 81 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0, 82 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0, 83 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0, 84 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0, 85 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0, 86 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1, 87 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1, 88 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1, 89 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1, 90 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1, 91 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1, 92 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1, 93 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1, 94 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2, 95 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2, 96 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2, 97 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2, 98 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2, 99 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2, 100 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2, 101 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2, 102 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3, 103 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3, 104 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3, 105 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3, 106 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3, 107 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3, 108 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3, 109 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3, 110 CIF_REG_MIPI_LVDS_INTEN, 111 CIF_REG_MIPI_LVDS_INTSTAT, 112 CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1, 113 CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3, 114 CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1, 115 CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3, 116 CIF_REG_MIPI_LVDS_ID0_CROP_START, 117 CIF_REG_MIPI_LVDS_ID1_CROP_START, 118 CIF_REG_MIPI_LVDS_ID2_CROP_START, 119 CIF_REG_MIPI_LVDS_ID3_CROP_START, 120 CIF_REG_MIPI_FRAME_NUM_VC0, 121 CIF_REG_MIPI_FRAME_NUM_VC1, 122 CIF_REG_MIPI_FRAME_NUM_VC2, 123 CIF_REG_MIPI_FRAME_NUM_VC3, 124 CIF_REG_LVDS_SAV_EAV_ACT0_ID0, 125 CIF_REG_LVDS_SAV_EAV_BLK0_ID0, 126 CIF_REG_LVDS_SAV_EAV_ACT1_ID0, 127 CIF_REG_LVDS_SAV_EAV_BLK1_ID0, 128 CIF_REG_LVDS_SAV_EAV_ACT0_ID1, 129 CIF_REG_LVDS_SAV_EAV_BLK0_ID1, 130 CIF_REG_LVDS_SAV_EAV_ACT1_ID1, 131 CIF_REG_LVDS_SAV_EAV_BLK1_ID1, 132 CIF_REG_LVDS_SAV_EAV_ACT0_ID2, 133 CIF_REG_LVDS_SAV_EAV_BLK0_ID2, 134 CIF_REG_LVDS_SAV_EAV_ACT1_ID2, 135 CIF_REG_LVDS_SAV_EAV_BLK1_ID2, 136 CIF_REG_LVDS_SAV_EAV_ACT0_ID3, 137 CIF_REG_LVDS_SAV_EAV_BLK0_ID3, 138 CIF_REG_LVDS_SAV_EAV_ACT1_ID3, 139 CIF_REG_LVDS_SAV_EAV_BLK1_ID3, 140 CIF_REG_MIPI_EFFECT_CODE_ID0, 141 CIF_REG_MIPI_EFFECT_CODE_ID1, 142 CIF_REG_MIPI_EFFECT_CODE_ID2, 143 CIF_REG_MIPI_EFFECT_CODE_ID3, 144 CIF_REG_LVDS_ID0_CTRL0, 145 CIF_REG_LVDS_ID1_CTRL0, 146 CIF_REG_LVDS_ID2_CTRL0, 147 CIF_REG_LVDS_ID3_CTRL0, 148 CIF_REG_MIPI_ON_PAD, 149 150 CIF_REG_Y_STAT_CONTROL, 151 CIF_REG_Y_STAT_VALUE, 152 CIF_REG_MMU_DTE_ADDR, 153 CIF_REG_MMU_STATUS, 154 CIF_REG_MMU_COMMAND, 155 CIF_REG_MMU_PAGE_FAULT_ADDR, 156 CIF_REG_MMU_ZAP_ONE_LINE, 157 CIF_REG_MMU_INT_RAWSTAT, 158 CIF_REG_MMU_INT_CLEAR, 159 CIF_REG_MMU_INT_MASK, 160 CIF_REG_MMU_INT_STATUS, 161 CIF_REG_MMU_AUTO_GATING, 162 /* reg belowed is in grf */ 163 CIF_REG_GRF_CIFIO_CON, 164 CIF_REG_GRF_CIFIO_CON1, 165 CIF_REG_GRF_CIFIO_VENC, 166 /* reg global control */ 167 CIF_REG_GLB_CTRL, 168 CIF_REG_GLB_INTEN, 169 CIF_REG_GLB_INTST, 170 CIF_REG_SCL_CH_CTRL, 171 CIF_REG_SCL_CTRL, 172 CIF_REG_SCL_FRM0_ADDR_CH0, 173 CIF_REG_SCL_FRM1_ADDR_CH0, 174 CIF_REG_SCL_VLW_CH0, 175 CIF_REG_SCL_FRM0_ADDR_CH1, 176 CIF_REG_SCL_FRM1_ADDR_CH1, 177 CIF_REG_SCL_VLW_CH1, 178 CIF_REG_SCL_FRM0_ADDR_CH2, 179 CIF_REG_SCL_FRM1_ADDR_CH2, 180 CIF_REG_SCL_VLW_CH2, 181 CIF_REG_SCL_FRM0_ADDR_CH3, 182 CIF_REG_SCL_FRM1_ADDR_CH3, 183 CIF_REG_SCL_VLW_CH3, 184 CIF_REG_SCL_BLC_CH0, 185 CIF_REG_SCL_BLC_CH1, 186 CIF_REG_SCL_BLC_CH2, 187 CIF_REG_SCL_BLC_CH3, 188 CIF_REG_TOISP0_CTRL, 189 CIF_REG_TOISP0_SIZE, 190 CIF_REG_TOISP0_CROP, 191 CIF_REG_TOISP1_CTRL, 192 CIF_REG_TOISP1_SIZE, 193 CIF_REG_TOISP1_CROP, 194 CIF_REG_INDEX_MAX 195 }; 196 197 /* CIF Reg Offset */ 198 #define CIF_CTRL 0x00 199 #define CIF_INTEN 0x04 200 #define CIF_INTSTAT 0x08 201 #define CIF_FOR 0x0c 202 #define CIF_LINE_NUM_ADDR 0x10 203 #define CIF_DMA_IDLE_REQ 0x10 204 #define CIF_FRM0_ADDR_Y 0x14 205 #define CIF_FRM0_ADDR_UV 0x18 206 #define CIF_FRM1_ADDR_Y 0x1c 207 #define CIF_FRM1_ADDR_UV 0x20 208 #define CIF_VIR_LINE_WIDTH 0x24 209 #define CIF_SET_SIZE 0x28 210 #define CIF_SCM_ADDR_Y 0x2c 211 #define CIF_LINE_INT_NUM 0x2c 212 #define CIF_SCM_ADDR_U 0x30 213 #define CIF_LINE_CNT 0x30 214 #define CIF_SCM_ADDR_V 0x34 215 #define CIF_WB_UP_FILTER 0x38 216 #define CIF_WB_LOW_FILTER 0x3c 217 #define CIF_WBC_CNT 0x40 218 #define CIF_CROP 0x44 219 #define RV1126_CIF_CROP 0x34 220 #define RK3568_CIF_FIFO_ENTRY 0x38 221 #define CIF_SCL_CTRL 0x48 222 #define CIF_PATH_SEL 0x48 223 #define CIF_SCL_DST 0x4c 224 #define CIF_SCL_FCT 0x50 225 #define CIF_SCL_VALID_NUM 0x54 226 #define CIF_FIFO_ENTRY 0x54 227 #define CIF_LINE_LOOP_CTR 0x58 228 #define CIF_FRAME_STATUS 0x60 229 #define RV1126_CIF_FRAME_STATUS 0x3c 230 #define CIF_CUR_DST 0x64 231 #define RV1126_CIF_CUR_DST 0x40 232 #define CIF_LAST_LINE 0x68 233 #define RV1126_CIF_LAST_LINE 0x44 234 #define CIF_LAST_PIX 0x6c 235 #define RV1126_CIF_LAST_PIX 0x48 236 #define CIF_MULTI_ID 0x10 237 #define CIF_FRM0_ADDR_Y_ID1 0x50 238 #define CIF_FRM0_ADDR_UV_ID1 0x54 239 #define CIF_FRM1_ADDR_Y_ID1 0x58 240 #define CIF_FRM1_ADDR_UV_ID1 0x5c 241 #define CIF_FRM0_ADDR_Y_ID2 0x60 242 #define CIF_FRM0_ADDR_UV_ID2 0x64 243 #define CIF_FRM1_ADDR_Y_ID2 0x68 244 #define CIF_FRM1_ADDR_UV_ID2 0x6c 245 #define CIF_FRM0_ADDR_Y_ID3 0x70 246 #define CIF_FRM0_ADDR_UV_ID3 0x74 247 #define CIF_FRM1_ADDR_Y_ID3 0x78 248 #define CIF_FRM1_ADDR_UV_ID3 0x7c 249 250 #define CIF_FETCH_Y_LAST_LINE(val) ((val) & 0x1fff) 251 /* Check if swap y and c in bt1120 mode */ 252 #define CIF_FETCH_IS_Y_FIRST(val) ((val >> 5) & 0x3) 253 #define CIF_RAW_STORED_BIT_WIDTH (16U) 254 #define CIF_RAW_STORED_BIT_WIDTH_RV1126 (8U) 255 #define CIF_YUV_STORED_BIT_WIDTH (8U) 256 257 /* RK1808 & RV1126 CIF CSI & LVDS Registers Offset */ 258 #define CIF_CSI_ID0_CTRL0 0x80 259 #define CIF_CSI_ID0_CTRL1 0x84 260 #define CIF_CSI_ID1_CTRL0 0x88 261 #define CIF_CSI_ID1_CTRL1 0x8c 262 #define CIF_CSI_ID2_CTRL0 0x90 263 #define CIF_CSI_ID2_CTRL1 0x94 264 #define CIF_CSI_ID3_CTRL0 0x98 265 #define CIF_CSI_ID3_CTRL1 0x9c 266 #define CIF_CSI_WATER_LINE 0xa0 267 #define CIF_CSI_MIPI_LVDS_CTRL 0xa0 268 #define CIF_CSI_FRM0_ADDR_Y_ID0 0xa4 269 #define CIF_CSI_FRM1_ADDR_Y_ID0 0xa8 270 #define CIF_CSI_FRM0_ADDR_UV_ID0 0xac 271 #define CIF_CSI_FRM1_ADDR_UV_ID0 0xb0 272 #define CIF_CSI_FRM0_VLW_Y_ID0 0xb4 273 #define CIF_CSI_FRM1_VLW_Y_ID0 0xb8 274 #define CIF_CSI_FRM0_VLW_UV_ID0 0xbc 275 #define CIF_CSI_FRM1_VLW_UV_ID0 0xc0 276 #define CIF_CSI_FRM0_ADDR_Y_ID1 0xc4 277 #define CIF_CSI_FRM1_ADDR_Y_ID1 0xc8 278 #define CIF_CSI_FRM0_ADDR_UV_ID1 0xcc 279 #define CIF_CSI_FRM1_ADDR_UV_ID1 0xd0 280 #define CIF_CSI_FRM0_VLW_Y_ID1 0xd4 281 #define CIF_CSI_FRM1_VLW_Y_ID1 0xd8 282 #define CIF_CSI_FRM0_VLW_UV_ID1 0xdc 283 #define CIF_CSI_FRM1_VLW_UV_ID1 0xe0 284 #define CIF_CSI_FRM0_ADDR_Y_ID2 0xe4 285 #define CIF_CSI_FRM1_ADDR_Y_ID2 0xe8 286 #define CIF_CSI_FRM0_ADDR_UV_ID2 0xec 287 #define CIF_CSI_FRM1_ADDR_UV_ID2 0xf0 288 #define CIF_CSI_FRM0_VLW_Y_ID2 0xf4 289 #define CIF_CSI_FRM1_VLW_Y_ID2 0xf8 290 #define CIF_CSI_FRM0_VLW_UV_ID2 0xfc 291 #define CIF_CSI_FRM1_VLW_UV_ID2 0x100 292 #define CIF_CSI_FRM0_ADDR_Y_ID3 0x104 293 #define CIF_CSI_FRM1_ADDR_Y_ID3 0x108 294 #define CIF_CSI_FRM0_ADDR_UV_ID3 0x10c 295 #define CIF_CSI_FRM1_ADDR_UV_ID3 0x110 296 #define CIF_CSI_FRM0_VLW_Y_ID3 0x114 297 #define CIF_CSI_FRM1_VLW_Y_ID3 0x118 298 #define CIF_CSI_FRM0_VLW_UV_ID3 0x11c 299 #define CIF_CSI_FRM1_VLW_UV_ID3 0x120 300 #define CIF_CSI_INTEN 0x124 301 #define CIF_CSI_INTSTAT 0x128 302 #define CIF_CSI_LINE_INT_NUM_ID0_1 0x12c 303 #define CIF_CSI_LINE_INT_NUM_ID2_3 0x130 304 #define CIF_CSI_LINE_CNT_ID0_1 0x134 305 #define CIF_CSI_LINE_CNT_ID2_3 0x138 306 #define CIF_CSI_ID0_CROP_START 0x13c 307 #define CIF_CSI_ID1_CROP_START 0x140 308 #define CIF_CSI_ID2_CROP_START 0x144 309 #define CIF_CSI_ID3_CROP_START 0x148 310 #define CIF_CSI_FRAME_NUM_VC0 0x14c 311 #define CIF_CSI_FRAME_NUM_VC1 0x150 312 #define CIF_CSI_FRAME_NUM_VC2 0x154 313 #define CIF_CSI_FRAME_NUM_VC3 0x158 314 #define CIF_LVDS_SAV_EAV_ACT0_ID0 0x150 315 #define CIF_LVDS_SAV_EAV_BLK0_ID0 0x154 316 #define CIF_LVDS_SAV_EAV_ACT1_ID0 0x158 317 #define CIF_LVDS_SAV_EAV_BLK1_ID0 0x15c 318 #define CIF_LVDS_SAV_EAV_ACT0_ID1 0x160 319 #define CIF_LVDS_SAV_EAV_BLK0_ID1 0x164 320 #define CIF_LVDS_SAV_EAV_ACT1_ID1 0x168 321 #define CIF_LVDS_SAV_EAV_BLK1_ID1 0x16c 322 #define CIF_LVDS_SAV_EAV_ACT0_ID2 0x170 323 #define CIF_LVDS_SAV_EAV_BLK0_ID2 0x174 324 #define CIF_LVDS_SAV_EAV_ACT1_ID2 0x178 325 #define CIF_LVDS_SAV_EAV_BLK1_ID2 0x17c 326 #define CIF_LVDS_SAV_EAV_ACT0_ID3 0x180 327 #define CIF_LVDS_SAV_EAV_BLK0_ID3 0x184 328 #define CIF_LVDS_SAV_EAV_ACT1_ID3 0x188 329 #define CIF_LVDS_SAV_EAV_BLK1_ID3 0x18c 330 #define CIF_Y_STAT_CONTROL 0x190 331 #define CIF_Y_STAT_VALUE 0x194 332 #define CIF_MMU_DTE_ADDR 0x800 333 #define CIF_MMU_STATUS 0x804 334 #define CIF_MMU_COMMAND 0x808 335 #define CIF_MMU_PAGE_FAULT_ADDR 0x80c 336 #define CIF_MMU_ZAP_ONE_LINE 0x810 337 #define CIF_MMU_INT_RAWSTAT 0x814 338 #define CIF_MMU_INT_CLEAR 0x818 339 #define CIF_MMU_INT_MASK 0x81c 340 #define CIF_MMU_INT_STATUS 0x820 341 #define CIF_MMU_AUTO_GATING 0x824 342 343 /* RK3588 DVP Registers Offset */ 344 #define DVP_CTRL 0x10 345 #define DVP_INTEN 0x14 346 #define DVP_INTSTAT 0x18 347 #define DVP_FOR 0x1C 348 #define DVP_MULTI_ID 0x20 349 #define DVP_SAV_EAV 0x24 350 #define DVP_CROP_SIZE 0x28 351 #define DVP_CROP 0x2C 352 #define DVP_FRM0_ADDR_Y_ID0 0x30 353 #define DVP_FRM0_ADDR_UV_ID0 0x34 354 #define DVP_FRM1_ADDR_Y_ID0 0x38 355 #define DVP_FRM1_ADDR_UV_ID0 0x3C 356 #define DVP_FRM0_ADDR_Y_ID1 0x40 357 #define DVP_FRM0_ADDR_UV_ID1 0x44 358 #define DVP_FRM1_ADDR_Y_ID1 0x48 359 #define DVP_FRM1_ADDR_UV_ID1 0x4C 360 #define DVP_FRM0_ADDR_Y_ID2 0x50 361 #define DVP_FRM0_ADDR_UV_ID2 0x54 362 #define DVP_FRM1_ADDR_Y_ID2 0x58 363 #define DVP_FRM1_ADDR_UV_ID2 0x5C 364 #define DVP_FRM0_ADDR_Y_ID3 0x60 365 #define DVP_FRM0_ADDR_UV_ID3 0x64 366 #define DVP_FRM1_ADDR_Y_ID3 0x68 367 #define DVP_FRM1_ADDR_UV_ID3 0x6C 368 #define DVP_VIR_LINE_WIDTH 0x70 369 #define DVP_LINE_INT_NUM_01 0x74 370 #define DVP_LINE_INT_NUM_23 0x78 371 #define DVP_LINE_CNT_01 0x7C 372 #define DVP_LINE_CNT_23 0x80 373 374 /* RK3588 CSI Registers Offset */ 375 #define CSI_MIPI0_ID0_CTRL0 0x100 376 #define CSI_MIPI0_ID0_CTRL1 0x104 377 #define CSI_MIPI0_ID1_CTRL0 0x108 378 #define CSI_MIPI0_ID1_CTRL1 0x10C 379 #define CSI_MIPI0_ID2_CTRL0 0x110 380 #define CSI_MIPI0_ID2_CTRL1 0x114 381 #define CSI_MIPI0_ID3_CTRL0 0x118 382 #define CSI_MIPI0_ID3_CTRL1 0x11C 383 #define CSI_MIPI0_CTRL 0x120 384 #define CSI_MIPI0_FRM0_ADDR_Y_ID0 0x124 385 #define CSI_MIPI0_FRM1_ADDR_Y_ID0 0x128 386 #define CSI_MIPI0_FRM0_ADDR_UV_ID0 0x12C 387 #define CSI_MIPI0_FRM1_ADDR_UV_ID0 0x130 388 #define CSI_MIPI0_VLW_ID0 0x134 389 #define CSI_MIPI0_FRM0_ADDR_Y_ID1 0x138 390 #define CSI_MIPI0_FRM1_ADDR_Y_ID1 0x13C 391 #define CSI_MIPI0_FRM0_ADDR_UV_ID1 0x140 392 #define CSI_MIPI0_FRM1_ADDR_UV_ID1 0x144 393 #define CSI_MIPI0_VLW_ID1 0x148 394 #define CSI_MIPI0_FRM0_ADDR_Y_ID2 0x14C 395 #define CSI_MIPI0_FRM1_ADDR_Y_ID2 0x150 396 #define CSI_MIPI0_FRM0_ADDR_UV_ID2 0x154 397 #define CSI_MIPI0_FRM1_ADDR_UV_ID2 0x158 398 #define CSI_MIPI0_VLW_ID2 0x15C 399 #define CSI_MIPI0_FRM0_ADDR_Y_ID3 0x160 400 #define CSI_MIPI0_FRM1_ADDR_Y_ID3 0x164 401 #define CSI_MIPI0_FRM0_ADDR_UV_ID3 0x168 402 #define CSI_MIPI0_FRM1_ADDR_UV_ID3 0x16C 403 #define CSI_MIPI0_VLW_ID3 0x170 404 #define CSI_MIPI0_INTEN 0x174 405 #define CSI_MIPI0_INTSTAT 0x178 406 #define CSI_MIPI0_LINE_INT_NUM_ID0_1 0x17C 407 #define CSI_MIPI0_LINE_INT_NUM_ID2_3 0x180 408 #define CSI_MIPI0_LINE_CNT_ID0_1 0x184 409 #define CSI_MIPI0_LINE_CNT_ID2_3 0x188 410 #define CSI_MIPI0_ID0_CROP_START 0x18C 411 #define CSI_MIPI0_ID1_CROP_START 0x190 412 #define CSI_MIPI0_ID2_CROP_START 0x194 413 #define CSI_MIPI0_ID3_CROP_START 0x198 414 #define CSI_MIPI0_FRAME_NUM_VC0 0x19C 415 #define CSI_MIPI0_FRAME_NUM_VC1 0x1A0 416 #define CSI_MIPI0_FRAME_NUM_VC2 0x1A4 417 #define CSI_MIPI0_FRAME_NUM_VC3 0x1A8 418 #define CSI_MIPI0_EFFECT_CODE_ID0 0x1AC 419 #define CSI_MIPI0_EFFECT_CODE_ID1 0x1B0 420 #define CSI_MIPI0_EFFECT_CODE_ID2 0x1B4 421 #define CSI_MIPI0_EFFECT_CODE_ID3 0x1B8 422 #define CSI_MIPI0_ON_PAD 0x1BC 423 424 /* RV1106 CONTROL Registers Offset */ 425 #define CIF_LVDS0_ID0_CTRL0 0x1D0 426 #define CIF_LVDS0_ID1_CTRL0 0x1D4 427 #define CIF_LVDS0_ID2_CTRL0 0x1D8 428 #define CIF_LVDS0_ID3_CTRL0 0x1DC 429 #define CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106 0x1E0 430 #define CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106 0x1E4 431 #define CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106 0x1E8 432 #define CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106 0x1EC 433 #define CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106 0x1F0 434 #define CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106 0x1F4 435 #define CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106 0x1F8 436 #define CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106 0x1FC 437 #define CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106 0x200 438 #define CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106 0x204 439 #define CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106 0x208 440 #define CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106 0x20C 441 #define CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106 0x210 442 #define CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106 0x214 443 #define CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106 0x218 444 #define CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106 0x21C 445 446 /* RK3588 CONTROL Registers Offset */ 447 #define GLB_CTRL 0X000 448 #define GLB_INTEN 0X004 449 #define GLB_INTST 0X008 450 #define SCL_CH_CTRL 0x700 451 #define SCL_CTRL 0x704 452 #define SCL_FRM0_ADDR_CH0 0x708 453 #define SCL_FRM1_ADDR_CH0 0x70C 454 #define SCL_VLW_CH0 0x710 455 #define SCL_FRM0_ADDR_CH1 0x714 456 #define SCL_FRM1_ADDR_CH1 0x718 457 #define SCL_VLW_CH1 0x71C 458 #define SCL_FRM0_ADDR_CH2 0x720 459 #define SCL_FRM1_ADDR_CH2 0x724 460 #define SCL_VLW_CH2 0x728 461 #define SCL_FRM0_ADDR_CH3 0x72C 462 #define SCL_FRM1_ADDR_CH3 0x730 463 #define SCL_VLW_CH3 0x734 464 #define SCL_BLC_CH0 0x738 465 #define SCL_BLC_CH1 0x73C 466 #define SCL_BLC_CH2 0x740 467 #define SCL_BLC_CH3 0x744 468 #define TOISP0_CH_CTRL 0x780 469 #define TOISP0_CROP_SIZE 0x784 470 #define TOISP0_CROP 0x788 471 #define TOISP1_CH_CTRL 0x78C 472 #define TOISP1_CROP_SIZE 0x790 473 #define TOISP1_CROP 0x794 474 475 /* The key register bit description */ 476 477 /* CIF_CTRL Reg */ 478 #define DISABLE_CAPTURE (0x0 << 0) 479 #define ENABLE_CAPTURE (0x1 << 0) 480 #define MODE_ONEFRAME (0x0 << 1) 481 #define MODE_PINGPONG (0x1 << 1) 482 #define MODE_LINELOOP (0x2 << 1) 483 #define AXI_BURST_16 (0xF << 12) 484 #define DVP_PRESS_EN (0x1 << 12) 485 #define DVP_HURRY_EN (0x1 << 8) 486 #define DVP_DMA_EN (0x1 << 1) 487 #define DVP_SW_WATER_LINE_75 (0x0 << 5) 488 #define DVP_SW_WATER_LINE_50 (0x1 << 5) 489 #define DVP_SW_WATER_LINE_25 (0x2 << 5) 490 #define DVP_SW_WATER_LINE_00 (0x3 << 5) 491 492 /* CIF_INTEN */ 493 #define INTEN_DISABLE (0x0 << 0) 494 #define FRAME_END_EN (0x1 << 0) 495 #define BUS_ERR_EN (0x1 << 6) 496 #define SCL_ERR_EN (0x1 << 7) 497 #define PRE_INF_FRAME_END_EN (0x1 << 8) 498 #define PST_INF_FRAME_END_EN (0x1 << 9) 499 #define LINE_INT_EN (0x1 << 10) 500 #define DVP_CHANNEL1_FRM_END_EN (0x1 << 11) 501 #define DVP_CHANNEL2_FRM_END_EN (0x1 << 12) 502 #define DVP_CHANNEL3_FRM_END_EN (0x1 << 13) 503 504 /* CIF INTSTAT */ 505 #define INTSTAT_CLS (0x3FF) 506 #define FRAME_END (0x01 << 0) 507 #define LINE_ERR (0x01 << 2) 508 #define PIX_ERR (0x01 << 3) 509 #define IFIFO_OVERFLOW (0x01 << 4) 510 #define DFIFO_OVERFLOW (0x01 << 5) 511 #define BUS_ERR (0x01 << 6) 512 #define PRE_INF_FRAME_END (0x01 << 8) 513 #define PST_INF_FRAME_END (0x01 << 9) 514 #define LINE_INT_END (0x01 << 10) 515 #define FRAME_END_CLR (0x01 << 0) 516 #define PRE_INF_FRAME_END_CLR (0x01 << 8) 517 #define PST_INF_FRAME_END_CLR (0x01 << 9) 518 #define INTSTAT_ERR (0xFC) 519 #define INTSTAT_ERR_RK3588 (DVP_SIZE_ERR |\ 520 DVP_FIFO_OVERFLOW |\ 521 DVP_BANDWIDTH_LACK) 522 523 #define DVP_ALL_OVERFLOW (IFIFO_OVERFLOW | DFIFO_OVERFLOW) 524 525 #define DVP_FIFO_OVERFLOW (0x01 << 16) 526 #define DVP_BANDWIDTH_LACK (0x01 << 17) 527 528 #define DVP_SIZE_ERR_ID0 (0x1 << 22) 529 #define DVP_SIZE_ERR_ID1 (0x1 << 23) 530 #define DVP_SIZE_ERR_ID2 (0x1 << 24) 531 #define DVP_SIZE_ERR_ID3 (0x1 << 25) 532 533 #define DVP_SIZE_ERR (DVP_SIZE_ERR_ID0 |\ 534 DVP_SIZE_ERR_ID1 |\ 535 DVP_SIZE_ERR_ID2 |\ 536 DVP_SIZE_ERR_ID3) 537 538 #define DVP_SW_PRESS_VALUE(val) (((val) & 0x7) << 13) 539 #define DVP_SW_HURRY_VALUE(val) (((val) & 0x7) << 9) 540 #define DVP_SW_CAP_EN(ID) (2 << ID) 541 #define DVP_SW_DMA_EN(ID) (0x100000 << ID) 542 #define DVP_START_INTSTAT(ID) (0x3 << ((ID) * 2)) 543 544 #define DVP_DMA_END_INTEN(id) \ 545 ({ \ 546 unsigned int mask; \ 547 switch (id) { \ 548 case 0: \ 549 mask = 0x1 << 0; \ 550 break; \ 551 default: \ 552 mask = 0x1 << (id + 10); \ 553 break; \ 554 } \ 555 mask; \ 556 }) 557 558 #define DVP_LINE_INTEN (0x01 << 10) 559 560 #define DVP_DMA_END_INTSTAT(id) \ 561 ({ \ 562 unsigned int mask; \ 563 switch (id) { \ 564 case 0: \ 565 mask = 0x1 << 0; \ 566 break; \ 567 default: \ 568 mask = 0x1 << (id + 10); \ 569 break; \ 570 } \ 571 mask; \ 572 }) 573 574 #define DVP_PST_INTSTAT PST_INF_FRAME_END 575 #define DVP_LINE_INTSTAT (0x01 << 10) 576 577 /* FRAME STATUS */ 578 #define FRAME_STAT_CLS 0x00 579 /* write 0 to clear frame 0 */ 580 #define FRM0_STAT_CLS 0xfffffffe 581 #define FRAME_NUM_SHIFT (16U) 582 #define FRAME_NUM_MASK (0xffff << FRAME_NUM_SHIFT) 583 #define CIF_GET_FRAME_ID(val) (((val) & FRAME_NUM_MASK) >> FRAME_NUM_SHIFT) 584 585 /* CIF FORMAT */ 586 #define VSY_HIGH_ACTIVE (0x01 << 0) 587 #define VSY_LOW_ACTIVE (0x00 << 0) 588 #define HSY_LOW_ACTIVE (0x01 << 1) 589 #define HSY_HIGH_ACTIVE (0x00 << 1) 590 #define INPUT_MODE_YUV (0x00 << 2) 591 #define INPUT_MODE_PAL (0x02 << 2) 592 #define INPUT_MODE_BT656_YUV422 (0x02 << 2) 593 #define INPUT_MODE_NTSC (0x03 << 2) 594 #define INPUT_MODE_BT1120 (0x07 << 2) 595 #define INPUT_MODE_RAW (0x04 << 2) 596 #define INPUT_MODE_JPEG (0x05 << 2) 597 #define INPUT_MODE_SONY_RAW (0x05 << 2) 598 #define INPUT_MODE_MIPI (0x06 << 2) 599 #define YUV_INPUT_ORDER_UYVY (0x00 << 5) 600 #define YUV_INPUT_ORDER_YVYU (0x01 << 5) 601 #define YUV_INPUT_ORDER_VYUY (0x10 << 5) 602 #define YUV_INPUT_ORDER_YUYV (0x03 << 5) 603 #define YUV_INPUT_422 (0x00 << 7) 604 #define YUV_INPUT_420 (0x01 << 7) 605 #define INPUT_420_ORDER_EVEN (0x00 << 8) 606 #define INPUT_420_ORDER_ODD (0x01 << 8) 607 #define CCIR_INPUT_ORDER_ODD (0x00 << 9) 608 #define CCIR_INPUT_ORDER_EVEN (0x01 << 9) 609 #define RAW_DATA_WIDTH_8 (0x00 << 11) 610 #define RAW_DATA_WIDTH_10 (0x01 << 11) 611 #define RAW_DATA_WIDTH_12 (0x02 << 11) 612 #define MIPI_MODE_32BITS_BYPASS (0x00 << 13) 613 #define MIPI_MODE_RGB (0x01 << 13) 614 #define MIPI_MODE_YUV (0x02 << 13) 615 #define YUV_OUTPUT_422 (0x00 << 16) 616 #define YUV_OUTPUT_420 (0x01 << 16) 617 #define OUTPUT_420_ORDER_EVEN (0x00 << 17) 618 #define OUTPUT_420_ORDER_ODD (0x01 << 17) 619 #define RAWD_DATA_LITTLE_ENDIAN (0x00 << 18) 620 #define RAWD_DATA_BIG_ENDIAN (0x01 << 18) 621 #define UV_STORAGE_ORDER_UVUV (0x00 << 19) 622 #define UV_STORAGE_ORDER_VUVU (0x01 << 19) 623 #define BT1120_CLOCK_SINGLE_EDGES (0x00 << 24) 624 #define BT1120_CLOCK_DOUBLE_EDGES (0x01 << 24) 625 #define BT1120_TRANSMIT_INTERFACE (0x00 << 25) 626 #define BT1120_TRANSMIT_PROGRESS (0x01 << 25) 627 #define BT1120_YC_SWAP (0x01 << 26) 628 #define BT656_1120_MULTI_ID_DISABLE (0x00 << 28) 629 #define BT656_1120_MULTI_ID_ENABLE (0x01 << 28) 630 #define BT656_1120_MULTI_ID_SEL_MSB (0x00 << 29) 631 #define BT656_1120_MULTI_ID_SEL_LSB (0x01 << 29) 632 #define BT656_1120_MULTI_ID_MODE_1 (0x00 << 30) 633 #define BT656_1120_MULTI_ID_MODE_2 (0x01 << 30) 634 #define BT656_1120_MULTI_ID_MODE_4 (0x02 << 30) 635 #define BT656_1120_MULTI_ID_0_MASK ~(0x03 << 4) 636 #define BT656_1120_MULTI_ID_1_MASK ~(0x03 << 12) 637 #define BT656_1120_MULTI_ID_2_MASK ~(0x03 << 20) 638 #define BT656_1120_MULTI_ID_3_MASK ~(0x03 << 28) 639 #define CIF_HIGH_ALIGN (0x01 << 18) 640 #define CIF_HIGH_ALIGN_RK3588 (0x01 << 21) 641 #define BT656_DETECT_SAV (0X01 << 13) 642 #define BT656_DETECT_SAV_EAV (0X00 << 13) 643 644 #define BT1120_CLOCK_SINGLE_EDGES_RK3588 (0x00 << 11) 645 #define BT1120_CLOCK_DOUBLE_EDGES_RK3588 (0x01 << 11) 646 #define TRANSMIT_INTERFACE_RK3588 (0x01 << 9) 647 #define TRANSMIT_PROGRESS_RK3588 (0x00 << 9) 648 #define BT1120_YC_SWAP_RK3588 (0x01 << 12) 649 #define INPUT_BT601_YUV422 (0x00 << 2) 650 #define INPUT_BT601_RAW (0x01 << 2) 651 #define INPUT_BT656_YUV422 (0x02 << 2) 652 #define INPUT_BT1120_YUV422 (0x03 << 2) 653 #define INPUT_SONY_RAW (0x04 << 2) 654 655 /* CIF_SCL_CTRL */ 656 #define ENABLE_SCL_DOWN (0x01 << 0) 657 #define DISABLE_SCL_DOWN (0x00 << 0) 658 #define ENABLE_SCL_UP (0x01 << 1) 659 #define DISABLE_SCL_UP (0x00 << 1) 660 #define ENABLE_YUV_16BIT_BYPASS (0x01 << 4) 661 #define DISABLE_YUV_16BIT_BYPASS (0x00 << 4) 662 #define ENABLE_RAW_16BIT_BYPASS (0x01 << 5) 663 #define DISABLE_RAW_16BIT_BYPASS (0x00 << 5) 664 #define ENABLE_32BIT_BYPASS (0x01 << 6) 665 #define DISABLE_32BIT_BYPASS (0x00 << 6) 666 667 /* CIF_FRAME_INTSTAT */ 668 #define CIF_F0_READY (0x01 << 0) 669 #define CIF_F1_READY (0x01 << 1) 670 #define DVP_CHANNEL0_FRM_READ (CIF_F0_READY | CIF_F1_READY) 671 #define DVP_CHANNEL1_F0_READY (0x01 << 4) 672 #define DVP_CHANNEL1_F1_READY (0x01 << 5) 673 #define DVP_CHANNEL1_FRM_READ (DVP_CHANNEL1_F0_READY | DVP_CHANNEL1_F1_READY) 674 #define DVP_CHANNEL2_F0_READY (0x01 << 8) 675 #define DVP_CHANNEL2_F1_READY (0x01 << 9) 676 #define DVP_CHANNEL2_FRM_READ (DVP_CHANNEL2_F0_READY | DVP_CHANNEL2_F1_READY) 677 #define DVP_CHANNEL3_F0_READY (0x01 << 12) 678 #define DVP_CHANNEL3_F1_READY (0x01 << 13) 679 #define DVP_CHANNEL3_FRM_READ (DVP_CHANNEL3_F0_READY | DVP_CHANNEL3_F1_READY) 680 681 #define DVP_FRAME0_START_ID0 (0x1 << 0) 682 #define DVP_FRAME1_START_ID0 (0x1 << 1) 683 684 #define DVP_FRAME_END_ID0 (0x1 << 0) 685 #define DVP_FRAME_END_ID1 (0x1 << 11) 686 #define DVP_FRAME_END_ID2 (0x1 << 12) 687 #define DVP_FRAME_END_ID3 (0x1 << 13) 688 689 #define DVP_FRAME0_END_ID0 (0x1 << 8) 690 #define DVP_FRAME1_END_ID0 (0x1 << 9) 691 #define DVP_ALL_END_ID0 (DVP_FRAME0_END_ID0 | DVP_FRAME1_END_ID0) 692 693 #define DVP_FRAME0_END_ID1 (0x1 << 10) 694 #define DVP_FRAME1_END_ID1 (0x1 << 11) 695 #define DVP_ALL_END_ID1 (DVP_FRAME0_END_ID1 | DVP_FRAME1_END_ID1) 696 697 #define DVP_FRAME0_END_ID2 (0x1 << 12) 698 #define DVP_FRAME1_END_ID2 (0x1 << 13) 699 #define DVP_ALL_END_ID2 (DVP_FRAME0_END_ID2 | DVP_FRAME1_END_ID2) 700 701 #define DVP_FRAME0_END_ID3 (0x1 << 14) 702 #define DVP_FRAME1_END_ID3 (0x1 << 15) 703 #define DVP_ALL_END_ID3 (DVP_FRAME0_END_ID3 | DVP_FRAME1_END_ID3) 704 705 #define DVP_ALIGN_MSB (0x01 << 21) 706 #define DVP_ALIGN_LSB (0x00 << 21) 707 708 #define DVP_FRM_STS_ID0(x) (((x) & (0x3 << 0)) >> 0) 709 #define DVP_FRM_STS_ID1(x) (((x) & (0x3 << 4)) >> 4) 710 #define DVP_FRM_STS_ID2(x) (((x) & (0x3 << 8)) >> 8) 711 #define DVP_FRM_STS_ID3(x) (((x) & (0x3 << 12)) >> 12) 712 713 #define DVP_SW_MULTI_ID(channel, id, bits) \ 714 ({ \ 715 unsigned int mask; \ 716 switch (channel) { \ 717 case 0: \ 718 mask = ((bits) << 4) | ((id) << 0); \ 719 break; \ 720 case 1: \ 721 mask = ((bits) << 12) | ((id) << 8); \ 722 break; \ 723 case 2: \ 724 mask = ((bits) << 20) | ((id) << 16); \ 725 break; \ 726 case 3: \ 727 mask = ((bits) << 28) | ((id) << 24); \ 728 break; \ 729 default: \ 730 mask = ((bits) << 4) | ((id) << 0); \ 731 break; \ 732 } \ 733 mask; \ 734 }) 735 736 /* CIF CROP */ 737 #define CIF_CROP_Y_SHIFT 16 738 #define CIF_CROP_X_SHIFT 0 739 740 /* CIF SCALE*/ 741 #define SCALE_END_INTSTAT(ch) (0x3 << ((ch + 1) * 2)) 742 #define SCALE_FIFO_OVERFLOW(ch) (1 << (10 + ch)) 743 #define SCALE_TOISP_AXI0_ERR (1 << 0) 744 #define SCALE_TOISP_AXI1_ERR (1 << 1) 745 #define CIF_SCALE_SW_PRESS_VALUE(val) (((val) & 0x7) << 13) 746 #define CIF_SCALE_SW_PRESS_ENABLE (0x1 << 12) 747 #define CIF_SCALE_SW_HURRY_VALUE(val) (((val) & 0x7) << 5) 748 #define CIF_SCALE_SW_HURRY_ENABLE (0x1 << 4) 749 #define CIF_SCALE_SW_WATER_LINE(val) (val << 1) 750 #define CIF_SCALE_SW_SRC_CH(val, ch) ((val & 0x1f) << (3 + ch * 8)) 751 #define CIF_SCALE_SW_MODE(val, ch) ((val & 0x3) << (1 + ch * 8)) 752 #define CIF_SCALE_EN(ch) (1 << (ch * 8)) 753 #define SW_SCALE_END(intstat, ch) ((intstat >> ((ch + 1) * 2)) & 0x3) 754 #define SCALE_SOFT_RESET(ch) (0x1 << (ch + 16)) 755 756 /* CIF TOISP*/ 757 #define CIF_TOISP0_FS(ch) (BIT(14) << ch) 758 #define CIF_TOISP1_FS(ch) (BIT(17) << ch) 759 #define CIF_TOISP0_FE(ch) (BIT(20) << ch) 760 #define CIF_TOISP1_FE(ch) (BIT(23) << ch) 761 762 /* CIF_CSI_ID_CTRL0 */ 763 #define CSI_DISABLE_CAPTURE (0x0 << 0) 764 #define CSI_ENABLE_CAPTURE (0x1 << 0) 765 #define CSI_WRDDR_TYPE_RAW8 (0x0 << 1) 766 #define CSI_WRDDR_TYPE_RAW10 (0x1 << 1) 767 #define CSI_WRDDR_TYPE_RAW12 (0x2 << 1) 768 #define CSI_WRDDR_TYPE_RGB888 (0x3 << 1) 769 #define CSI_WRDDR_TYPE_YUV422 (0x4 << 1) 770 #define CSI_WRDDR_TYPE_YUV420SP (0x5 << 1) 771 #define CSI_WRDDR_TYPE_YUV400 (0x6 << 1) 772 #define CSI_WRDDR_TYPE_RGB565 (0x7 << 1) 773 #define CSI_DISABLE_COMMAND_MODE (0x0 << 4) 774 #define CSI_ENABLE_COMMAND_MODE (0x1 << 4) 775 #define CSI_DISABLE_CROP (0x0 << 5) 776 #define CSI_ENABLE_CROP (0x1 << 5) 777 #define CSI_DISABLE_CROP_V1 (0x0 << 4) 778 #define CSI_ENABLE_CROP_V1 (0x1 << 4) 779 #define CSI_ENABLE_MIPI_COMPACT (0x1 << 6) 780 #define CSI_YUV_INPUT_ORDER_UYVY (0x0 << 16) 781 #define CSI_YUV_INPUT_ORDER_VYUY (0x1 << 16) 782 #define CSI_YUV_INPUT_ORDER_YUYV (0x2 << 16) 783 #define CSI_YUV_INPUT_ORDER_YVYU (0x3 << 16) 784 #define CSI_HIGH_ALIGN (0x1 << 31) 785 #define CSI_HIGH_ALIGN_RK3588 (0x1 << 27) 786 787 #define CSI_YUV_OUTPUT_ORDER_UYVY (0x0 << 18) 788 #define CSI_YUV_OUTPUT_ORDER_VYUY (0x1 << 18) 789 #define CSI_YUV_OUTPUT_ORDER_YUYV (0x2 << 18) 790 #define CSI_YUV_OUTPUT_ORDER_YVYU (0x3 << 18) 791 #define CSI_WRDDR_TYPE_RAW_COMPACT (0x0 << 5) 792 #define CSI_WRDDR_TYPE_RAW_UNCOMPACT (0x1 << 5) 793 #define CSI_WRDDR_TYPE_YUV_PACKET (0x2 << 5) 794 #define CSI_WRDDR_TYPE_YUV400_RK3588 (0x3 << 5) 795 #define CSI_WRDDR_TYPE_YUV422SP_RK3588 (0x4 << 5) 796 #define CSI_WRDDR_TYPE_YUV420SP_RK3588 (0x5 << 5) 797 #define CSI_ALIGN_MSB (0x01 << 27) 798 #define CSI_ALIGN_LSB (0x0 << 27) 799 #define CSI_DMA_ENABLE (0x1 << 28) 800 801 #define CSI_NO_HDR (0X0 << 22) 802 #define CSI_HDR2 (0X1 << 22) 803 #define CSI_HDR3 (0X2 << 22) 804 805 #define CSI_HDR_MODE_VC (0x0 << 20) 806 #define CSI_HDR_MODE_LINE_CNT (0x1 << 20) 807 #define CSI_HDR_MODE_LINE_INFO (0x2 << 20) 808 #define CSI_HDR_VC_MODE_PROTECT (0x1 << 29) 809 810 #define LVDS_ENABLE_CAPTURE (0x1 << 16) 811 #define LVDS_MODE(mode) (((mode) & 0x7) << 17) 812 #define LVDS_LANES_ENABLED(lanes) \ 813 ({ \ 814 unsigned int mask; \ 815 switch (lanes) { \ 816 case 1: \ 817 mask = 0x1 << 20; \ 818 break; \ 819 case 2: \ 820 mask = 0x3 << 20; \ 821 break; \ 822 case 3: \ 823 mask = 0x7 << 20; \ 824 break; \ 825 case 4: \ 826 mask = 0xf << 20; \ 827 break; \ 828 default: \ 829 mask = 0x1 << 20; \ 830 break; \ 831 } \ 832 mask; \ 833 }) 834 835 #define LVDS_MAIN_LANE(index) (((index) & 0x3) << 24) 836 #define LVDS_FID(id) (((id) & 0x3) << 26) 837 #define LVDS_HDR_FRAME_X2 (0x0 << 28) 838 #define LVDS_HDR_FRAME_X3 (0x1 << 28) 839 #define LVDS_COMPACT (0x1 << 29) 840 841 #define LVDS_ENABLE_CAPTURE_RV1106 (0x1 << 0) 842 #define LVDS_MODE_RV1106(mode) (((mode) & 0x7) << 1) 843 #define LVDS_LANES_ENABLED_RV1106(lanes) \ 844 ({ \ 845 unsigned int mask; \ 846 switch (lanes) { \ 847 case 1: \ 848 mask = 0x1 << 4; \ 849 break; \ 850 case 2: \ 851 mask = 0x3 << 4; \ 852 break; \ 853 case 3: \ 854 mask = 0x7 << 4; \ 855 break; \ 856 case 4: \ 857 mask = 0xf << 4; \ 858 break; \ 859 default: \ 860 mask = 0x1 << 4; \ 861 break; \ 862 } \ 863 mask; \ 864 }) 865 866 #define LVDS_MAIN_LANE_RV1106(index) (((index) & 0x3) << 8) 867 #define LVDS_FID_RV1106(id) (((id) & 0x3) << 10) 868 #define LVDS_HDR_FRAME_X2_RV1106 (0x0 << 12) 869 #define LVDS_HDR_FRAME_X3_RV1106 (0x1 << 12) 870 #define LVDS_DMAEN_RV1106 (0x1 << 15) 871 872 /* CIF_CSI_INTEN */ 873 #define CSI_FRAME1_START_INTEN(id) (0x1 << ((id) * 2 + 1)) 874 #define CSI_FRAME0_END_INTEN(id) (0x1 << ((id) * 2 + 8)) 875 #define CSI_FRAME1_END_INTEN(id) (0x1 << ((id) * 2 + 9)) 876 #define CSI_DMA_Y_FIFO_OVERFLOW_INTEN (0x1 << 16) 877 #define CSI_DMA_UV_FIFO_OVERFLOW_INTEN (0x1 << 17) 878 #define CSI_CONFIG_FIFO_OVERFLOW_INTEN (0x1 << 18) 879 #define CSI_BANDWIDTH_LACK_INTEN (0x1 << 19) 880 #define CSI_RX_FIFO_OVERFLOW_INTEN (0x1 << 20) 881 #define CSI_ALL_FRAME_START_INTEN (0xff << 0) 882 #define CSI_ALL_FRAME_END_INTEN (0xff << 8) 883 #define CSI_ALL_ERROR_INTEN (0x1f << 16) 884 #define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16) 885 886 #define CSI_START_INTEN(id) (0x3 << ((id) * 2)) 887 #define CSI_DMA_END_INTEN(id) (0x3 << ((id) * 2 + 8)) 888 #define CSI_LINE_INTEN(id) (0x1 << ((id) + 21)) 889 #define CSI_LINE_INTEN_RK3588(id) (0x1 << ((id) + 20)) 890 891 #define CSI_START_INTSTAT(id) (0x3 << ((id) * 2)) 892 #define CSI_DMA_END_INTSTAT(id) (0x3 << ((id) * 2 + 8)) 893 #define CSI_LINE_INTSTAT(id) (0x1 << ((id) + 21)) 894 #define CSI_LINE_INTSTAT_V1(id) (0x1 << ((id) + 20)) 895 896 /* CIF_CSI_INTSTAT */ 897 #define CSI_FRAME0_START_ID0 (0x1 << 0) 898 #define CSI_FRAME1_START_ID0 (0x1 << 1) 899 #define CSI_FRAME0_START_ID1 (0x1 << 2) 900 #define CSI_FRAME1_START_ID1 (0x1 << 3) 901 #define CSI_FRAME0_START_ID2 (0x1 << 4) 902 #define CSI_FRAME1_START_ID2 (0x1 << 5) 903 #define CSI_FRAME0_START_ID3 (0x1 << 6) 904 #define CSI_FRAME1_START_ID3 (0x1 << 7) 905 #define CSI_FRAME0_END_ID0 (0x1 << 8) 906 #define CSI_FRAME1_END_ID0 (0x1 << 9) 907 #define CSI_FRAME0_END_ID1 (0x1 << 10) 908 #define CSI_FRAME1_END_ID1 (0x1 << 11) 909 #define CSI_FRAME0_END_ID2 (0x1 << 12) 910 #define CSI_FRAME1_END_ID2 (0x1 << 13) 911 #define CSI_FRAME0_END_ID3 (0x1 << 14) 912 #define CSI_FRAME1_END_ID3 (0x1 << 15) 913 #define CSI_DMA_Y_FIFO_OVERFLOW (0x1 << 16) 914 #define CSI_DMA_UV_FIFO_OVERFLOW (0x1 << 17) 915 #define CSI_CONFIG_FIFO_OVERFLOW (0x1 << 18) 916 #define CSI_BANDWIDTH_LACK (0x1 << 19) 917 #define CSI_RX_FIFO_OVERFLOW (0x1 << 20) 918 #define CSI_LINE_ID0_INTST (0x1 << 21) 919 #define CSI_LINE_ID1_INTST (0x1 << 22) 920 #define CSI_LINE_ID2_INTST (0x1 << 23) 921 #define CSI_LINE_ID3_INTST (0x1 << 24) 922 #define CSI_DMA_LVDS_ID2_FIFO_OVERFLOW (0x1 << 25) 923 #define CSI_DMA_LVDS_ID3_FIFO_OVERFLOW (0x1 << 26) 924 #define CSI_SIZE_ERR_ID0 (0x1 << 24) 925 #define CSI_SIZE_ERR_ID1 (0x1 << 25) 926 #define CSI_SIZE_ERR_ID2 (0x1 << 26) 927 #define CSI_SIZE_ERR_ID3 (0x1 << 27) 928 929 #define CSI_FRAME_START_ID0 (CSI_FRAME0_START_ID0 |\ 930 CSI_FRAME1_START_ID0) 931 #define CSI_FRAME_START_ID1 (CSI_FRAME0_START_ID1 |\ 932 CSI_FRAME1_START_ID1) 933 #define CSI_FRAME_START_ID2 (CSI_FRAME0_START_ID2 |\ 934 CSI_FRAME1_START_ID2) 935 #define CSI_FRAME_START_ID3 (CSI_FRAME0_START_ID3 |\ 936 CSI_FRAME1_START_ID3) 937 #define CSI_FRAME_END_ID0 (CSI_FRAME0_END_ID0 |\ 938 CSI_FRAME1_END_ID0) 939 #define CSI_FRAME_END_ID1 (CSI_FRAME0_END_ID1 |\ 940 CSI_FRAME1_END_ID1) 941 #define CSI_FRAME_END_ID2 (CSI_FRAME0_END_ID2 |\ 942 CSI_FRAME1_END_ID2) 943 #define CSI_FRAME_END_ID3 (CSI_FRAME0_END_ID3 |\ 944 CSI_FRAME1_END_ID3) 945 #define CSI_FIFO_OVERFLOW (CSI_DMA_Y_FIFO_OVERFLOW |\ 946 CSI_DMA_UV_FIFO_OVERFLOW |\ 947 CSI_CONFIG_FIFO_OVERFLOW |\ 948 CSI_RX_FIFO_OVERFLOW |\ 949 CSI_DMA_LVDS_ID2_FIFO_OVERFLOW |\ 950 CSI_DMA_LVDS_ID3_FIFO_OVERFLOW) 951 952 /*mask for rk3588*/ 953 #define CSI_RX_FIFO_OVERFLOW_V1 (0x1 << 19) 954 #define CSI_BANDWIDTH_LACK_V1 (0x1 << 18) 955 #define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16) 956 957 958 #define CSI_FIFO_OVERFLOW_V1 (CSI_DMA_Y_FIFO_OVERFLOW |\ 959 CSI_DMA_UV_FIFO_OVERFLOW |\ 960 CSI_RX_FIFO_OVERFLOW_V1) 961 #define CSI_SIZE_ERR (CSI_SIZE_ERR_ID0 |\ 962 CSI_SIZE_ERR_ID1 |\ 963 CSI_SIZE_ERR_ID2 |\ 964 CSI_SIZE_ERR_ID3) 965 966 /* CIF_MIPI_LVDS_CTRL */ 967 #define CIF_MIPI_LVDS_SW_DMA_IDLE (0x1 << 16) 968 #define CIF_MIPI_LVDS_SW_PRESS_VALUE(val) (((val) & 0x3) << 13) 969 #define CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(val) (((val) & 0x7) << 13) 970 #define CIF_MIPI_LVDS_SW_PRESS_ENABLE (0x1 << 12) 971 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS (0x0 << 9) 972 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS (0x1 << 9) 973 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS (0x2 << 9) 974 #define CIF_MIPI_LVDS_SW_SEL_LVDS (0x1 << 8) 975 #define CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106 (0x1 << 3) 976 #define CIF_MIPI_LVDS_SW_HURRY_VALUE(val) (((val) & 0x3) << 5) 977 #define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(val) (((val) & 0x7) << 5) 978 #define CIF_MIPI_LVDS_SW_HURRY_ENABLE (0x1 << 4) 979 #define CIF_MIPI_LVDS_SW_WATER_LINE_75 (0x0 << 1) 980 #define CIF_MIPI_LVDS_SW_WATER_LINE_50 (0x1 << 1) 981 #define CIF_MIPI_LVDS_SW_WATER_LINE_25 (0x2 << 1) 982 #define CIF_MIPI_LVDS_SW_WATER_LINE_00 (0x3 << 1) 983 #define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE (0x1 << 0) 984 #define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808 (0x1 << 24) 985 #define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(val) (((val) & 0x3) << 17) 986 #define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808 (0x1 << 16) 987 #define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808 (0x0 << 0) 988 #define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808 (0x1 << 0) 989 #define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 (0x2 << 0) 990 #define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808 (0x3 << 0) 991 #define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 (0x1 << 4) 992 993 /* CSI Host Registers Define */ 994 #define CSIHOST_N_LANES 0x04 995 #define CSIHOST_PHY_RSTZ 0x0c 996 #define CSIHOST_RESETN 0x10 997 #define CSIHOST_ERR1 0x20 998 #define CSIHOST_ERR2 0x24 999 #define CSIHOST_MSK1 0x28 1000 #define CSIHOST_MSK2 0x2c 1001 #define CSIHOST_CONTROL 0x40 1002 1003 #define SW_CPHY_EN(x) ((x) << 0) 1004 #define SW_DSI_EN(x) ((x) << 4) 1005 #define SW_DATATYPE_FS(x) ((x) << 8) 1006 #define SW_DATATYPE_FE(x) ((x) << 14) 1007 #define SW_DATATYPE_LS(x) ((x) << 20) 1008 #define SW_DATATYPE_LE(x) ((x) << 26) 1009 1010 #define SW_FRM_END_ID0(x) (((x) & CSI_FRAME_END_ID0) >> 8) 1011 #define SW_FRM_END_ID1(x) (((x) & CSI_FRAME_END_ID1) >> 10) 1012 #define SW_FRM_END_ID2(x) (((x) & CSI_FRAME_END_ID2) >> 12) 1013 #define SW_FRM_END_ID3(x) (((x) & CSI_FRAME_END_ID3) >> 14) 1014 1015 /*RV1106 SKIP FUNC*/ 1016 #define RKCIF_CAP_SHIFT 0x18 1017 #define RKCIF_SKIP_SHIFT 0X15 1018 #define RKCIF_SKIP_EN(x) (0x1 << (8 + x)) 1019 1020 /* CIF LVDS SAV EAV Define */ 1021 #define SW_LVDS_EAV_ACT(code) (((code) & 0xfff) << 16) 1022 #define SW_LVDS_SAV_ACT(code) (((code) & 0xfff) << 0) 1023 #define SW_LVDS_EAV_BLK(code) (((code) & 0xfff) << 16) 1024 #define SW_LVDS_SAV_BLK(code) (((code) & 0xfff) << 0) 1025 1026 /* GRF related with CIF */ 1027 #define CIF_GRF_CIFIO_CON (0x10250) 1028 #define CIF_PCLK_SAMPLING_EDGE_RISING (0x04000400) 1029 #define CIF_PCLK_SAMPLING_EDGE_FALLING (0x04000000) 1030 #define CIF_PCLK_DELAY_ENABLE (0x02000200) 1031 #define CIF_PCLK_DELAY_DISABLE (0x02000000) 1032 #define CIF_SAMPLING_EDGE_DOUBLE (0x01000100) 1033 #define CIF_SAMPLING_EDGE_SINGLE (0x01000000) 1034 #define CIF_PCLK_DELAY_NUM(num) (0x00ff0000 | ((num) & 0xff)) 1035 #define CIF_GRF_VI_CON0 (0x340) 1036 #define CIF_GRF_VI_CON1 (0x344) 1037 #define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10000000) 1038 #define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10001000) 1039 #define RK3568_CIF_PCLK_SINGLE_EDGE (0x02000000) 1040 #define RK3568_CIF_PCLK_DUAL_EDGE (0x02000200) 1041 #define CIF_GRF_SOC_CON2 (0x308) 1042 #define RK3588_CIF_PCLK_SAMPLING_EDGE_RISING (0x00100000) 1043 #define RK3588_CIF_PCLK_SAMPLING_EDGE_FALLING (0x00100010) 1044 #define RK3588_CIF_PCLK_SINGLE_EDGE (0x00200000) 1045 #define RK3588_CIF_PCLK_DUAL_EDGE (0x00200020) 1046 #define RV1106_CIF_GRF_VI_CON (0x50038) 1047 #define RV1106_CIF_GRF_VENC_WRAPPER (0x10008) 1048 #define RV1106_CIF_PCLK_SINGLE_EDGE (0x00040000) 1049 #define RV1106_CIF_PCLK_DUAL_EDGE (0x00040004) 1050 #define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020002) 1051 #define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020000) 1052 #define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010001) 1053 #define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010000) 1054 #define RV1106_CIF_GRF_SEL_M0 (0x00010000) 1055 #define RV1106_CIF_GRF_SEL_M1 (0x00010001) 1056 1057 /*toisp*/ 1058 #define TOISP_FS_CH0(index) (0x1 << (14 + index * 3)) 1059 #define TOISP_FS_CH1(index) (0x1 << (15 + index * 3)) 1060 #define TOISP_FS_CH2(index) (0x1 << (16 + index * 3)) 1061 1062 #define TOISP_END_CH0(index) (0x1 << (20 + index * 3)) 1063 #define TOISP_END_CH1(index) (0x1 << (21 + index * 3)) 1064 #define TOISP_END_CH2(index) (0x1 << (22 + index * 3)) 1065 1066 #endif 1067