1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 17 #ifndef __PHYDM_PHYSTATUS_H__ 18 #define __PHYDM_PHYSTATUS_H__ 19 20 21 /*--------------------------Define -------------------------------------------*/ 22 #define CCK_RSSI_INIT_COUNT 5 23 24 #define RA_RSSI_STATE_INIT 0 25 #define RA_RSSI_STATE_SEND 1 26 #define RA_RSSI_STATE_HOLD 2 27 28 #define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) 29 /* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ 30 31 /* ************************************************************ 32 * structure and define 33 * ************************************************************ */ 34 35 __PACK struct _phy_rx_agc_info { 36 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 37 u8 gain: 7, trsw: 1; 38 #else 39 u8 trsw: 1, gain: 7; 40 #endif 41 }; 42 43 __PACK struct _phy_status_rpt_8192cd { 44 struct _phy_rx_agc_info path_agc[2]; 45 u8 ch_corr[2]; 46 u8 cck_sig_qual_ofdm_pwdb_all; 47 u8 cck_agc_rpt_ofdm_cfosho_a; 48 u8 cck_rpt_b_ofdm_cfosho_b; 49 u8 rsvd_1;/*ch_corr_msb;*/ 50 u8 noise_power_db_msb; 51 s8 path_cfotail[2]; 52 u8 pcts_mask[2]; 53 s8 stream_rxevm[2]; 54 u8 path_rxsnr[2]; 55 u8 noise_power_db_lsb; 56 u8 rsvd_2[3]; 57 u8 stream_csi[2]; 58 u8 stream_target_csi[2]; 59 s8 sig_evm; 60 u8 rsvd_3; 61 62 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 63 u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ 64 u8 sgi_en: 1; 65 u8 rxsc: 2; 66 u8 idle_long: 1; 67 u8 r_ant_train_en: 1; 68 u8 ant_sel_b: 1; 69 u8 ant_sel: 1; 70 #else /*_BIG_ENDIAN_ */ 71 u8 ant_sel: 1; 72 u8 ant_sel_b: 1; 73 u8 r_ant_train_en: 1; 74 u8 idle_long: 1; 75 u8 rxsc: 2; 76 u8 sgi_en: 1; 77 u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ 78 #endif 79 }; 80 81 struct _phy_status_rpt_8812 { 82 /* DWORD 0*/ 83 u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ 84 u8 chl_num_LSB; /*channel number[7:0]*/ 85 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 86 u8 chl_num_MSB: 2; /*channel number[9:8]*/ 87 u8 sub_chnl: 4; /*sub-channel location[3:0]*/ 88 u8 r_RFMOD: 2; /*RF mode[1:0]*/ 89 #else /*_BIG_ENDIAN_ */ 90 u8 r_RFMOD: 2; 91 u8 sub_chnl: 4; 92 u8 chl_num_MSB: 2; 93 #endif 94 95 /* DWORD 1*/ 96 u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ 97 s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ 98 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 99 /*this should be checked again because the definition of 8812 and 8814 is different*/ 100 /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ 101 /* u8 cck_rx_path:4; cck rx path[3:0]*/ 102 u8 resvd_0: 6; 103 u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ 104 #else /*_BIG_ENDIAN_*/ 105 u8 bt_RF_ch_MSB: 2; 106 u8 resvd_0: 6; 107 #endif 108 109 /* DWORD 2*/ 110 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 111 u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ 112 u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ 113 u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ 114 #else /*_BIG_ENDIAN_ */ 115 u8 bt_RF_ch_LSB: 6; 116 u8 ant_div_sw_b: 1; 117 u8 ant_div_sw_a: 1; 118 #endif 119 s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ 120 u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ 121 u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ 122 123 /* DWORD 3*/ 124 s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ 125 s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ 126 127 /* DWORD 4*/ 128 u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ 129 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 130 u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ 131 u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ 132 u8 resvd_1: 1; /*1'b0*/ 133 #else /*_BIG_ENDIAN_*/ 134 u8 resvd_1: 1; 135 u8 pcts_rpt_valid: 1; 136 u8 PCTS_MSK_RPT_3: 6; 137 #endif 138 s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ 139 140 /* DWORD 5*/ 141 u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ 142 u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ 143 144 /* DWORD 6*/ 145 s8 sigevm; /*signal field EVM*/ 146 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 147 u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ 148 u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ 149 u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ 150 u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ 151 #else /*_BIG_ENDIAN_*/ 152 u8 GNT_BT_keep: 1; 153 u8 dpdt_ctrl_keep: 1; 154 u8 antidx_antd: 3; 155 u8 antidx_antc: 3; 156 #endif 157 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 158 u8 antidx_anta: 3; /*antidx_anta[2:0]*/ 159 u8 antidx_antb: 3; /*antidx_antb[2:0]*/ 160 u8 hw_antsw_occur: 2; /*1'b0*/ 161 #else /*_BIG_ENDIAN_*/ 162 u8 hw_antsw_occur: 2; 163 u8 antidx_antb: 3; 164 u8 antidx_anta: 3; 165 #endif 166 }; 167 168 169 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 170 171 __PACK struct _phy_status_rpt_jaguar2_type0 { 172 /* DW0 */ 173 u8 page_num; 174 u8 pwdb; 175 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 176 u8 gain: 6; 177 u8 rsvd_0: 1; 178 u8 trsw: 1; 179 #else 180 u8 trsw: 1; 181 u8 rsvd_0: 1; 182 u8 gain: 6; 183 #endif 184 u8 rsvd_1; 185 186 /* DW1 */ 187 u8 rsvd_2; 188 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 189 u8 rxsc: 4; 190 u8 agc_table: 4; 191 #else 192 u8 agc_table: 4; 193 u8 rxsc: 4; 194 #endif 195 u8 channel; 196 u8 band; 197 198 /* DW2 */ 199 u16 length; 200 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 201 u8 antidx_a: 3; 202 u8 antidx_b: 3; 203 u8 rsvd_3: 2; 204 u8 antidx_c: 3; 205 u8 antidx_d: 3; 206 u8 rsvd_4:2; 207 #else 208 u8 rsvd_3: 2; 209 u8 antidx_b: 3; 210 u8 antidx_a: 3; 211 u8 rsvd_4:2; 212 u8 antidx_d: 3; 213 u8 antidx_c: 3; 214 #endif 215 216 /* DW3 */ 217 u8 signal_quality; 218 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 219 u8 vga:5; 220 u8 lna_l:3; 221 u8 bb_power:6; 222 u8 rsvd_9:1; 223 u8 lna_h:1; 224 #else 225 u8 lna_l:3; 226 u8 vga:5; 227 u8 lna_h:1; 228 u8 rsvd_9:1; 229 u8 bb_power:6; 230 #endif 231 u8 rsvd_5; 232 233 /* DW4 */ 234 u32 rsvd_6; 235 236 /* DW5 */ 237 u32 rsvd_7; 238 239 /* DW6 */ 240 u32 rsvd_8; 241 }; 242 243 __PACK struct _phy_status_rpt_jaguar2_type1 { 244 /* DW0 and DW1 */ 245 u8 page_num; 246 u8 pwdb[4]; 247 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 248 u8 l_rxsc: 4; 249 u8 ht_rxsc: 4; 250 #else 251 u8 ht_rxsc: 4; 252 u8 l_rxsc: 4; 253 #endif 254 u8 channel; 255 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 256 u8 band: 2; 257 u8 rsvd_0: 1; 258 u8 hw_antsw_occu: 1; 259 u8 gnt_bt: 1; 260 u8 ldpc: 1; 261 u8 stbc: 1; 262 u8 beamformed: 1; 263 #else 264 u8 beamformed: 1; 265 u8 stbc: 1; 266 u8 ldpc: 1; 267 u8 gnt_bt: 1; 268 u8 hw_antsw_occu: 1; 269 u8 rsvd_0: 1; 270 u8 band: 2; 271 #endif 272 273 /* DW2 */ 274 u16 lsig_length; 275 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 276 u8 antidx_a: 3; 277 u8 antidx_b: 3; 278 u8 rsvd_1: 2; 279 u8 antidx_c: 3; 280 u8 antidx_d: 3; 281 u8 rsvd_2: 2; 282 #else 283 u8 rsvd_1: 2; 284 u8 antidx_b: 3; 285 u8 antidx_a: 3; 286 u8 rsvd_2: 2; 287 u8 antidx_d: 3; 288 u8 antidx_c: 3; 289 #endif 290 291 /* DW3 */ 292 u8 paid; 293 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 294 u8 paid_msb: 1; 295 u8 gid: 6; 296 u8 rsvd_3: 1; 297 #else 298 u8 rsvd_3: 1; 299 u8 gid: 6; 300 u8 paid_msb: 1; 301 #endif 302 u8 intf_pos; 303 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 304 u8 intf_pos_msb: 1; 305 u8 rsvd_4: 2; 306 u8 nb_intf_flag: 1; 307 u8 rf_mode: 2; 308 u8 rsvd_5: 2; 309 #else 310 u8 rsvd_5: 2; 311 u8 rf_mode: 2; 312 u8 nb_intf_flag: 1; 313 u8 rsvd_4: 2; 314 u8 intf_pos_msb: 1; 315 #endif 316 317 /* DW4 */ 318 s8 rxevm[4]; /* s(8,1) */ 319 320 /* DW5 */ 321 s8 cfo_tail[4]; /* s(8,7) */ 322 323 /* DW6 */ 324 s8 rxsnr[4]; /* s(8,1) */ 325 }; 326 327 __PACK struct _phy_status_rpt_jaguar2_type2 { 328 /* DW0 ane DW1 */ 329 u8 page_num; 330 u8 pwdb[4]; 331 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 332 u8 l_rxsc: 4; 333 u8 ht_rxsc: 4; 334 #else 335 u8 ht_rxsc: 4; 336 u8 l_rxsc: 4; 337 #endif 338 u8 channel; 339 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 340 u8 band: 2; 341 u8 rsvd_0: 1; 342 u8 hw_antsw_occu: 1; 343 u8 gnt_bt: 1; 344 u8 ldpc: 1; 345 u8 stbc: 1; 346 u8 beamformed: 1; 347 #else 348 u8 beamformed: 1; 349 u8 stbc: 1; 350 u8 ldpc: 1; 351 u8 gnt_bt: 1; 352 u8 hw_antsw_occu: 1; 353 u8 rsvd_0: 1; 354 u8 band: 2; 355 #endif 356 357 /* DW2 */ 358 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 359 u8 shift_l_map: 6; 360 u8 rsvd_1: 2; 361 #else 362 u8 rsvd_1: 2; 363 u8 shift_l_map: 6; 364 #endif 365 u8 cnt_pw2cca; 366 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 367 u8 agc_table_a: 4; 368 u8 agc_table_b: 4; 369 u8 agc_table_c: 4; 370 u8 agc_table_d: 4; 371 #else 372 u8 agc_table_b: 4; 373 u8 agc_table_a: 4; 374 u8 agc_table_d: 4; 375 u8 agc_table_c: 4; 376 #endif 377 378 /* DW3 ~ DW6*/ 379 u8 cnt_cca2agc_rdy; 380 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 381 u8 gain_a: 6; 382 u8 rsvd_2: 1; 383 u8 trsw_a: 1; 384 u8 gain_b: 6; 385 u8 rsvd_3: 1; 386 u8 trsw_b: 1; 387 u8 gain_c: 6; 388 u8 rsvd_4: 1; 389 u8 trsw_c: 1; 390 u8 gain_d: 6; 391 u8 rsvd_5: 1; 392 u8 trsw_d: 1; 393 u8 aagc_step_a: 2; 394 u8 aagc_step_b: 2; 395 u8 aagc_step_c: 2; 396 u8 aagc_step_d: 2; 397 #else 398 u8 trsw_a: 1; 399 u8 rsvd_2: 1; 400 u8 gain_a: 6; 401 u8 trsw_b: 1; 402 u8 rsvd_3: 1; 403 u8 gain_b: 6; 404 u8 trsw_c: 1; 405 u8 rsvd_4: 1; 406 u8 gain_c: 6; 407 u8 trsw_d: 1; 408 u8 rsvd_5: 1; 409 u8 gain_d: 6; 410 u8 aagc_step_d: 2; 411 u8 aagc_step_c: 2; 412 u8 aagc_step_b: 2; 413 u8 aagc_step_a: 2; 414 #endif 415 u8 ht_aagc_gain[4]; 416 u8 dagc_gain[4]; 417 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 418 u8 counter: 6; 419 u8 rsvd_6: 2; 420 u8 syn_count: 5; 421 u8 rsvd_7:3; 422 #else 423 u8 rsvd_6: 2; 424 u8 counter: 6; 425 u8 rsvd_7:3; 426 u8 syn_count: 5; 427 #endif 428 }; 429 /*==============================================*/ 430 #elif (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 2) 431 __PACK struct _phy_status_rpt_jaguar2_type0 { 432 /* DW0 : Offset 0 */ 433 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 434 u8 page_num:4; 435 u8 pkt_cnt:2; 436 u8 channel_msb:2; 437 #else 438 u8 channel_msb:2; 439 u8 pkt_cnt:2; 440 u8 page_num:4; 441 #endif 442 u8 pwdb_a; 443 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 444 u8 gain_a: 6; 445 u8 rsvd_0: 1; 446 u8 trsw: 1; 447 #else 448 u8 trsw: 1; 449 u8 rsvd_0: 1; 450 u8 gain_a: 6; 451 #endif 452 453 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 454 u8 agc_table_b:4; 455 u8 agc_table_c:4; 456 #else 457 u8 agc_table_c:4; 458 u8 agc_table_b:4; 459 #endif 460 461 /* DW1 : Offset 4 */ 462 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 463 u8 rsvd_1: 4; 464 u8 agc_table_d: 4; 465 #else 466 u8 agc_table_d: 4; 467 u8 rsvd_1: 4; 468 #endif 469 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 470 u8 l_rxsc: 4; 471 u8 agc_table_a: 4; 472 #else 473 u8 agc_table_a: 4; 474 u8 l_rxsc: 4; 475 #endif 476 u8 channel; 477 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 478 u8 band:2; 479 u8 rsvd_2_1: 1; 480 u8 hw_antsw_occur_keep_cck:1; 481 u8 gnt_bt_keep_cck:1; 482 u8 rsvd_2_2:3; 483 #else 484 u8 rsvd_2_2:3; 485 u8 gnt_bt_keep_cck:1; 486 u8 hw_antsw_occur_keep_cck:1; 487 u8 rsvd_2_1: 1; 488 u8 band:2; 489 #endif 490 491 /* DW2 : Offset 8 */ 492 u16 length; 493 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 494 u8 antidx_a: 4; 495 u8 antidx_b: 4; 496 u8 antidx_c: 4; 497 u8 antidx_d: 4; 498 #else 499 u8 antidx_b: 4; 500 u8 antidx_a: 4; 501 u8 antidx_d: 4; 502 u8 antidx_c: 4; 503 #endif 504 505 /* DW3 : Offset 12 */ 506 u8 signal_quality; 507 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 508 u8 vga_a:5; 509 u8 lna_l_a:3; 510 u8 bb_power_a:6; 511 u8 rsvd_3_1:1; 512 u8 lna_h_a:1; 513 #else 514 u8 lna_l_a:3; 515 u8 vga_a:5; 516 u8 lna_h_a:1; 517 u8 rsvd_3_1:1; 518 u8 bb_power_a:6; 519 #endif 520 u8 rsvd_3_2; 521 522 /* DW4 : Offset 16 */ 523 u8 pwdb_b; 524 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 525 u8 vga_b:5; 526 u8 lna_l_b:3; 527 u8 bb_power_b:6; 528 u8 rsvd_4_1:1; 529 u8 lna_h_b:1; 530 u8 gain_b: 6; 531 u8 rsvd_4_2:2; 532 #else 533 u8 lna_l_b:3; 534 u8 vga_b:5; 535 u8 lna_h_b:1; 536 u8 rsvd_4_1:1; 537 u8 bb_power_b:6; 538 u8 rsvd_4_2:2; 539 u8 gain_b: 6; 540 #endif 541 542 /* DW5 : Offset 20 */ 543 u8 pwdb_c; 544 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 545 u8 vga_c:5; 546 u8 lna_l_c:3; 547 u8 bb_power_c:6; 548 u8 rsvd_5_1:1; 549 u8 lna_h_c:1; 550 u8 gain_c: 6; 551 u8 rsvd_5_2:2; 552 #else 553 u8 lna_l_c:3; 554 u8 vga_c:5; 555 u8 lna_h_c:1; 556 u8 rsvd_5_1:1; 557 u8 bb_power_c:6; 558 u8 rsvd_5_2:2; 559 u8 gain_c: 6; 560 #endif 561 562 /* DW6 : Offset 24 */ 563 u8 pwdb_d; 564 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 565 u8 vga_d:5; 566 u8 lna_l_d:3; 567 u8 bb_power_d:6; 568 u8 rsvd_6_1:1; 569 u8 lna_h_d:1; 570 u8 gain_d: 6; 571 u8 rsvd_6_2:2; 572 #else 573 u8 lna_l_d:3; 574 u8 vga_d:5; 575 u8 lna_h_d:1; 576 u8 rsvd_6_1:1; 577 u8 bb_power_d:6; 578 u8 rsvd_6_2:2; 579 u8 gain_d: 6; 580 #endif 581 }; 582 583 __PACK struct _phy_status_rpt_jaguar2_type1 { 584 /* DW0 : Offset 0 */ 585 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 586 u8 page_num:4; 587 u8 pkt_cnt:2; 588 u8 channel_pri_msb:2; 589 #else 590 u8 channel_pri_msb:2; 591 u8 pkt_cnt:2; 592 u8 page_num:4; 593 #endif 594 u8 pwdb_a; 595 u8 pwdb_b; 596 u8 pwdb_c; 597 598 /* DW1 : Offset 4 */ 599 u8 pwdb_d; 600 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 601 u8 l_rxsc: 4; 602 u8 ht_rxsc: 4; 603 #else 604 u8 ht_rxsc: 4; 605 u8 l_rxsc: 4; 606 #endif 607 u8 channel_pri_lsb; 608 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 609 u8 band: 2; 610 u8 rsvd_0: 2; 611 u8 gnt_bt: 1; 612 u8 ldpc: 1; 613 u8 stbc: 1; 614 u8 beamformed: 1; 615 #else 616 u8 beamformed: 1; 617 u8 stbc: 1; 618 u8 ldpc: 1; 619 u8 gnt_bt: 1; 620 u8 rsvd_0: 2; 621 u8 band: 2; 622 #endif 623 624 /* DW2 : Offset 8 */ 625 u8 channel_sec_lsb; 626 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 627 u8 channel_sec_msb:2; 628 u8 rsvd_1: 2; 629 u8 hw_antsw_occur_a:1; 630 u8 hw_antsw_occur_b:1; 631 u8 hw_antsw_occur_c:1; 632 u8 hw_antsw_occur_d:1; 633 #else 634 u8 hw_antsw_occur_d:1; 635 u8 hw_antsw_occur_c:1; 636 u8 hw_antsw_occur_b:1; 637 u8 hw_antsw_occur_a:1; 638 u8 rsvd_1: 2; 639 u8 channel_sec_msb:2; 640 641 #endif 642 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 643 u8 antidx_a: 4; 644 u8 antidx_b: 4; 645 u8 antidx_c: 4; 646 u8 antidx_d: 4; 647 #else 648 u8 antidx_b: 4; 649 u8 antidx_a: 4; 650 u8 antidx_d: 4; 651 u8 antidx_c: 4; 652 #endif 653 654 /* DW3 : Offset 12 */ 655 u8 paid; 656 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 657 u8 paid_msb: 1; 658 u8 gid: 6; 659 u8 rsvd_3: 1; 660 #else 661 u8 rsvd_3: 1; 662 u8 gid: 6; 663 u8 paid_msb: 1; 664 #endif 665 u16 rsvd_4; 666 /* 667 u8 rsvd_4; 668 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 669 u8 rsvd_5: 6; 670 u8 rf_mode: 2; 671 #else 672 u8 rf_mode: 2; 673 u8 rsvd_5: 6; 674 #endif 675 */ 676 /* DW4 */ 677 s8 rxevm[4]; /* s(8,1) */ 678 679 /* DW5 */ 680 s8 cfo_tail[4]; /* s(8,7) */ 681 682 /* DW6 */ 683 s8 rxsnr[4]; /* s(8,1) */ 684 }; 685 __PACK struct _phy_status_rpt_jaguar2_type2_type3 { 686 /* Type2 is primary channel & type3 is secondary channel */ 687 /* DW0 ane DW1 */ 688 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 689 u8 page_num:4; 690 u8 pkt_cnt:2; 691 u8 channel_msb:2; 692 #else 693 u8 channel_msb:2; 694 u8 pkt_cnt:2; 695 u8 page_num:4; 696 #endif 697 u8 pwdb[4]; 698 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 699 u8 l_rxsc: 4; 700 u8 ht_rxsc: 4; 701 #else 702 u8 ht_rxsc: 4; 703 u8 l_rxsc: 4; 704 #endif 705 u8 channel_lsb; 706 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 707 u8 band: 2; 708 u8 rsvd_0: 1; 709 u8 hw_antsw_occu: 1; 710 u8 gnt_bt: 1; 711 u8 ldpc: 1; 712 u8 stbc: 1; 713 u8 beamformed: 1; 714 #else 715 u8 beamformed: 1; 716 u8 stbc: 1; 717 u8 ldpc: 1; 718 u8 gnt_bt: 1; 719 u8 hw_antsw_occu: 1; 720 u8 rsvd_0: 1; 721 u8 band: 2; 722 #endif 723 724 /* DW2 */ 725 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 726 u8 shift_l_map: 6; 727 u8 rsvd_1: 2; 728 #else 729 u8 rsvd_1: 2; 730 u8 shift_l_map: 6; 731 #endif 732 s8 pwed_th; /* dynamic energy threshold S(8,2) */ 733 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 734 u8 agc_table_a: 4; 735 u8 agc_table_b: 4; 736 u8 agc_table_c: 4; 737 u8 agc_table_d: 4; 738 #else 739 u8 agc_table_b: 4; 740 u8 agc_table_a: 4; 741 u8 agc_table_d: 4; 742 u8 agc_table_c: 4; 743 #endif 744 745 /* DW3 ~ DW6*/ 746 u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */ 747 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 748 u8 mp_gain_a: 6; 749 u8 mp_gain_b_lsb: 2; 750 u8 mp_gain_b_msb: 4; 751 u8 mp_gain_c_lsb: 4; 752 u8 mp_gain_c_msb: 2; 753 u8 avg_noise_pwr_lsb: 4; 754 u8 rsvd_3:2; 755 /* u8 r_rfmod:2; */ 756 u8 mp_gain_d: 6; 757 u8 is_freq_select_fading: 1; 758 u8 rsvd_2: 1; 759 u8 aagc_step_a: 2; 760 u8 aagc_step_b: 2; 761 u8 aagc_step_c: 2; 762 u8 aagc_step_d: 2; 763 #else 764 u8 mp_gain_b_lsb: 2; 765 u8 mp_gain_a: 6; 766 u8 mp_gain_c_lsb: 4; 767 u8 mp_gain_b_msb: 4; 768 u8 rsvd_3:2; 769 /* u8 r_rfmod:2; */ 770 u8 avg_noise_pwr_lsb: 4; 771 u8 mp_gain_c_msb: 2; 772 u8 rsvd_2: 1; 773 u8 is_freq_select_fading: 1; 774 u8 mp_gain_d: 6; 775 u8 aagc_step_d: 2; 776 u8 aagc_step_c: 2; 777 u8 aagc_step_b: 2; 778 u8 aagc_step_a: 2; 779 #endif 780 u8 ht_aagc_gain[4]; 781 u8 dagc_gain[4]; 782 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 783 u8 counter: 6; 784 u8 syn_count_lsb: 2; 785 u8 syn_count_msb: 3; 786 u8 avg_noise_pwr_msb:5; 787 #else 788 u8 syn_count_lsb: 2; 789 u8 counter: 6; 790 u8 avg_noise_pwr_msb:5; 791 u8 syn_count_msb: 3; 792 #endif 793 }; 794 795 __PACK struct _phy_status_rpt_jaguar2_type4 { 796 /* smart antenna */ 797 /* DW0 ane DW1 */ 798 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 799 u8 page_num:4; 800 u8 pkt_cnt:2; 801 u8 channel_msb:2; 802 #else 803 u8 channel_msb:2; 804 u8 pkt_cnt:2; 805 u8 page_num:4; 806 #endif 807 u8 pwdb[4]; 808 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 809 u8 l_rxsc: 4; 810 u8 ht_rxsc: 4; 811 #else 812 u8 ht_rxsc: 4; 813 u8 l_rxsc: 4; 814 #endif 815 u8 channel_lsb; 816 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 817 u8 band: 2; 818 u8 rsvd_0: 1; 819 u8 hw_antsw_occu: 1; 820 u8 gnt_bt: 1; 821 u8 ldpc: 1; 822 u8 stbc: 1; 823 u8 beamformed: 1; 824 #else 825 u8 beamformed: 1; 826 u8 stbc: 1; 827 u8 ldpc: 1; 828 u8 gnt_bt: 1; 829 u8 hw_antsw_occu: 1; 830 u8 rsvd_0: 1; 831 u8 band: 2; 832 #endif 833 834 /* DW2 ~ DW3 */ 835 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 836 u8 bad_tone_cnt_min_eign_0:4; 837 u8 bad_tone_cnt_cn_excess_0:4; 838 u8 training_done_a:1; 839 u8 training_done_b:1; 840 u8 training_done_c:1; 841 u8 training_done_d:1; 842 u8 hw_antsw_occur_a:1; 843 u8 hw_antsw_occur_b:1; 844 u8 hw_antsw_occur_c:1; 845 u8 hw_antsw_occur_d:1; 846 u8 antidx_a: 4; 847 u8 antidx_b: 4; 848 u8 antidx_c: 4; 849 u8 antidx_d: 4; 850 #else 851 u8 bad_tone_cnt_cn_excess_0:4; 852 u8 bad_tone_cnt_min_eign_0:4; 853 u8 hw_antsw_occur_d:1; 854 u8 hw_antsw_occur_c:1; 855 u8 hw_antsw_occur_b:1; 856 u8 hw_antsw_occur_a:1; 857 u8 training_done_d:1; 858 u8 training_done_c:1; 859 u8 training_done_b:1; 860 u8 training_done_a:1; 861 u8 antidx_b: 4; 862 u8 antidx_a: 4; 863 u8 antidx_d: 4; 864 u8 antidx_c: 4; 865 #endif 866 u8 tx_pkt_cnt; 867 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 868 u8 bad_tone_cnt_min_eign_1:4; 869 u8 bad_tone_cnt_cn_excess_1:4; 870 u8 avg_cond_num_0:7; 871 u8 avg_cond_num_1_lsb:1; 872 u8 avg_cond_num_1_msb:6; 873 u8 rsvd_1:2; 874 #else 875 u8 bad_tone_cnt_cn_excess_1:4; 876 u8 bad_tone_cnt_min_eign_1:4; 877 u8 avg_cond_num_1_lsb:1; 878 u8 avg_cond_num_0:7; 879 u8 rsvd_1:2; 880 u8 avg_cond_num_1_msb:6; 881 #endif 882 883 /* DW4 */ 884 s8 rxevm[4]; /* s(8,1) */ 885 886 /* DW5 */ 887 u8 eigenvalue[4]; /* eigenvalue or eigenvalue of seg0 (in dB) */ 888 889 /* DW6 */ 890 s8 rxsnr[4]; /* s(8,1) */ 891 }; 892 893 __PACK struct _phy_status_rpt_jaguar2_type5 { 894 /* smart antenna */ 895 /* DW0 ane DW1 */ 896 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 897 u8 page_num:4; 898 u8 pkt_cnt:2; 899 u8 channel_msb:2; 900 #else 901 u8 channel_msb:2; 902 u8 pkt_cnt:2; 903 u8 page_num:4; 904 #endif 905 u8 pwdb[4]; 906 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 907 u8 l_rxsc: 4; 908 u8 ht_rxsc: 4; 909 #else 910 u8 ht_rxsc: 4; 911 u8 l_rxsc: 4; 912 #endif 913 u8 channel_lsb; 914 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 915 u8 band: 2; 916 u8 rsvd_0: 1; 917 u8 hw_antsw_occu: 1; 918 u8 gnt_bt: 1; 919 u8 ldpc: 1; 920 u8 stbc: 1; 921 u8 beamformed: 1; 922 #else 923 u8 beamformed: 1; 924 u8 stbc: 1; 925 u8 ldpc: 1; 926 u8 gnt_bt: 1; 927 u8 hw_antsw_occu: 1; 928 u8 rsvd_0: 1; 929 u8 band: 2; 930 #endif 931 /* DW2 ~ DW5 */ 932 u8 rsvd_1; 933 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 934 u8 rsvd_2:4; 935 u8 hw_antsw_occur_a:1; 936 u8 hw_antsw_occur_b:1; 937 u8 hw_antsw_occur_c:1; 938 u8 hw_antsw_occur_d:1; 939 u8 antidx_a: 4; 940 u8 antidx_b: 4; 941 u8 antidx_c: 4; 942 u8 antidx_d: 4; 943 #else 944 u8 hw_antsw_occur_d:1; 945 u8 hw_antsw_occur_c:1; 946 u8 hw_antsw_occur_b:1; 947 u8 hw_antsw_occur_a:1; 948 u8 rsvd_2:4; 949 u8 antidx_b: 4; 950 u8 antidx_a: 4; 951 u8 antidx_d: 4; 952 u8 antidx_c: 4; 953 #endif 954 u8 tx_pkt_cnt; 955 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) 956 u8 inf_pos_0_A_flg:1; 957 u8 inf_pos_1_A_flg:1; 958 u8 inf_pos_0_B_flg:1; 959 u8 inf_pos_1_B_flg:1; 960 u8 inf_pos_0_C_flg:1; 961 u8 inf_pos_1_C_flg:1; 962 u8 inf_pos_0_D_flg:1; 963 u8 inf_pos_1_D_flg:1; 964 #else 965 u8 inf_pos_1_D_flg:1; 966 u8 inf_pos_0_D_flg:1; 967 u8 inf_pos_1_C_flg:1; 968 u8 inf_pos_0_C_flg:1; 969 u8 inf_pos_1_B_flg:1; 970 u8 inf_pos_0_B_flg:1; 971 u8 inf_pos_1_A_flg:1; 972 u8 inf_pos_0_A_flg:1; 973 #endif 974 u8 rsvd_3; 975 u8 rsvd_4; 976 u8 inf_pos_0_a; 977 u8 inf_pos_1_a; 978 u8 inf_pos_0_b; 979 u8 inf_pos_1_b; 980 u8 inf_pos_0_c; 981 u8 inf_pos_1_c; 982 u8 inf_pos_0_d; 983 u8 inf_pos_1_d; 984 }; 985 #endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ 986 987 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) 988 989 void 990 phydm_rx_phy_status_new_type( 991 void *p_dm_void, 992 u8 *p_phy_status, 993 struct phydm_perpkt_info_struct *p_pktinfo, 994 struct phydm_phyinfo_struct *p_phy_info 995 ); 996 997 boolean 998 phydm_query_is_mu_api( 999 struct PHY_DM_STRUCT *p_phydm, 1000 u8 ppdu_idx, 1001 u8 *p_data_rate, 1002 u8 *p_gid 1003 ); 1004 #endif 1005 1006 void 1007 phydm_reset_phystatus_avg( 1008 struct PHY_DM_STRUCT *p_dm 1009 ); 1010 1011 void 1012 phydm_reset_phystatus_statistic( 1013 struct PHY_DM_STRUCT *p_dm 1014 ); 1015 1016 void 1017 phydm_reset_rssi_for_dm( 1018 struct PHY_DM_STRUCT *p_dm, 1019 u8 station_id 1020 ); 1021 1022 void 1023 phydm_get_cck_rssi_table_from_reg( 1024 struct PHY_DM_STRUCT *p_dm 1025 ); 1026 1027 u8 1028 phydm_rate_to_num_ss( 1029 struct PHY_DM_STRUCT *p_dm, 1030 u8 data_rate 1031 ); 1032 1033 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1034 void 1035 phydm_normal_driver_rx_sniffer( 1036 struct PHY_DM_STRUCT *p_dm, 1037 u8 *p_desc, 1038 PRT_RFD_STATUS p_rt_rfd_status, 1039 u8 *p_drv_info, 1040 u8 phy_status 1041 ); 1042 #endif 1043 1044 s32 1045 phydm_signal_scale_mapping( 1046 struct PHY_DM_STRUCT *p_dm, 1047 s32 curr_sig 1048 ); 1049 1050 void 1051 odm_phy_status_query( 1052 struct PHY_DM_STRUCT *p_dm, 1053 struct phydm_phyinfo_struct *p_phy_info, 1054 u8 *p_phy_status, 1055 struct phydm_perpkt_info_struct *p_pktinfo 1056 ); 1057 1058 void 1059 phydm_rx_phy_status_init( 1060 void *p_dm_void 1061 ); 1062 1063 #endif /*#ifndef __HALHWOUTSRC_H__*/ 1064