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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regSTC.h 98 // Description: TSP STC/PCR Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_STC_H_ 103 #define _REG_STC_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_STC_64 148 { 149 REG32 STC_L; 150 REG32 STC_H; 151 } REG_STC_64; 152 153 typedef struct _REG_STC_ENG_Ctrl // STC (Bank:0x300E) 154 { 155 // reg_pcr64_0_riu @ tsp0 bank h'7 ~ h'A 156 // reg_pcr64_1_riu @ tsp1 bank h'10 ~ h'13 157 REG_STC_64 CFG_STC_00_17[6]; // reg_pcr64_2_riu ~ reg_pcr64_7_riu 158 159 REG16 CFG_STC_18; // reserved 160 161 // @NOTE: STC0_CONFIG & STC1_CONFIG is controlled by TSP HW , 162 // no need riu fields... 163 REG32 CFG_STC_19_1A; 164 #define CFG_STC_19_1A_REG_SET_BASE_STC 0x00000001 165 #define CFG_STC_19_1A_REG_STC_ENABLE 0x00000002 166 #define CFG_STC_19_1A_REG_STC_LD 0x00000004 167 168 } REG_STC_ENG_Ctrl; 169 170 // PCR (Bank:0x300E) 171 // [Eng , Offset] 172 // HW PCR0 , h'20 ~ h'27 173 // HW PCR1 , h'28 ~ h'2F 174 // HW PCR2 , h'30 ~ h'38 175 // HW PCR3 , h'38 ~ h'3f 176 // HW PCR4 , h'40 ~ h'48 177 // HW PCR5 , h'48 ~ h'4F 178 // HW PCR6 , h'50 ~ h'58 179 // HW PCR7 , h'58 ~ h'5F 180 typedef struct _REG_PCR_ENG_Ctrl 181 { 182 REG16 CFG_PCR_00; 183 #define CFG_PCR_00_REG_PCR_SRC_MASK 0x000F 184 #define CFG_PCR_00_REG_PCR_SRC_SHIFT 0 185 #define CFG_PCR_00_REG_TEI_SKIP_PKT_PCR 0x0010 186 #define CFG_PCR_00_REG_PCR_RESET 0x0020 187 #define CFG_PCR_00_REG_PCR_READ 0x0040 188 #define CFG_PCR_00_REG_DSS_ENABLE 0x0080 189 #define CFG_PCR_00_REG_SKIP_PVR_RUSH_DATA 0x0100 190 #define CFG_PCR_00_REG_PCR_CONFIG_MASK 0xFE00 191 #define CFG_PCR_00_REG_PCR_CONFIG_SHIFT 9 192 193 REG32 CFG_PCR_01_02; // reg_pidflt_pcr 194 #define CFG_PCR_01_02_REG_PIDFLT_PCR_PID_MASK 0x00001FFF 195 #define CFG_PCR_01_02_REG_PIDFLT_PCR_PID_SHIFT 0 196 #define CFG_PCR_01_02_REG_PIDFLT_PCR_ENPCR 0x00008000 197 #define CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_MASK 0x003F0000 198 #define CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_SHIFT 16 199 200 REG32 CFG_PCR_03_04; // reg_pcr_valid ([31:0]) 201 202 REG16 CFG_PCR_05; // reg_pcr_valid ([32]) , reg_pcr_valid_ext 203 #define CFG_PCR_05_REG_PCR_VALID_BIT32_MASK 0x0001 204 #define CFG_PCR_05_REG_PCR_VALID_EXT_MASK 0x03FE 205 #define CFG_PCR_05_REG_PCR_VALID_EXT_SHIFT 1 206 207 REG32 CFG_PCR_06_07; // reserved 208 209 } REG_PCR_ENG_Ctrl; 210 211 #endif // _REG_STC_H_ 212