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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regPATH.h 98 // Description: TSP Live-in Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_PATH_H_ 103 #define _REG_PATH_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_PATH_ENG_Ctrl // LIVE-IN (Bank:0x1610) 148 { 149 REG16 CFG_PATH_00; 150 #define CFG_PATH_00_REG_TS_IF_EN 0x0001 151 #define CFG_PATH_00_REG_TS_DATA_SWAP 0x0002 152 #define CFG_PATH_00_REG_P_SEL 0x0004 153 #define CFG_PATH_00_REG_EXT_SYNC_SEL 0x0008 154 #define CFG_PATH_00_REG_TS_SIN_C0 0x0010 155 #define CFG_PATH_00_REG_TS_SIN_C1 0x0020 156 #define CFG_PATH_00_REG_SERIAL_EXT_SYNC_1T 0x0040 157 #define CFG_PATH_00_REG_FORCE_SYNC_BYTE 0x0080 158 #define CFG_PATH_00_REG_DATA_CHK_2T 0x0100 159 #define CFG_PATH_00_REG_MERGED_MATCH_SYNC_BYTE_EN 0x0400 160 #define CFG_PATH_00_REG_TS_FIFO_BYPASS 0x0800 161 #define CFG_PATH_00_REG_TS_FIFO_EVER_OVERFLOW_CLR 0x1000 162 #define CFG_PATH_00_REG_TS_FIFO_EVER_FULL_CLR 0x2000 163 #define CFG_PATH_00_REG_TS_FIFO_EVER_OVERFLOW 0x4000 164 #define CFG_PATH_00_REG_TS_FIFO_EVER_FULL 0x8000 165 166 REG16 CFG_PATH_01; 167 #define CFG_PATH_01_REG_PKT_CHK_SIZE_MASK 0x00FF 168 #define CFG_PATH_01_REG_PKT_CHK_SIZE_SHIFT 0 169 170 REG16 CFG_PATH_02; 171 #define CFG_PATH_02_REG_LOCKED_PKT_CNT_CLR 0x0001 172 #define CFG_PATH_02_REG_LOCKED_PKT_CNT_LOAD 0x0002 173 #define CFG_PATH_02_REG_CLR_OVERFLOW 0x0004 174 #define CFG_PATH_02_REG_UNLOCKED_PKT_CNT_MODE 0x0008 175 #define CFG_PATH_02_REG_EVER_UNLOCK_STATUS 0x0010 176 #define CFG_PATH_02_REG_TSIF_EVER_OVERFLOW 0x0020 177 #define CFG_PATH_02_REG_TSIF_TSO0_BLOCK_EN 0x0100 178 #define CFG_PATH_02_REG_TSIF_TSO1_BLOCK_EN 0x0200 179 #define CFG_PATH_02_REG_TSIF_TSIO_BLOCK_EN 0x0400 180 181 REG16 CFG_PATH_03; // reg_locked_pkt_cnt 182 183 REG16 CFG_PATH_04; // directv_130_188 184 #define CFG_PATH_04_REG_DIRECTV_EN 0x0001 185 #define CFG_PATH_04_REG_DIRECTV_PSI_EN 0x0002 186 #define CFG_PATH_04_REG_DIRECTV_TEI_EN 0x0004 187 #define CFG_PATH_04_REG_DIRECTV_ERR_CLR 0x0008 188 #define CFG_PATH_04_REG_DIRECTV_ERR_STATUS 0x0010 189 190 REG16 CFG_PATH_05; // reg_pkt_converter_config0 191 #define CFG_PATH_05_PKT_CONVERTER_MODE_MASK 0x0007 192 #define CFG_PATH_05_PKT_CONVERTER_MODE_SHIFT 0 193 #define CFG_PATH_05_PKT_CONVERTER_NORMAL_MODE 0 194 #define CFG_PATH_05_PKT_CONVERTER_CIPLUS_MODE 1 195 #define CFG_PATH_05_PKT_CONVERTER_OPENCABLE_MODE 2 196 #define CFG_PATH_05_PKT_CONVERTER_ATS_MODE 3 197 #define CFG_PATH_05_PKT_CONVERTER_MXL_MODE 4 198 #define CFG_PATH_05_PKT_CONVERTER_ND_MODE 5 199 #define CFG_PATH_05_PKT_CONVERTER_FORCE_SYNCBYTE 0x0008 200 #define CFG_PATH_05_BYPASS_PKT_CONVERTER 0x0010 201 #define CFG_PATH_05_BYPASS_SRC_ID_PARSER 0x0020 202 #define CFG_PATH_05_SRC_ID_FLT_EN 0x0040 203 #define CFG_PATH_05_MXL_PKT_HEADER_MASK 0x0F80 204 #define CFG_PATH_05_MXL_PKT_HEADER_SHIFT 7 205 #define CFG_PATH_05_SYNC_BYTE_POSITION_MASK 0xF000 206 #define CFG_PATH_05_SYNC_BYTE_POSITION_SHIFT 12 207 208 REG16 CFG_PATH_06; 209 // reg_pkt_converter_config1 210 #define CFG_PATH_06_REG_ECO_TS_SYNC_OUT_DELAY 0x0001 211 #define CFG_PATH_06_REG_ECO_TS_SYNC_OUT_REVERSE_BLOCK 0x0002 212 #define CFG_PATH_06_REG_PKT_CONVERTER_FIRST_SYNC_VALID_MASK_EN 0x0004 213 #define CFG_PATH_06_REG_DISABLE_STREAM_ID_CHK_FOR_NAGRA_DONGLE 0x0008 214 #define CFG_PATH_06_REG_DISABLE_PATH_ID_CHK_IN_PKT_CONVERTER 0x0010 215 #define CFG_PATH_06_REG_FILTER_STREAM_ID_0_TO_1F_FOR_NAGRA_DONGLE 0x0080 216 // filter null pkt 217 #define CFG_PATH_06_REG_FILTER_NULL_PKT 0x0100 218 #define CFG_PATH_06_REG_FIX_FILTER_NULL_PKT 0x0200 219 220 REG16 CFG_PATH_07; 221 #define CFG_PATH_07_REG_CAVID_MASK 0x001F 222 #define CFG_PATH_07_REG_CAVID_SHIFT 0 223 #define CFG_PATH_07_REG_BYPASS_CA_PATH 0x0020 224 #define CFG_PATH_07_REG_USE_PID_SLOT_MAP 0x0040 225 #define CFG_PATH_07_REG_DUP_PKT_SKIP 0x0080 226 #define CFG_PATH_07_REG_ADP_DUP 0x0100 227 #define CFG_PATH_07_REG_NDS_TEST_MODE 0x0200 228 #define CFG_PATH_07_REG_DIS_DUP_FOR_NSK21 0x0400 229 #define CFG_PATH_07_REG_CA_DEST_GEN_EN 0x0800 230 #define CFG_PATH_07_REG_CLEAR_REPLACE_EN_MASK 0xF000 231 #define CFG_PATH_07_REG_CLEAR_REPLACE_EN_SHIFT 12 232 233 REG16 CFG_PATH_08; 234 #define CFG_PATH_08_REG_TEI_SKIP_PKT 0x0001 235 #define CFG_PATH_08_REG_BLK_AF_SCRMB_BIT_TSP 0x0002 236 #define CFG_PATH_08_REG_UPDATE_SCRMB_BIT_BY_PUSI 0x0004 237 #define CFG_PATH_08_REG_PDFLT_OVERFLOW_INT_ENABLE 0x0008 238 #define CFG_PATH_08_REG_PDFLT_CLR_OVERFLOW_INT 0x0010 239 #define CFG_PATH_08_REG_REC_NULL_PKT 0x0020 240 #define CFG_PATH_08_REG_ONEWAY_TO_LOCK_BYPASS_CA 0x0040 241 #define CFG_PATH_08_REG_PDFLT_PACKET_LENGTH_MASK 0xFF00 242 #define CFG_PATH_08_REG_PDFLT_PACKET_LENGTH_SHIFT 8 243 244 REG16 CFG_PATH_09; 245 #define CFG_PATH_09_REG_CA_CHANNEL_ID_MASK 0x000F 246 #define CFG_PATH_09_REG_CA_CHANNEL_ID_SHIFT 0 247 #define CFG_PATH_09_REG_PKT_CNT_INIT 0x0010 248 #define CFG_PATH_09_REG_TIMESTAMP_PKT_CNT_SEL 0x0020 249 #define CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_MASK 0xC000 250 #define CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_SHIFT 14 251 252 REG16 CFG_PATH_0A; 253 #define CFG_PATH_0A_REG_DIS_NULL_PKT 0x0001 254 #define CFG_PATH_0A_REG_START_READ_BYPASS_ENABLE 0x0002 255 #define CFG_PATH_0A_REG_MASK_PRIVILEGE_EN 0x0004 256 #define CFG_PATH_0A_REG_ONEWAY_AV_NOT_TO_SEC 0x0008 257 #define CFG_PATH_0A_REG_SKIP_SEC_RUSH_DATA 0x0010 258 #define CFG_PATH_0A_REG_SKIP_ADP_RUSH_DATA 0x0020 259 #define CFG_PATH_0A_REG_SEC_ERR_RM_EN 0x0040 260 #define CFG_PATH_0A_REG_ALT_TS_SIZE 0x0080 261 #define CFG_PATH_0A_REG_PKT_SIZE_SECTION_MASK 0xFF00 262 #define CFG_PATH_0A_REG_PKT_SIZE_SECTION_SHIFT 8 263 264 REG16 CFG_PATH_0B; // reg_err_pkt_cntr 265 266 REG16 CFG_PATH_0C; 267 #define CFG_PATH_0C_REG_CLR_BYTE_CNT 0x0001 268 #define CFG_PATH_0C_REG_ERR_PKT_CNTR_CLR 0x0002 269 #define CFG_PATH_0C_REG_ERR_PKT_CNTR_LOAD 0x0004 270 271 REG16 CFG_PATH_0D; 272 #define CFG_PATH_0D_REG_CHECK_TIMEOUT_CNT_TS_FIFO_MASK 0x00FF 273 #define CFG_PATH_0D_REG_CHECK_TIMEOUT_CNT_TS_FIFO_SHIFT 0 274 #define CFG_PATH_0D_REG_CHECK_TIMEOUT_CNT_PDFLT_MASK 0xFF00 275 #define CFG_PATH_0D_REG_CHECK_TIMEOUT_CNT_PDFLT_SHIFT 8 276 277 REG16 CFG_PATH_0E; 278 #define CFG_PATH_0E_REG_RESET_PATH 0x0001 279 #define CFG_PATH_0E_REG_RESET_TSIF 0x0002 280 #define CFG_PATH_0E_REG_RESET_DIRECTV_130_188 0x0004 281 #define CFG_PATH_0E_REG_RESET_PKT_CONVERTER 0x0008 282 #define CFG_PATH_0E_REG_RESET_TS_DSS_CONVERTER 0x0010 283 #define CFG_PATH_0E_REG_RESET_FILTER_NULL_PKT 0x0020 284 #define CFG_PATH_0E_REG_RESET_SRC_ID_PARSER 0x0040 285 #define CFG_PATH_0E_REG_RESET_PDFLT 0x0080 286 #define CFG_PATH_0E_REG_RESET_RBF_PDFLT 0x0100 287 #define CFG_PATH_0E_REG_RESET_SCR_FILTER 0x0200 288 289 REG16 CFG_PATH_0F; 290 #define CFG_PATH_0F_REG_CLK_GATING_TSP_PATH 0x0001 291 #define CFG_PATH_0F_REG_CLK_GATING_MIU_PATH 0x0002 292 #define CFG_PATH_0F_REG_CLK_GATING_PATH_LIVEIN 0x0004 293 #define CFG_PATH_0F_REG_CLK_GATING_PATH_FILEIN 0x0008 294 #define CFG_PATH_0F_REG_CHECK_TIMEOUT_ENABLE_0 0x0010 295 #define CFG_PATH_0F_REG_CHECK_TIMEOUT_ENABLE_1 0x0020 296 #define CFG_PATH_0F_REG_CHECK_TIMEOUT_ENABLE_2 0x0040 297 298 } REG_PATH_ENG_Ctrl; 299 300 #endif // _REG_PATH_H_ 301