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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regFILE.h 98 // Description: TSP File-in Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_FILE_H_ 103 #define _REG_FILE_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_FILE_ENG_Ctrl // FILE (Bank:0x1611 , 0x1627) 148 { 149 REG16 CFG_FILE_00; 150 #define CFG_FILE_00_REG_TSP_FILE_IN 0x0001 151 #define CFG_FILE_00_REG_MEM_TS_DATA_ENDIAN 0x0002 152 #define CFG_FILE_00_REG_TSP_FILE_SEGMENT 0x0004 153 #define CFG_FILE_00_REG_FILEIN_RADDR_READ 0x0008 154 #define CFG_FILE_00_REG_MEM_TS_W_ORDER 0x0010 155 #define CFG_FILE_00_REG_DIS_MIU_RQ 0x0020 156 #define CFG_FILE_00_REG_RST_TS_FIN 0x0040 157 #define CFG_FILE_00_REG_RST_FILEIN_TSIF 0x0080 158 #define CFG_FILE_00_REG_RST_CMDQ_FILEIN 0x0100 159 #define CFG_FILE_00_REG_WB_RST_FILEIN 0x0200 160 #define CFG_FILE_00_REG_RST_WB_DMA_FILEIN 0x0400 161 #define CFG_FILE_00_REG_FILE2MI_PRI 0x0800 162 #define CFG_FILE_00_REG_RST_READ_DMA 0x1000 163 #define CFG_FILE_00_REG_LPCR2_LOAD 0x2000 164 #define CFG_FILE_00_REG_WB_FSM_RESET 0x4000 165 166 REG16 CFG_FILE_01; 167 #define CFG_FILE_01_REG_TIMER_EN 0x0002 168 #define CFG_FILE_01_REG_PKT192_EN 0x0004 169 #define CFG_FILE_01_REG_PKT192_BLK_DISABLE 0x0008 170 #define CFG_FILE_01_REG_LPCR2_WLD 0x0010 171 #define CFG_FILE_01_REG_TS_DATA_PORT_SEL 0x0020 172 #define CFG_FILE_01_REG_LPCR_FREG_27M_90K 0x0040 173 #define CFG_FILE_01_REG_TSP_FILEIN_ABORT 0x0080 174 #define CFG_FILE_01_REG_DISABLE_FILEIN_ADDR_LEN_BY_TEE 0x0100 175 #define CFG_FILE_01_REG_PS_MODE_BLOCK 0x0200 176 #define CFG_FILE_01_REG_TSIF_PAUSE 0x0400 177 #define CFG_FILE_01_REG_DISABLE_STREAM_ID_CHK_FOR_NAGRA_DONGLE 0x0800 178 #define CFG_FILE_01_REG_FILTER_STREAM_ID_0_TO_1F_FOR_NAGRA_DONGLE 0x1000 179 #define CFG_FILE_01_REG_INCR_PERFORMANCE_ENABLE 0x2000 180 181 REG32 CFG_FILE_02_03; // reg_tsp_filein_raddr_tsif 182 183 REG32 CFG_FILE_04_05; // reg_tsp_filein_rnum_tsif 184 185 REG16 CFG_FILE_06; // reg_tsp_filein_ctrl_tsif 186 #define CFG_FILE_06_REG_FILEIN_RSTART 0x0001 187 #define CFG_FILE_06_REG_FILEIN_DONE 0x0002 188 #define CFG_FILE_06_REG_FILEIN_INIT_TRUST 0x0004 189 #define CFG_FILE_06_REG_FILEIN_ABORT 0x0010 190 191 REG16 CFG_FILE_07; 192 #define CFG_FILE_07_CMD_WR_CNT_TSIF1_MASK 0x001F 193 #define CFG_FILE_07_CMD_WR_CNT_TSIF1_SHIFT 0 194 #define CFG_FILE_07_CMD_FIFO_FULL_TSIF1 0x0040 195 #define CFG_FILE_07_CMD_FIFO_EMPTY_TSIF1 0x0080 196 #define CFG_FILE_07_CMD_WR_LEVEL_TSIF1_MASK 0x0300 197 #define CFG_FILE_07_CMD_WR_LEVEL_TSIF1_SHIFT 8 198 199 REG16 CFG_FILE_08; 200 #define CFG_FILE_08_REG_CHK_PKT_SIZE_MASK 0x00FF 201 #define CFG_FILE_08_REG_CHK_PKT_SIZE_SHIFT 0 202 #define CFG_FILE_08_REG_MATCH_CNT_THRESHOLD_MASK 0x0F00 203 #define CFG_FILE_08_REG_MATCH_CNT_THRESHOLD_SHIFT 8 204 #define CFG_FILE_08_REG_MATCH_CNT_INIT_VALUE_MASK 0xF000 205 #define CFG_FILE_08_REG_MATCH_CNT_INIT_VALUE_SHIFT 12 206 207 REG16 CFG_FILE_09; // reg_tsp_file_timer 208 209 REG16 CFG_FILE_0A; 210 #define CFG_FILE_0A_REG_FIX_192_TIMER_0_EN 0x0001 211 #define CFG_FILE_0A_REG_INIT_TIMESTAMP 0x0002 212 #define CFG_FILE_0A_REG_FIXED_TIMESTAMP_RING_BACK_EN 0x0004 213 #define CFG_FILE_0A_REG_FIX_LPCR_RING_BACK_EN 0x0008 214 #define CFG_FILE_0A_REG_MATCH_CNT_FILEIN_EN 0x0010 215 #define CFG_FILE_0A_REG_INIT_STAMP_RSTART_EN 0x0020 216 #define CFG_FILE_0A_REG_CHK_PRIVILEGE_SYNC_BYTE_EN 0x0040 217 #define CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_MASK 0xFF00 218 #define CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_SHIFT 8 219 220 REG32 CFG_FILE_0B_0C; // reg_init_timestamp_vld 221 222 REG16 CFG_FILE_0D; 223 #define CFG_FILE_0D_REG_SYNC_BYTE_PRIVILEGE_MASK 0x00FF 224 #define CFG_FILE_0D_REG_SYNC_BYTE_PRIVILEGE_SHIFT 0 225 #define CFG_FILE_0D_REG_REPLACE_PRIVILEGE_SYNC_BYTE_MASK 0xFF00 226 #define CFG_FILE_0D_REG_REPLACE_PRIVILEGE_SYNC_BYTE_SHIFT 8 227 228 REG16 CFG_FILE_0E; 229 #define CFG_FILE_0E_REG_RVU_PSI_EN 0x0001 230 #define CFG_FILE_0E_REG_RVU_TEI_EN 0x0002 231 #define CFG_FILE_0E_REG_RVU_ERR_CLR 0x0004 232 #define CFG_FILE_0E_REG_RVU_EN 0x0008 233 #define CFG_FILE_0E_REG_RVU_TIMESTAMP_EN 0x0010 234 #define CFG_FILE_0E_REG_RVU_ERR_EVER 0x0020 235 #define CFG_FILE_0E_REG_HD_0000_TO_SECTION 0x0040 236 #define CFG_FILE_0E_REG_HD_1100_TO_SECTION 0x0080 237 #define CFG_FILE_0E_REG_HD_10X0_11X0_TO_SECTION 0x0100 238 #define CFG_FILE_0E_REG_PAYLOAD_128_MODE 0x0200 239 #define CFG_FILE_0E_REG_SUPPORT_NB 0x0400 240 #define CFG_FILE_0E_REG_FIND_RVU_SYNC_PID 0x0800 241 242 REG16 CFG_FILE_0F; 243 #define CFG_FILE_0F_REG_TSIF_SPD_RST 0x0001 244 #define CFG_FILE_0F_REG_SPD_TSIF_BYPASS 0x0002 245 #define CFG_FILE_0F_REG_LOAD_SPD_KEY 0x0004 246 247 REG32 CFG_FILE_10_11; // reg_lpcr_buf 248 249 REG32 CFG_FILE_12_13; // reg_lpcr_tsif 250 251 REG32 CFG_FILE_14_15; // reg_timestamp 252 253 REG32 CFG_FILE_16_17; // reg_tsp2mi_raddr_tsif 254 #define CFG_FILE_16_17_REG_TSP2MI_RADDR_TSIF_MASK 0x0FFFFFFF 255 256 REG16 CFG_FILE_18; 257 #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F0_MASK 0x00FF 258 #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F0_SHIFT 0 259 #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F1_MASK 0xFF00 260 #define CFG_FILE_18_REG_NAGRA_DONGLE_SYNC_BYTE_F1_SHIFT 8 261 262 REG16 CFG_FILE_19_1F[0x20 - 0x19]; // reserved 263 264 } REG_FILE_ENG_Ctrl; 265 266 #endif // _REG_FILE_H_ 267