1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regPVR_IframeLUT.h 98 // Description: PVR Iframe LUT Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _PVR_IframeLUT_REG_H_ 103 #define _PVR_IframeLUT_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG32PVR_IframeLUT 148 { 149 volatile MS_U16 low; 150 volatile MS_U16 _null_l; 151 volatile MS_U16 high; 152 volatile MS_U16 _null_h; 153 } REG32PVR_IframeLUT; 154 155 typedef struct _REG16PVR_IframeLUT 156 { 157 volatile MS_U16 data; 158 volatile MS_U16 _null; 159 } REG16PVR_IframeLUT; 160 161 typedef struct _PVR_IframeLUT32 162 { 163 volatile MS_U32 REG32PVR_IframeLUT; 164 } PVR_IframeLUT32; 165 166 typedef struct _REG_Ctrl0 // PVR_IframeLUT LUT Bank:0x1736 167 { 168 REG16PVR_IframeLUT CFG0_00; 169 #define CFG0_00_REG_SW_RSTB 0x0001 170 #define CFG0_00_REG_TABLE_ID_AUTO_SET 0x0002 // choose table_id golden. 0: riu, 1:auto 171 #define CFG0_00_REG_WB_ACK_LOC 0x0004 172 #define CFG0_00_REG_CHANNEL_EN0 0x0100 173 #define CFG0_00_REG_CHANNEL_EN1 0x0200 174 #define CFG0_00_REG_CHANNEL_EN2 0x0400 175 #define CFG0_00_REG_CHANNEL_EN3 0x0800 176 REG16PVR_IframeLUT CFG0_01; 177 #define GOLDEN_TABLE_ID0_MASK 0x001F 178 #define GOLDEN_TABLE_ID1_MASK 0x1F00 179 REG16PVR_IframeLUT CFG0_02; 180 #define GOLDEN_TABLE_ID2_MASK 0x001F 181 #define GOLDEN_TABLE_ID3_MASK 0x1F00 182 REG32PVR_IframeLUT CFG0_03_04; // set golden pes start code prefix value 0 183 REG32PVR_IframeLUT CFG0_05_06; // set golden pes start code prefix value 1 184 REG32PVR_IframeLUT CFG0_07_08; // set golden pes start code prefix value 2 185 REG32PVR_IframeLUT CFG0_09_0A; // set golden pes start code prefix value 3 186 REG16PVR_IframeLUT CFG0_0B; 187 #define CFG0_0B_REG_LUT2MI_EN0 0x0001 188 #define CFG0_0B_REG_LUT2MI_EN1 0x0002 189 #define CFG0_0B_REG_LUT2MI_EN2 0x0004 190 #define CFG0_0B_REG_LUT2MI_RST_WADR 0x0008 // reset lut2mi wadr 191 #define CFG0_0B_REG_LUT2MI_DSWAP 0x0010 // swap lut2mi_data_in bit by bit 192 #define CFG0_0B_REG_LUT2MI_DSWAP_BT_ORDER 0x0020 // swap lut2mi_data_in byte by byte 193 #define CFG0_0B_REG_LUT2MI_PAUSE 0x0040 // lut2mi pause data input 194 #define CFG0_0B_REG_LUT2MI_WADR_LD 0x0080 // lut2mi wadr load to cpu 195 #define CFG0_0B_REG_LUT2MI_INT_EN 0x0100 // interrupt enable 196 #define CFG0_0B_REG_LUT2MI_INT_PTS_EN 0x0200 // PTS interrupt enable 197 REG16PVR_IframeLUT CFG0_0C; 198 #define CFG0_0C_REG_LUT2MI_INT 0x0001 // lut2mi interrupt 199 #define CFG0_0C_REG_LUT2MI_PTS_INT 0x0002 // pts interrupt 200 201 #define REG_LUT2MI_ADDR_MASKMASK 0x0FFFFFFF 202 REG16PVR_IframeLUT CFG0_0D_0F[3]; 203 204 REG32PVR_IframeLUT CFG0_10_11; // lut2mi dram start waddr for pvr0 205 REG32PVR_IframeLUT CFG0_12_13; // lut2mi dram mid waddr for pvr0 206 REG32PVR_IframeLUT CFG0_14_15; // lut2mi dram end waddr for pvr0 207 208 REG32PVR_IframeLUT CFG0_16_17; // lut2mi dram start waddr for pvr1 209 REG32PVR_IframeLUT CFG0_18_19; // lut2mi dram mid waddr for pvr1 210 REG32PVR_IframeLUT CFG0_1A_1B; // lut2mi dram end waddr for pvr1 211 212 REG32PVR_IframeLUT CFG0_1C_1D; // lut2mi dram start waddr for pvr2 213 REG32PVR_IframeLUT CFG0_1E_1F; // lut2mi dram mid waddr for pvr2 214 REG32PVR_IframeLUT CFG0_20_21; // lut2mi dram end waddr for pvr2 215 216 REG32PVR_IframeLUT CFG0_22_23; // lut2mi dram start waddr for pvr3 217 REG32PVR_IframeLUT CFG0_24_25; // lut2mi dram mid waddr for pvr3 218 REG32PVR_IframeLUT CFG0_26_27; // lut2mi dram end waddr for pvr3 219 220 221 REG32PVR_IframeLUT CFG0_28_29; // read current lut2mi_wadr 222 #define REG_LUT2MI_WADR_R_MASKMASK 0x0FFFFFFF 223 REG16PVR_IframeLUT CFG0_2A; 224 #define CFG0_2A_REG_SW_RSTZ_MEET_TAIL0 0x0001 // sw resets "meet tail0" status 225 #define CFG0_2A_REG_SW_RSTZ_MEET_MID0 0x0002 // sw resets "meet mid0" status 226 #define CFG0_2A_REG_SW_RSTZ_MEET_TAIL1 0x0004 // sw resets "meet tail1" status 227 #define CFG0_2A_REG_SW_RSTZ_MEET_MID1 0x0008 // sw resets "meet mid1" status 228 #define CFG0_2A_REG_SW_RSTZ_MEET_TAIL2 0x0010 // sw resets "meet tail2" status 229 #define CFG0_2A_REG_SW_RSTZ_MEET_MID2 0x0020 // sw resets "meet mid2" status 230 #define CFG0_2A_REG_SW_RSTZ_MEET_TAIL3 0x0040 // sw resets "meet tail3" status 231 #define CFG0_2A_REG_SW_RSTZ_MEET_MID3 0x0080 // sw resets "meet mid3" status 232 REG16PVR_IframeLUT CFG0_2B; 233 #define CFG0_2B_REG_MEET_TAIL0 0x0001 // meet tail0 status 234 #define CFG0_2B_REG_MEET_MID0 0x0002 // meet mid1 status 235 #define CFG0_2B_REG_MEET_TAIL1 0x0004 // meet tail1 status 236 #define CFG0_2B_REG_MEET_MID1 0x0008 // meet mid1 status 237 #define CFG0_2B_REG_MEET_TAIL2 0x0010 // meet tail2 status 238 #define CFG0_2B_REG_MEET_MID2 0x0020 // meet mid2 status 239 #define CFG0_2B_REG_MEET_TAIL3 0x0040 // meet tail3 status 240 #define CFG0_2B_REG_MEET_MID3 0x0080 // meet mid3 status 241 REG16PVR_IframeLUT CFG0_2C_2F[4]; 242 REG32PVR_IframeLUT CFG0_30_31_PTS0_L; // PTS in channel0 // PTS0_low 243 REG16PVR_IframeLUT CFG0_32; 244 #define CFG0_32_REG_PES2TS_PTS0_H 0x0001 // PTS in channel0 // PTS0_high 245 #define CFG0_32_REG_PES2TS_PTS0_RSTB 0x0002 // reset PTS in channel0 246 247 REG32PVR_IframeLUT CFG0_33_34_PTS1_L; // PTS in channel1 // PTS1_low 248 REG16PVR_IframeLUT CFG0_35; 249 #define CFG0_35_REG_PES2TS_PTS1_H 0x0001 // PTS in channel1 // PTS1_high 250 #define CFG0_35_REG_PES2TS_PTS1_RSTB 0x0002 // reset PTS in channe1l 251 252 REG32PVR_IframeLUT CFG0_36_37_PTS2_L; // PTS in channel2 // PTS2_low 253 REG16PVR_IframeLUT CFG0_38; 254 #define CFG0_38_REG_PES2TS_PTS2_H 0x0001 // PTS in channel2 // PTS2_high 255 #define CFG0_38_REG_PES2TS_PTS2_RSTB 0x0002 // reset PTS in channel2 256 257 REG32PVR_IframeLUT CFG0_39_3A_PTS3_L; // PTS in channel3 // PTS3_low 258 REG16PVR_IframeLUT CFG0_3B; 259 #define CFG0_3B_REG_PES2TS_PTS3_H 0x0001 // PTS in channel3 // PTS3_high 260 #define CFG0_3B_REG_PES2TS_PTS3_RSTB 0x0002 // reset PTS in channel3 261 REG16PVR_IframeLUT CFG0_3C_3E[3]; 262 REG16PVR_IframeLUT CFG0_3F; // register scan number: h5cf3 263 264 } REG_Ctrl0; 265 266 typedef struct _REG_Ctrl1 // pvr_fsc Bank:0x1737 (PVR 1~4) 267 { 268 REG16PVR_IframeLUT CFG1_00; 269 #define CFG1_00_REG_PVR_CHK_ID_MATCH_ON 0x0001 // When packet_header=0, get next packet only when stream_id matches. 270 #define CFG1_00_REG_PVR_ID_CHK_QUALIFY_OFF 0x0002 // 0: pes parser will not qualify stream_id with state machine 271 // 1: parser will take stream_id to be leagal only at ID_CHK state and PKT_DATA state when pkt_cnt >5 to avoid start code emulation. 272 #define CFG1_00_REG_PVR_PKT_LEN_EN 0x0004 // 0: ignore reading packet length from PES stream. The packet length is taken as 0 273 // 1: read packet length from PES stream. 274 #define CFG1_00_REG_PVR_IGNORE_ERR 0x0008 // Enable ignoring PES header parsing error 275 #define CFG1_00_REG_PVR_TS_PUSI_DIS 0x0010 // Disable PES start code identification with PUSI flag 276 #define CFG1_00_REG_PVR_SER_ERROR 0x0100 // write 1 to clear PES header parsing error flag 277 REG16PVR_IframeLUT CFG1_01; // PES stream ID 278 #define CFG1_01_REG_PVR_STREAM_ID_MASK 0x00FF 279 #define CFG1_01_REG_PVR_STREAM_ID_SHIFT 0 280 #define CFG1_01_REG_PVR_STREAM_ID_MASK_MASK 0xFF00 281 #define CFG1_01_REG_PVR_STREAM_ID_MASK_SHIFT 8 282 REG16PVR_IframeLUT CFG1_02; // Last detected PES stream ID 283 #define CFG1_02_REG_PVR_PES_LAST_STREAM_ID_MASK 0x00FF 284 #define CFG1_02_REG_PVR_PES_LAST_STREAM_ID_SHIFT 0 285 REG16PVR_IframeLUT CFG1_03; 286 #define CFG1_03_REG_PVR_CODEC_MPGE 0x0001 287 #define CFG1_03_REG_PVR_CODEC_H264 0x0002 288 #define CFG1_03_REG_PVR_CODEC_HEVC 0x0003 289 #define CFG1_03_REG_PVR_CODEC_AVS 0x0004 290 #define CFG1_03_REG_PVR_SPS_TAG_EN 0x0010 // Enable SPS tag 291 292 REG32PVR_IframeLUT CFG1_04_05; // Start code prefix pattern 293 #define REG_PVR_SC_PREFIX 0x00FFFFFF 294 REG32PVR_IframeLUT CFG1_06_07; // Start code prefix pattern mask 295 #define REG_PVR_SC_PREFIX_MASK 0x00FFFFFF 296 297 REG32PVR_IframeLUT CFG1_08_09; // HEVC VCL NAL enable flag 298 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_TRAIL_N 0x00000001 299 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_TRAIL_R 0x00000002 300 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_TSA_N 0x00000004 301 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_TSA_R 0x00000008 302 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_STSA_N 0x00000010 303 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_STSA_R 0x00000020 304 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RADL_N 0x00000040 305 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RADL_R 0x00000080 306 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RASL_N 0x00000100 307 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RASL_R 0x00000200 308 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_N10 0x00000400 309 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_R11 0x00000800 310 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_N12 0x00001000 311 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_R13 0x00002000 312 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_N14 0x00004000 313 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_VCL_R15 0x00008000 314 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_BLA_W_LP 0x00010000 315 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_BLA_W_RADL 0x00020000 316 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_BLA_N_LP 0x00040000 317 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_IDR_W_RADL 0x00080000 318 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_IDR_N_LP 0x00100000 319 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_CRA_NUT 0x00200000 320 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_IRAP_VCL22 0x00400000 321 #define CFG1_08_09_REG_PVR_HEVC_NAL_EN_RSV_IRAP_VCL23 0x00800000 322 REG32PVR_IframeLUT CFG1_0A_0B; // HEVC VCL IDR NAL flag 323 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_TRAIL_N 0x00000001 324 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_TRAIL_R 0x00000002 325 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_TSA_N 0x00000004 326 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_TSA_R 0x00000008 327 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_STSA_N 0x00000010 328 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_STSA_R 0x00000020 329 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RADL_N 0x00000040 330 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RADL_R 0x00000080 331 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RASL_N 0x00000100 332 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RASL_R 0x00000200 333 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_N10 0x00000400 334 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_R11 0x00000800 335 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_N12 0x00001000 336 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_R13 0x00002000 337 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_N14 0x00004000 338 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_VCL_R15 0x00008000 339 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_BLA_W_LP 0x00010000 340 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_BLA_W_RADL 0x00020000 341 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_BLA_N_LP 0x00040000 342 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_IDR_W_RADL 0x00080000 343 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_IDR_N_LP 0x00100000 344 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_CRA_NUT 0x00200000 345 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_IRAP_VCL22 0x00400000 346 #define CFG1_0A_0B_REG_PVR_HEVC_NAL_IDR_RSV_IRAP_VCL23 0x00800000 347 REG16PVR_IframeLUT CFG1_0C_1F[20]; 348 349 } REG_Ctrl1; 350 351 #endif // _PVR_IframeLUT_REG_H_ 352