1 /** @file mlan_sdio.h 2 * 3 * @brief This file contains definitions for SDIO interface. 4 * driver. 5 * 6 * Copyright (C) 2008-2017, Marvell International Ltd. 7 * 8 * This software file (the "File") is distributed by Marvell International 9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 10 * (the "License"). You may use, redistribute and/or modify this File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 * 21 */ 22 /**************************************************** 23 Change log: 24 ****************************************************/ 25 26 #ifndef _MLAN_SDIO_H 27 #define _MLAN_SDIO_H 28 29 /** Block mode */ 30 #ifndef BLOCK_MODE 31 #define BLOCK_MODE 1 32 #endif 33 34 /** Fixed address mode */ 35 #ifndef FIXED_ADDRESS 36 #define FIXED_ADDRESS 0 37 #endif 38 39 /* Host Control Registers */ 40 /** Host Control Registers : Host to Card Event */ 41 #define HOST_TO_CARD_EVENT_REG 0x00 42 /** Host Control Registers : Host terminates Command 53 */ 43 #define HOST_TERM_CMD53 (0x1U << 2) 44 /** Host Control Registers : Host without Command 53 finish host */ 45 #define HOST_WO_CMD53_FINISH_HOST (0x1U << 2) 46 /** Host Control Registers : Host power up */ 47 #define HOST_POWER_UP (0x1U << 1) 48 /** Host Control Registers : Host power down */ 49 #define HOST_POWER_DOWN (0x1U << 0) 50 51 /** Host Control Registers : Host interrupt RSR */ 52 #define HOST_INT_RSR_REG 0x04 53 54 /** Host Control Registers : Upload host interrupt RSR */ 55 #define UP_LD_HOST_INT_RSR (0x1U) 56 #define HOST_INT_RSR_MASK 0xFF 57 58 /** Host Control Registers : Host interrupt mask */ 59 #define HOST_INT_MASK_REG 0x08 60 61 /** Host Control Registers : Upload host interrupt mask */ 62 #define UP_LD_HOST_INT_MASK (0x1U) 63 /** Host Control Registers : Download host interrupt mask */ 64 #define DN_LD_HOST_INT_MASK (0x2U) 65 /** Host Control Registers : Cmd port upload interrupt mask */ 66 #define CMD_PORT_UPLD_INT_MASK (0x1U << 6) 67 /** Host Control Registers : Cmd port download interrupt mask */ 68 #define CMD_PORT_DNLD_INT_MASK (0x1U << 7) 69 /** Enable Host interrupt mask */ 70 #define HIM_ENABLE (UP_LD_HOST_INT_MASK | \ 71 DN_LD_HOST_INT_MASK | \ 72 CMD_PORT_UPLD_INT_MASK | \ 73 CMD_PORT_DNLD_INT_MASK) 74 /** Disable Host interrupt mask */ 75 #define HIM_DISABLE 0xff 76 77 /** Host Control Registers : Host interrupt status */ 78 #define HOST_INT_STATUS_REG 0x0C 79 80 /** Host Control Registers : Upload command port host interrupt status */ 81 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 82 /** Host Control Registers : Download command port host interrupt status */ 83 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 84 85 /** Host Control Registers : Upload host interrupt status */ 86 #define UP_LD_HOST_INT_STATUS (0x1U) 87 /** Host Control Registers : Download host interrupt status */ 88 #define DN_LD_HOST_INT_STATUS (0x2U) 89 90 /** Port for registers */ 91 #define REG_PORT 0 92 /** Port for memory */ 93 #define MEM_PORT 0x10000 94 /** LSB of read bitmap */ 95 #define RD_BITMAP_L 0x10 96 /** MSB of read bitmap */ 97 #define RD_BITMAP_U 0x11 98 /** LSB of read bitmap second word */ 99 #define RD_BITMAP_1L 0x12 100 /** MSB of read bitmap second word */ 101 #define RD_BITMAP_1U 0x13 102 /** LSB of write bitmap */ 103 #define WR_BITMAP_L 0x14 104 /** MSB of write bitmap */ 105 #define WR_BITMAP_U 0x15 106 /** LSB of write bitmap second word */ 107 #define WR_BITMAP_1L 0x16 108 /** MSB of write bitmap second word */ 109 #define WR_BITMAP_1U 0x17 110 /** LSB of read length for port 0 */ 111 #define RD_LEN_P0_L 0x18 112 /** MSB of read length for port 0 */ 113 #define RD_LEN_P0_U 0x19 114 115 /* Card Control Registers : Command port read length 0 */ 116 #define CMD_RD_LEN_0 0xC0 117 /* Card Control Registers : Command port read length 1 */ 118 #define CMD_RD_LEN_1 0xC1 119 /* Card Control Registers : Command port read length 2 (reserved) */ 120 #define CMD_RD_LEN_2 0xC2 121 /* Card Control Registers : Command port read length 3 */ 122 #define CMD_RD_LEN_3 0xC3 123 /* Card Control Registers : Command port configuration 0 */ 124 #define CMD_CONFIG_0 0xC4 125 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 126 /* Card Control Registers : Command port configuration 1 */ 127 #define CMD_CONFIG_1 0xC5 128 /* Card Control Registers : cmd port auto enable */ 129 #define CMD_PORT_AUTO_EN (0x1U << 0) 130 /* Card Control Registers : Command port configuration 2 (reserved) */ 131 #define CMD_CONFIG_2 0xC6 132 /* Card Control Registers : Command port configuration 3 (reserved) */ 133 #define CMD_CONFIG_3 0xC7 134 135 /* Command port */ 136 #define CMD_PORT_SLCT 0x8000 137 /** Data port mask */ 138 #define DATA_PORT_MASK 0xffffffff 139 140 /** Misc. Config Register : Auto Re-enable interrupts */ 141 #define AUTO_RE_ENABLE_INT MBIT(4) 142 143 /** Host Control Registers : Host transfer status */ 144 #define HOST_RESTART_REG 0x58 145 /** Host Control Registers : Download CRC error */ 146 #define DN_LD_CRC_ERR (0x1U << 2) 147 /** Host Control Registers : Upload restart */ 148 #define UP_LD_RESTART (0x1U << 1) 149 /** Host Control Registers : Download restart */ 150 #define DN_LD_RESTART (0x1U << 0) 151 152 /* Card Control Registers */ 153 /** Card Control Registers : Card to host event */ 154 #define CARD_TO_HOST_EVENT_REG 0x5C 155 /** Card Control Registers : Command port upload ready */ 156 #define UP_LD_CP_RDY (0x1U << 6) 157 /** Card Control Registers : Command port download ready */ 158 #define DN_LD_CP_RDY (0x1U << 7) 159 /** Card Control Registers : Card I/O ready */ 160 #define CARD_IO_READY (0x1U << 3) 161 /** Card Control Registers : CIS card ready */ 162 #define CIS_CARD_RDY (0x1U << 2) 163 /** Card Control Registers : Upload card ready */ 164 #define UP_LD_CARD_RDY (0x1U << 1) 165 /** Card Control Registers : Download card ready */ 166 #define DN_LD_CARD_RDY (0x1U << 0) 167 168 /** Card Control Registers : Host interrupt mask register */ 169 #define HOST_INTERRUPT_MASK_REG 0x60 170 /** Card Control Registers : Host power interrupt mask */ 171 #define HOST_POWER_INT_MASK (0x1U << 3) 172 /** Card Control Registers : Abort card interrupt mask */ 173 #define ABORT_CARD_INT_MASK (0x1U << 2) 174 /** Card Control Registers : Upload card interrupt mask */ 175 #define UP_LD_CARD_INT_MASK (0x1U << 1) 176 /** Card Control Registers : Download card interrupt mask */ 177 #define DN_LD_CARD_INT_MASK (0x1U << 0) 178 179 /** Card Control Registers : Card interrupt status register */ 180 #define CARD_INTERRUPT_STATUS_REG 0x64 181 /** Card Control Registers : Power up interrupt */ 182 #define POWER_UP_INT (0x1U << 4) 183 /** Card Control Registers : Power down interrupt */ 184 #define POWER_DOWN_INT (0x1U << 3) 185 186 /** Card Control Registers : Card interrupt RSR register */ 187 #define CARD_INTERRUPT_RSR_REG 0x68 188 /** Card Control Registers : Power up RSR */ 189 #define POWER_UP_RSR (0x1U << 4) 190 /** Card Control Registers : Power down RSR */ 191 #define POWER_DOWN_RSR (0x1U << 3) 192 193 /** Card Control Registers : SQ Read base address 0 register */ 194 #define READ_BASE_0_REG 0xf8 195 /** Card Control Registers : SQ Read base address 1 register */ 196 #define READ_BASE_1_REG 0xf9 197 /** Enable GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1*/ 198 #define ENABLE_GPIO_1_INT_MODE 0x88 199 /** Scratch reg 3 2 : Configure GPIO-1 INT*/ 200 #define SCRATCH_REG_32 0xEE 201 202 /** Card Control Registers : Card revision register */ 203 #define CARD_REVISION_REG 0xC8 204 205 /** Firmware status 0 register (SCRATCH0_0) */ 206 #define CARD_FW_STATUS0_REG 0xe8 207 /** Firmware status 1 register (SCRATCH0_1) */ 208 #define CARD_FW_STATUS1_REG 0xe9 209 /** Rx length register (SCRATCH0_2) */ 210 #define CARD_RX_LEN_REG 0xea 211 /** Rx unit register (SCRATCH0_3) */ 212 #define CARD_RX_UNIT_REG 0xeb 213 214 /** Card Control Registers : Card OCR 0 register */ 215 #define CARD_OCR_0_REG 0xD4 216 /** Card Control Registers : Card OCR 1 register */ 217 #define CARD_OCR_1_REG 0xD5 218 /** Card Control Registers : Card OCR 3 register */ 219 #define CARD_OCR_3_REG 0xD6 220 /** Card Control Registers : Card config register */ 221 #define CARD_CONFIG_REG 0xD7 222 /** Card Control Registers : Miscellaneous Configuration Register */ 223 #define CARD_MISC_CFG_REG 0xD8 224 225 /** Card Control Registers : sdio new mode register 1 */ 226 #define CARD_CONFIG_2_1_REG 0xD9 227 /** Card Control Registers : cmd53 new mode */ 228 #define CMD53_NEW_MODE (0x1U << 0) 229 /** Card Control Registers : cmd53 tx len format 1 (0x10) */ 230 #define CMD53_TX_LEN_FORMAT_1 (0x1U << 4) 231 /** Card Control Registers : cmd53 tx len format 2 (0x20)*/ 232 #define CMD53_TX_LEN_FORMAT_2 (0x1U << 5) 233 /** Card Control Registers : cmd53 rx len format 1 (0x40) */ 234 #define CMD53_RX_LEN_FORMAT_1 (0x1U << 6) 235 /** Card Control Registers : cmd53 rx len format 2 (0x80)*/ 236 #define CMD53_RX_LEN_FORMAT_2 (0x1U << 7) 237 238 /** Card Control Registers : sdio new mode register 2 */ 239 #define CARD_CONFIG_2_2_REG 0xDA 240 /** Card Control Registers : test data out (0x01) */ 241 #define TEST_DATA_OUT_1 (0x1U << 0) 242 /** Card Control Registers : test data out (0x02) */ 243 #define TEST_DATA_OUT_2 (0x1U << 1) 244 /** Card Control Registers : test data out (0x04) */ 245 #define TEST_DATA_OUT_3 (0x1U << 2) 246 /** Card Control Registers : test data out (0x08) */ 247 #define TEST_DATA_OUT_4 (0x1U << 3) 248 /** Card Control Registers : test cmd out (0x10) */ 249 #define TEST_CMD_OUT (0x1U << 4) 250 251 /** Card Control Registers : sdio new mode register 3 */ 252 #define CARD_CONFIG_2_3_REG 0xDB 253 /** Card Control Registers : test data enable (0x01) */ 254 #define TEST_DATA_EN_1 (0x1U << 0) 255 /** Card Control Registers : test data enable (0x02) */ 256 #define TEST_DATA_EN_2 (0x1U << 1) 257 /** Card Control Registers : test data enable (0x04) */ 258 #define TEST_DATA_EN_3 (0x1U << 2) 259 /** Card Control Registers : test data enable (0x08) */ 260 #define TEST_DATA_EN_4 (0x1U << 3) 261 /** Card Control Registers : test cmd enable (0x10) */ 262 #define TEST_CMD_EN (0x1U << 4) 263 /** Card Control Registers : test mode (0x20) */ 264 #define TEST_MODE (0x1U << 5) 265 266 /** Card Control Registers : Debug 0 register */ 267 #define DEBUG_0_REG 0xDC 268 /** Card Control Registers : SD test BUS 0 */ 269 #define SD_TESTBUS0 (0x1U) 270 /** Card Control Registers : Debug 1 register */ 271 #define DEBUG_1_REG 0xDD 272 /** Card Control Registers : SD test BUS 1 */ 273 #define SD_TESTBUS1 (0x1U) 274 /** Card Control Registers : Debug 2 register */ 275 #define DEBUG_2_REG 0xDE 276 /** Card Control Registers : SD test BUS 2 */ 277 #define SD_TESTBUS2 (0x1U) 278 /** Card Control Registers : Debug 3 register */ 279 #define DEBUG_3_REG 0xDF 280 /** Card Control Registers : SD test BUS 3 */ 281 #define SD_TESTBUS3 (0x1U) 282 283 /** Host Control Registers : I/O port 0 */ 284 #define IO_PORT_0_REG 0xE4 285 /** Host Control Registers : I/O port 1 */ 286 #define IO_PORT_1_REG 0xE5 287 /** Host Control Registers : I/O port 2 */ 288 #define IO_PORT_2_REG 0xE6 289 290 #define FW_RESET_REG 0x0EE 291 #define FW_RESET_VAL 0x99 292 293 /** Event header Len*/ 294 #define MLAN_EVENT_HEADER_LEN 8 295 296 /** SDIO byte mode size */ 297 #define MAX_BYTE_MODE_SIZE 512 298 299 #if defined(SDIO_MULTI_PORT_TX_AGGR) || defined(SDIO_MULTI_PORT_RX_AGGR) 300 /** The base address for packet with multiple ports aggregation */ 301 #define SDIO_MPA_ADDR_BASE 0x1000 302 #endif 303 304 #ifdef SDIO_MULTI_PORT_TX_AGGR 305 306 /** SDIO Tx aggregation in progress ? */ 307 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 308 309 /** SDIO Tx aggregation buffer room for next packet ? */ 310 #define MP_TX_AGGR_BUF_HAS_ROOM(a, mbuf, len) \ 311 (((a->mpa_tx.buf_len) + len) <= (a->mpa_tx.buf_size)) 312 313 /** Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 314 #define MP_TX_AGGR_BUF_PUT(a, mbuf, port) do { \ 315 pmadapter->callbacks.moal_memmove(a->pmoal_handle, \ 316 &a->mpa_tx.buf[a->mpa_tx.buf_len], \ 317 mbuf->pbuf+mbuf->data_offset, mbuf->data_len);\ 318 a->mpa_tx.buf_len += mbuf->data_len; \ 319 a->mpa_tx.mp_wr_info[a->mpa_tx.pkt_cnt] = \ 320 *(t_u16 *)(mbuf->pbuf+mbuf->data_offset); \ 321 if (!a->mpa_tx.pkt_cnt) { \ 322 a->mpa_tx.start_port = port; \ 323 } \ 324 a->mpa_tx.ports |= (1 << port); \ 325 a->mpa_tx.pkt_cnt++; \ 326 } while (0) 327 328 #define MP_TX_AGGR_BUF_PUT_SG(a, mbuf, port) do { \ 329 a->mpa_tx.buf_len += mbuf->data_len; \ 330 a->mpa_tx.mp_wr_info[a->mpa_tx.pkt_cnt] = \ 331 *(t_u16 *)(mbuf->pbuf+mbuf->data_offset); \ 332 a->mpa_tx.mbuf_arr[a->mpa_tx.pkt_cnt] = mbuf; \ 333 if (!a->mpa_tx.pkt_cnt) { \ 334 a->mpa_tx.start_port = port; \ 335 } \ 336 a->mpa_tx.ports |= (1 << port); \ 337 a->mpa_tx.pkt_cnt++; \ 338 } while (0) 339 /** SDIO Tx aggregation limit ? */ 340 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) ((a->mpa_tx.pkt_cnt) \ 341 == (a->mpa_tx.pkt_aggr_limit)) 342 343 /** SDIO Tx aggregation port limit ? */ 344 #define MP_TX_AGGR_PORT_LIMIT_REACHED(a) (MFALSE) 345 346 /** Reset SDIO Tx aggregation buffer parameters */ 347 #define MP_TX_AGGR_BUF_RESET(a) do { \ 348 memset(a, a->mpa_tx.mp_wr_info, 0, sizeof(a->mpa_tx.mp_wr_info)); \ 349 a->mpa_tx.pkt_cnt = 0; \ 350 a->mpa_tx.buf_len = 0; \ 351 a->mpa_tx.ports = 0; \ 352 a->mpa_tx.start_port = 0; \ 353 } while (0) 354 355 #endif /* SDIO_MULTI_PORT_TX_AGGR */ 356 357 #ifdef SDIO_MULTI_PORT_RX_AGGR 358 359 /** SDIO Rx aggregation limit ? */ 360 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) (a->mpa_rx.pkt_cnt \ 361 == a->mpa_rx.pkt_aggr_limit) 362 363 /** SDIO Rx aggregation port limit ? */ 364 /** this is for test only, because port 0 is reserved for control port */ 365 /* #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) (a->curr_rd_port == 1) */ 366 367 /* receive packets aggregated up to a half of mp_end_port */ 368 /* note: hw rx wraps round only after port (MAX_PORT-1) */ 369 #define MP_RX_AGGR_PORT_LIMIT_REACHED(a) \ 370 (((a->curr_rd_port < a->mpa_rx.start_port) && \ 371 (((MAX_PORT - a->mpa_rx.start_port) + a->curr_rd_port) \ 372 >= (a->mp_end_port >> 1))) || \ 373 ((a->curr_rd_port - a->mpa_rx.start_port) >= \ 374 (a->mp_end_port >> 1))) 375 376 /** SDIO Rx aggregation in progress ? */ 377 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 378 379 /** SDIO Rx aggregation buffer room for next packet ? */ 380 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 381 ((a->mpa_rx.buf_len + rx_len) <= a->mpa_rx.buf_size) 382 383 /** Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 384 #define MP_RX_AGGR_SETUP(a, mbuf, port, rx_len) do { \ 385 a->mpa_rx.buf_len += rx_len; \ 386 if (!a->mpa_rx.pkt_cnt) { \ 387 a->mpa_rx.start_port = port; \ 388 } \ 389 a->mpa_rx.ports |= (1 << port); \ 390 a->mpa_rx.mbuf_arr[a->mpa_rx.pkt_cnt] = mbuf; \ 391 a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = rx_len; \ 392 a->mpa_rx.pkt_cnt++; \ 393 } while (0) 394 395 /** Reset SDIO Rx aggregation buffer parameters */ 396 #define MP_RX_AGGR_BUF_RESET(a) do { \ 397 a->mpa_rx.pkt_cnt = 0; \ 398 a->mpa_rx.buf_len = 0; \ 399 a->mpa_rx.ports = 0; \ 400 a->mpa_rx.start_port = 0; \ 401 } while (0) 402 403 #endif /* SDIO_MULTI_PORT_RX_AGGR */ 404 405 /** Enable host interrupt */ 406 mlan_status wlan_enable_host_int(pmlan_adapter pmadapter); 407 /** Probe and initialization function */ 408 mlan_status wlan_sdio_probe(pmlan_adapter pmadapter); 409 /** multi interface download check */ 410 mlan_status wlan_check_winner_status(mlan_adapter *pmadapter, t_u32 *val); 411 412 #ifdef SDIO_MULTI_PORT_TX_AGGR 413 mlan_status wlan_send_mp_aggr_buf(mlan_adapter *pmadapter); 414 #endif 415 416 #if defined(SDIO_MULTI_PORT_RX_AGGR) 417 mlan_status wlan_re_alloc_sdio_rx_mpa_buffer(IN mlan_adapter *pmadapter); 418 #endif 419 420 void wlan_decode_spa_buffer(mlan_adapter *pmadapter, t_u8 *buf, t_u32 len); 421 t_void wlan_sdio_deaggr_rx_pkt(IN pmlan_adapter pmadapter, mlan_buffer *pmbuf); 422 /** Firmware status check */ 423 mlan_status wlan_check_fw_status(mlan_adapter *pmadapter, t_u32 pollnum); 424 /** Read interrupt status */ 425 mlan_status wlan_interrupt(pmlan_adapter pmadapter); 426 /** Process Interrupt Status */ 427 mlan_status wlan_process_int_status(mlan_adapter *pmadapter); 428 /** Transfer data to card */ 429 mlan_status wlan_sdio_host_to_card(mlan_adapter *pmadapter, t_u8 type, 430 mlan_buffer *mbuf, mlan_tx_param *tx_param); 431 mlan_status wlan_set_sdio_gpio_int(IN pmlan_private priv); 432 mlan_status wlan_cmd_sdio_gpio_int(pmlan_private pmpriv, 433 IN HostCmd_DS_COMMAND *cmd, 434 IN t_u16 cmd_action, IN t_void *pdata_buf); 435 mlan_status wlan_reset_fw(pmlan_adapter pmadapter); 436 #endif /* _MLAN_SDIO_H */ 437