1Marvell Armada 8040 NBX Platform 2================================ 3 4The a80x0_nbx platform provides TF-A support for the Free Mobile Nodebox10G 5(NBX), a network appliance based on the Marvell Armada 8040 SoC with dual 6CP110 companion processors. 7 8Hardware Configuration 9---------------------- 10 11- SoC: Marvell Armada 8040 (AP806 + 2x CP110) 12- CPU: Quad-core ARM Cortex-A72 @ 1.3GHz 13- DDR4 memory with ECC support (single channel, 32-bit) 14- Dual CP110 companion processors (CP0 and CP1) 15- SGMII 1G Ethernet on CP0 lane 5 16- I2C buses for peripheral access (CP0: 100kHz, CP1: 400kHz) 17- NS16550 UART console at 115200 baud 18- eMMC boot via Xenon SDHCI controller 19 20Building 21-------- 22 23For general build instructions (toolchain, environment variables, build 24options), refer to :ref:`TF-A Build Instructions for Marvell Platforms 25<build_marvell>`. 26 27.. code:: shell 28 29 make PLAT=a80x0_nbx DEBUG=1 LOG_LEVEL=40 USE_COHERENT_MEM=0 \ 30 PLAT_RECOVERY_IMAGE_ENABLE=1 all fip mrvl_flash 31 32The final flash image is located at 33``build/a80x0_nbx/<debug|release>/flash-image.bin``. 34 35Platform-Specific Features 36-------------------------- 37 38Ramoops Buffer Preservation (ramoopsies) 39~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 41On ECC-enabled DDR configurations, the memory controller must scrub all 42memory during initialization to establish valid parity bits. This would 43normally destroy the Linux kernel ramoops buffer containing crash logs 44from the previous boot. 45 46The ramoopsies driver intercepts the DDR scrubbing function using the 47GNU linker ``--wrap`` feature, saving the 32KB ramoops buffer to SRAM 48before scrubbing and restoring it afterward. The driver also handles 49pending SError exceptions that occur when reading uninitialized ECC 50memory by installing a minimal exception vector that acknowledges and 51clears them. 52 53This is implemented using ``--wrap=mv_ddr_mem_scrubbing`` without 54modifying the upstream mv-ddr-marvell repository. 55 56Source: ``plat/marvell/armada/a8k/a80x0_nbx/board/ramoopsies.c`` 57 58Memory layout: 59 60:: 61 62 Ramoops buffer address: 0x3FFF8000 63 Ramoops buffer size: 32 KB (0x8000) 64 End address: 0x3FFFFFFF (just below 1GB boundary) 65 66Linux kernel configuration: 67 68:: 69 70 CONFIG_PSTORE=y 71 CONFIG_PSTORE_RAM=y 72 CONFIG_PSTORE_CONSOLE=y # Optional: capture kernel console 73 CONFIG_PSTORE_PMSG=y # Optional: capture userspace messages 74 75Device tree configuration: 76 77.. code:: dts 78 79 / { 80 reserved-memory { 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 ramoops@3fff8000 { 86 compatible = "ramoops"; 87 reg = <0x0 0x3fff8000 0x0 0x8000>; 88 record-size = <0x2000>; 89 console-size = <0x2000>; 90 pmsg-size = <0x2000>; 91 ftrace-size = <0x0>; 92 ecc-size = <0x0>; 93 }; 94 }; 95 }; 96 97Alternatively, pass via kernel command line: 98 99.. code:: shell 100 101 ramoops.mem_address=0x3fff8000 ramoops.mem_size=0x8000 \ 102 ramoops.record_size=0x2000 103 104After a kernel crash and reboot, logs are available via pstore: 105 106.. code:: shell 107 108 mount -t pstore pstore /sys/fs/pstore 109 cat /sys/fs/pstore/dmesg-ramoops-0 110 111.. note:: 112 113 Only cold boot (power cycle) triggers DDR scrubbing; warm reboot 114 preserves RAM content without this mechanism. 115 116UART Skip Image Recovery 117~~~~~~~~~~~~~~~~~~~~~~~~ 118 119The platform uses the ``USER_DEFINED`` skip image detection callback 120to implement software-based boot recovery without requiring a dedicated 121GPIO button. Users can trigger recovery mode by holding the ``s`` key 122during early boot, causing the bootloader to load from the 123secondary/recovery image instead of the primary firmware. 124 125Enabled with ``PLAT_RECOVERY_IMAGE_ENABLE=1``. 126 127Usage: 128 1291. Connect serial console (115200 8N1) 1302. Power on or reset the board 1313. Hold ``s`` key during boot 1324. System will skip to recovery/secondary image 133 134DDR Configuration 135~~~~~~~~~~~~~~~~~ 136 137Memory is configured dynamically via SPD (Serial Presence Detect) EEPROM: 138 139==================== =========================== 140SPD I2C Address 0x53 141SPD Page Select 0x36 142I2C Controller CP0 I2C (MPP 37/38) 143Bus Width 64-bit with ECC 144Speed Bin DDR4-2400T 145==================== =========================== 146 147The topology defaults to Micron 8Gbit x8 devices but actual 148configuration is read from the DIMM SPD at runtime. 149 150Flashing 151-------- 152 153Via SPI (from U-Boot): 154 155.. code:: shell 156 157 tftpboot $loadaddr flash-image.bin 158 sf probe 159 sf erase 0 0x100000 160 sf write $loadaddr 0 $filesize 161 162For UART recovery, use the Marvell WTP tools or a compatible UART 163download script when the board is in UART boot mode. 164See :doc:`uart-booting` for details. 165 166Board Files 167----------- 168 169Platform-specific source files are located under 170``plat/marvell/armada/a8k/a80x0_nbx/board/``: 171 172- ``dram_port.c`` - DDR topology and SPD configuration 173- ``marvell_plat_config.c`` - Memory maps, power management, skip image 174- ``phy-porting-layer.h`` - SerDes PHY parameters 175- ``ramoopsies.c`` - ECC memory crash log preservation 176