1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * maxim-max96745.h -- register define for max96745 chip 4 * 5 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 6 * 7 * Author: luowei <lw@rock-chips.com> 8 * 9 */ 10 11 #ifndef __MFD_SERDES_MAXIM_MAX96745_H__ 12 #define __MFD_SERDES_MAXIM_MAX96745_H__ 13 14 #include <linux/bitfield.h> 15 16 #define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8)) 17 #define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8)) 18 #define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8)) 19 #define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8)) 20 21 /* 0005h */ 22 #define PU_LF3 BIT(3) 23 #define PU_LF2 BIT(2) 24 #define PU_LF1 BIT(1) 25 #define PU_LF0 BIT(0) 26 27 /* 0010h */ 28 #define RESET_ALL BIT(7) 29 #define SLEEP BIT(3) 30 31 /* 0011h */ 32 #define CXTP_B BIT(2) 33 #define CXTP_A BIT(0) 34 35 /* 0013h */ 36 #define LOCKED BIT(3) 37 #define ERROR BIT(2) 38 39 /* 0026h */ 40 #define LF_0 GENMASK(2, 0) 41 #define LF_1 GENMASK(6, 4) 42 43 /* 0027h */ 44 #define LF_2 GENMASK(2, 0) 45 #define LF_3 GENMASK(6, 4) 46 47 /* 0028h, 0032h */ 48 #define LINK_EN BIT(7) 49 #define TX_RATE GENMASK(3, 2) 50 51 /* 0029h, 0033h */ 52 #define RESET_LINK BIT(0) 53 #define RESET_ONESHOT BIT(1) 54 55 /* 002Ah, 0034h */ 56 #define LINK_LOCKED BIT(0) 57 58 /* 0076h, 0086h */ 59 #define DIS_REM_CC BIT(7) 60 61 /* 0100h */ 62 #define VID_LINK_SEL GENMASK(2, 1) 63 #define VID_TX_EN BIT(0) 64 65 /* 0101h */ 66 #define BPP GENMASK(5, 0) 67 68 /* 0102h */ 69 #define PCLKDET_A BIT(7) 70 #define DRIFT_ERR_A BIT(6) 71 #define OVERFLOW_A BIT(5) 72 #define FIFO_WARN_A BIT(4) 73 #define LIM_HEART BIT(2) 74 75 /* 0107h */ 76 #define VID_TX_ACTIVE_B BIT(7) 77 #define VID_TX_ACTIVE_A BIT(6) 78 79 /* 0108h */ 80 #define PCLKDET_B BIT(7) 81 #define DRIFT_ERR_B BIT(6) 82 #define OVERFLOW_B BIT(5) 83 #define FIFO_WARN_B BIT(4) 84 85 /* 0200h */ 86 #define RES_CFG BIT(7) 87 #define TX_COM_EN BIT(5) 88 #define GPIO_OUT BIT(4) 89 #define GPIO_IN BIT(3) 90 #define GPIO_OUT_DIS BIT(0) 91 92 /* 0201h */ 93 #define PULL_UPDN_SEL GENMASK(7, 6) 94 #define OUT_TYPE BIT(5) 95 #define GPIO_TX_ID GENMASK(4, 0) 96 97 /* 0202h */ 98 #define OVR_RES_CFG BIT(7) 99 #define IO_EDGE_RATE GENMASK(6, 5) 100 #define GPIO_RX_ID GENMASK(4, 0) 101 102 /* 0203h */ 103 #define GPIO_IO_RX_EN BIT(5) 104 #define GPIO_OUT_LGC BIT(4) 105 #define GPIO_RX_EN_B BIT(3) 106 #define GPIO_TX_EN_B BIT(2) 107 #define GPIO_RX_EN_A BIT(1) 108 #define GPIO_TX_EN_A BIT(0) 109 110 /* 0750h */ 111 #define FRCZEROPAD GENMASK(7, 6) 112 #define FRCZPEN BIT(5) 113 #define FRCSDGAIN BIT(4) 114 #define FRCSDEN BIT(3) 115 #define FRCGAIN GENMASK(2, 1) 116 #define FRCEN BIT(0) 117 118 /* 0751h */ 119 #define FRCDATAWIDTH BIT(3) 120 #define FRCASYNCEN BIT(2) 121 #define FRCHSPOL BIT(1) 122 #define FRCVSPOL BIT(0) 123 124 /* 0752h */ 125 #define FRCDCMODE GENMASK(1, 0) 126 127 /* 641Ah */ 128 #define DPRX_TRAIN_STATE GENMASK(7, 4) 129 130 /* 7000h */ 131 #define LINK_ENABLE BIT(0) 132 133 /* 7070h */ 134 #define MAX_LANE_COUNT GENMASK(7, 0) 135 136 /* 7074h */ 137 #define MAX_LINK_RATE GENMASK(7, 0) 138 139 enum link_mode { 140 DUAL_LINK, 141 LINKA, 142 LINKB, 143 SPLITTER_MODE, 144 }; 145 146 #endif 147