1 /* 2 * Copyright 2018-2021 NXP 3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 9 #ifndef PLAT_COMMON_H 10 #define PLAT_COMMON_H 11 12 #include <stdbool.h> 13 #include <stddef.h> 14 #include <common/bl_common.h> 15 16 #include <dcfg.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 19 #include <platform_def.h> 20 21 #ifdef IMAGE_BL31 22 23 #define BL31_END (uintptr_t)(&__BL31_END__) 24 25 /******************************************************************************* 26 * This structure represents the superset of information that can be passed to 27 * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be 28 * populated only if BL2 detects its presence. A pointer to a structure of this 29 * type should be passed in X0 to BL31's cold boot entrypoint. 30 * 31 * Use of this structure and the X0 parameter is not mandatory: the BL31 32 * platform code can use other mechanisms to provide the necessary information 33 * about BL32 and BL33 to the common and SPD code. 34 * 35 * BL31 image information is mandatory if this structure is used. If either of 36 * the optional BL32 and BL33 image information is not provided, this is 37 * indicated by the respective image_info pointers being zero. 38 ******************************************************************************/ 39 typedef struct bl31_params { 40 param_header_t h; 41 image_info_t *bl31_image_info; 42 entry_point_info_t *bl32_ep_info; 43 image_info_t *bl32_image_info; 44 entry_point_info_t *bl33_ep_info; 45 image_info_t *bl33_image_info; 46 } bl31_params_t; 47 48 /* BL3 utility functions */ 49 void ls_bl31_early_platform_setup(void *from_bl2, 50 void *plat_params_from_bl2); 51 /* LS Helper functions */ 52 unsigned int plat_my_core_mask(void); 53 unsigned int plat_core_mask(u_register_t mpidr); 54 unsigned int plat_core_pos(u_register_t mpidr); 55 //unsigned int plat_my_core_pos(void); 56 57 /* BL31 Data API(s) */ 58 void _init_global_data(void); 59 void _initialize_psci(void); 60 uint32_t _getCoreState(u_register_t core_mask); 61 void _setCoreState(u_register_t core_mask, u_register_t core_state); 62 63 /* SoC defined structure and API(s) */ 64 void soc_runtime_setup(void); 65 void soc_init(void); 66 void soc_platform_setup(void); 67 void soc_early_platform_setup2(void); 68 #endif /* IMAGE_BL31 */ 69 70 #ifdef IMAGE_BL2 71 void soc_early_init(void); 72 void soc_mem_access(void); 73 void soc_preload_setup(void); 74 void soc_bl2_prepare_exit(void); 75 76 /* IO storage utility functions */ 77 int plat_io_setup(void); 78 int open_backend(const uintptr_t spec); 79 80 void ls_bl2_plat_arch_setup(void); 81 82 enum boot_device { 83 BOOT_DEVICE_IFC_NOR, 84 BOOT_DEVICE_IFC_NAND, 85 BOOT_DEVICE_QSPI, 86 BOOT_DEVICE_EMMC, 87 BOOT_DEVICE_SDHC2_EMMC, 88 BOOT_DEVICE_FLEXSPI_NOR, 89 BOOT_DEVICE_FLEXSPI_NAND, 90 BOOT_DEVICE_NONE 91 }; 92 93 enum boot_device get_boot_dev(void); 94 95 /* DDR Related functions */ 96 #if DDR_INIT 97 #ifdef NXP_WARM_BOOT 98 long long init_ddr(uint32_t wrm_bt_flg); 99 #else 100 long long init_ddr(void); 101 #endif 102 #endif 103 104 /* Board specific weak functions */ 105 bool board_enable_povdd(void); 106 bool board_disable_povdd(void); 107 108 void mmap_add_ddr_region_dynamically(void); 109 #endif /* IMAGE_BL2 */ 110 111 typedef struct { 112 uint64_t addr; 113 uint64_t size; 114 } region_info_t; 115 116 typedef struct { 117 uint64_t num_dram_regions; 118 int64_t total_dram_size; 119 region_info_t region[NUM_DRAM_REGIONS]; 120 } dram_regions_info_t; 121 122 dram_regions_info_t *get_dram_regions_info(void); 123 124 void ls_setup_page_tables(uintptr_t total_base, 125 size_t total_size, 126 uintptr_t code_start, 127 uintptr_t code_limit, 128 uintptr_t rodata_start, 129 uintptr_t rodata_limit 130 #if USE_COHERENT_MEM 131 , uintptr_t coh_start, 132 uintptr_t coh_limit 133 #endif 134 ); 135 136 #define SOC_NAME_MAX_LEN (20) 137 138 /* Structure to define SoC personality */ 139 struct soc_type { 140 char name[SOC_NAME_MAX_LEN]; 141 uint32_t version; 142 uint8_t num_clusters; 143 uint8_t cores_per_cluster; 144 }; 145 void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, 146 uint8_t *num_clusters, uint8_t *cores_per_cluster); 147 148 #define SOC_ENTRY(n, v, ncl, nc) { \ 149 .name = #n, \ 150 .version = SVR_##v, \ 151 .num_clusters = (ncl), \ 152 .cores_per_cluster = (nc)} 153 154 #endif /* PLAT_COMMON_H */ 155