1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2022 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 #ifndef _CORESIGHT_MALI_COMMON_H 23 #define _CORESIGHT_MALI_COMMON_H 24 25 #include <linux/types.h> 26 #include <linux/mali_kbase_debug_coresight_csf.h> 27 28 /* Macros for CoreSight OP types. */ 29 #define WRITE_IMM_OP(_reg_addr, _val) \ 30 { \ 31 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_WRITE_IMM, \ 32 .op.write_imm.reg_addr = _reg_addr, .op.write_imm.val = _val \ 33 } 34 35 #define WRITE_RANGE_OP(_reg_start, _reg_end, _val) \ 36 { \ 37 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_WRITE_IMM_RANGE, \ 38 .op.write_imm_range.reg_start = _reg_start, \ 39 .op.write_imm_range.reg_end = _reg_end, .op.write_imm_range.val = _val \ 40 } 41 42 #define WRITE_PTR_OP(_reg_addr, _ptr) \ 43 { \ 44 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_WRITE, .op.write.reg_addr = _reg_addr, \ 45 .op.write.ptr = _ptr \ 46 } 47 48 #define READ_OP(_reg_addr, _ptr) \ 49 { \ 50 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_READ, .op.read.reg_addr = _reg_addr, \ 51 .op.read.ptr = _ptr \ 52 } 53 54 #define POLL_OP(_reg_addr, _mask, _val) \ 55 { \ 56 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_POLL, .op.poll.reg_addr = _reg_addr, \ 57 .op.poll.mask = _mask, .op.poll.val = _val \ 58 } 59 60 #define BIT_OR_OP(_ptr, _val) \ 61 { \ 62 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_BIT_OR, .op.bitw.ptr = _ptr, \ 63 .op.bitw.val = _val \ 64 } 65 66 #define BIT_XOR_OP(_ptr, _val) \ 67 { \ 68 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_BIT_XOR, .op.bitw.ptr = _ptr, \ 69 .op.bitw.val = _val \ 70 } 71 72 #define BIT_AND_OP(_ptr, _val) \ 73 { \ 74 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_BIT_AND, .op.bitw.ptr = _ptr, \ 75 .op.bitw.val = _val \ 76 } 77 78 #define BIT_NOT_OP(_ptr) \ 79 { \ 80 .type = KBASE_DEBUG_CORESIGHT_CSF_OP_TYPE_BIT_NOT, .op.bitw.ptr = _ptr, \ 81 } 82 83 #ifndef CS_MALI_UNLOCK_COMPONENT 84 /** 85 * CS_MALI_UNLOCK_COMPONENT - A write of 0xC5ACCE55 enables write access to the block 86 */ 87 #define CS_MALI_UNLOCK_COMPONENT 0xC5ACCE55 88 #endif 89 90 /** 91 * struct coresight_mali_drvdata - Coresight mali driver data 92 * 93 * @csdev: Coresight device pointer 94 * @dev: Device pointer 95 * @kbase_client: Pointer to coresight mali client 96 * @config: Pointer to coresight mali config, used for enabling and 97 * disabling the coresight component 98 * @enable_seq: Enable sequence needed to enable coresight block 99 * @disable_seq: Disable sequence needed to enable coresight block 100 * @gpu_dev: Pointer to gpu device structure 101 * @mode: Mode in which the driver operates 102 */ 103 struct coresight_mali_drvdata { 104 struct coresight_device *csdev; 105 struct device *dev; 106 void *kbase_client; 107 void *config; 108 struct kbase_debug_coresight_csf_sequence enable_seq; 109 struct kbase_debug_coresight_csf_sequence disable_seq; 110 void *gpu_dev; 111 u32 mode; 112 }; 113 114 /** 115 * coresight_mali_enable_component - Generic enable for a coresight block 116 * 117 * @csdev: Coresight device to be enabled 118 * @mode: Mode in which the block should start operating in 119 * 120 * Return: 0 if success. Error code on failure. 121 */ 122 int coresight_mali_enable_component(struct coresight_device *csdev, u32 mode); 123 124 /** 125 * coresight_mali_disable_component - Generic disable for a coresight block 126 * 127 * @csdev: Coresight device to be disabled 128 * 129 * Return: 0 if success. Error code on failure. 130 */ 131 int coresight_mali_disable_component(struct coresight_device *csdev); 132 133 #endif /* _CORESIGHT_MALI_COMMON_H */ 134