1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __HAL_DATA_H__ 21 #define __HAL_DATA_H__ 22 23 #if 1//def CONFIG_SINGLE_IMG 24 25 #include "../hal/phydm/phydm_precomp.h" 26 #ifdef CONFIG_BT_COEXIST 27 #include <hal_btcoex.h> 28 #endif 29 30 #ifdef CONFIG_SDIO_HCI 31 #include <hal_sdio.h> 32 #endif 33 #ifdef CONFIG_GSPI_HCI 34 #include <hal_gspi.h> 35 #endif 36 // 37 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 38 // 39 typedef enum _RT_MULTI_FUNC{ 40 RT_MULTI_FUNC_NONE = 0x00, 41 RT_MULTI_FUNC_WIFI = 0x01, 42 RT_MULTI_FUNC_BT = 0x02, 43 RT_MULTI_FUNC_GPS = 0x04, 44 }RT_MULTI_FUNC,*PRT_MULTI_FUNC; 45 // 46 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 47 // 48 typedef enum _RT_POLARITY_CTL { 49 RT_POLARITY_LOW_ACT = 0, 50 RT_POLARITY_HIGH_ACT = 1, 51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 52 53 // For RTL8723 regulator mode. by tynli. 2011.01.14. 54 typedef enum _RT_REGULATOR_MODE { 55 RT_SWITCHING_REGULATOR = 0, 56 RT_LDO_REGULATOR = 1, 57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 58 59 // 60 // Interface type. 61 // 62 typedef enum _INTERFACE_SELECT_PCIE{ 63 INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard 64 INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard 65 INTF_SEL2_PCIe = 2, // PCIe Card 66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 67 68 69 typedef enum _INTERFACE_SELECT_USB{ 70 INTF_SEL0_USB = 0, // USB 71 INTF_SEL1_USB_High_Power = 1, // USB with high power PA 72 INTF_SEL2_MINICARD = 2, // Minicard 73 INTF_SEL3_USB_Solo = 3, // USB solo-Slim module 74 INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module 75 INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card 76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 77 78 typedef enum _RT_AMPDU_BRUST_MODE{ 79 RT_AMPDU_BRUST_NONE = 0, 80 RT_AMPDU_BRUST_92D = 1, 81 RT_AMPDU_BRUST_88E = 2, 82 RT_AMPDU_BRUST_8812_4 = 3, 83 RT_AMPDU_BRUST_8812_8 = 4, 84 RT_AMPDU_BRUST_8812_12 = 5, 85 RT_AMPDU_BRUST_8812_15 = 6, 86 RT_AMPDU_BRUST_8723B = 7, 87 }RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE; 88 89 #define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number 90 #define CHANNEL_MAX_NUMBER_2G 14 91 #define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A" 92 #define CHANNEL_MAX_NUMBER_5G_80M 7 93 #define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups 94 #define MAX_PG_GROUP 13 95 96 // Tx Power Limit Table Size 97 #define MAX_REGULATION_NUM 4 98 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 99 #define MAX_2_4G_BANDWITH_NUM 2 100 #define MAX_RATE_SECTION_NUM 10 101 #define MAX_5G_BANDWITH_NUM 4 102 103 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4 104 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4 105 106 107 //###### duplicate code,will move to ODM ######### 108 //#define IQK_MAC_REG_NUM 4 109 //#define IQK_ADDA_REG_NUM 16 110 111 //#define IQK_BB_REG_NUM 10 112 #define IQK_BB_REG_NUM_92C 9 113 #define IQK_BB_REG_NUM_92D 10 114 #define IQK_BB_REG_NUM_test 6 115 116 #define IQK_Matrix_Settings_NUM_92D 1+24+21 117 118 //#define HP_THERMAL_NUM 8 119 //###### duplicate code,will move to ODM ######### 120 121 #ifdef CONFIG_USB_RX_AGGREGATION 122 typedef enum _USB_RX_AGG_MODE{ 123 USB_RX_AGG_DISABLE, 124 USB_RX_AGG_DMA, 125 USB_RX_AGG_USB, 126 USB_RX_AGG_MIX 127 }USB_RX_AGG_MODE; 128 129 //#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer 130 131 #endif 132 133 /* For store initial value of BB register */ 134 typedef struct _BB_INIT_REGISTER { 135 u16 offset; 136 u32 value; 137 138 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 139 140 #define PAGE_SIZE_128 128 141 #define PAGE_SIZE_256 256 142 #define PAGE_SIZE_512 512 143 144 #define HCI_SUS_ENTER 0 145 #define HCI_SUS_LEAVING 1 146 #define HCI_SUS_LEAVE 2 147 #define HCI_SUS_ENTERING 3 148 #define HCI_SUS_ERR 4 149 150 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 151 typedef enum _ACS_OP { 152 ACS_INIT, /*ACS - Variable init*/ 153 ACS_RESET, /*ACS - NHM Counter reset*/ 154 ACS_SELECT, /*ACS - NHM Counter Statistics */ 155 } ACS_OP; 156 157 typedef enum _ACS_STATE { 158 ACS_DISABLE, 159 ACS_ENABLE, 160 } ACS_STATE; 161 162 struct auto_chan_sel { 163 ATOMIC_T state; 164 u8 ch; /* previous channel*/ 165 }; 166 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 167 168 #define EFUSE_FILE_UNUSED 0 169 #define EFUSE_FILE_FAILED 1 170 #define EFUSE_FILE_LOADED 2 171 172 #define MACADDR_FILE_UNUSED 0 173 #define MACADDR_FILE_FAILED 1 174 #define MACADDR_FILE_LOADED 2 175 176 #define KFREE_FLAG_ON BIT0 177 #define KFREE_FLAG_THERMAL_K_ON BIT1 178 179 struct kfree_data_t { 180 u8 flag; 181 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 182 #ifdef CONFIG_RTL8814A 183 s8 pa_bias_5g[RF_PATH_MAX]; 184 s8 pad_bias_5g[RF_PATH_MAX]; 185 #endif 186 s8 thermal; 187 }; 188 189 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 190 191 typedef struct hal_com_data 192 { 193 HAL_VERSION VersionID; 194 RT_MULTI_FUNC MultiFunc; // For multi-function consideration. 195 RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. 196 RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO 197 u8 hw_init_completed; 198 /****** FW related ******/ 199 u16 FirmwareVersion; 200 u16 FirmwareVersionRev; 201 u16 FirmwareSubVersion; 202 u16 FirmwareSignature; 203 u8 RegFWOffload; 204 u8 fw_ractrl; 205 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ 206 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 207 208 /****** current WIFI_PHY values ******/ 209 WIRELESS_MODE CurrentWirelessMode; 210 CHANNEL_WIDTH CurrentChannelBW; 211 BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ 212 BAND_TYPE BandSet; 213 u8 CurrentChannel; 214 u8 CurrentCenterFrequencyIndex1; 215 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 216 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 217 BOOLEAN bSwChnlAndSetBWInProgress; 218 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 219 u16 BasicRateSet; 220 u32 ReceiveConfig; 221 BOOLEAN bSwChnl; 222 BOOLEAN bSetChnlBW; 223 BOOLEAN bChnlBWInitialized; 224 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 225 struct auto_chan_sel acs; 226 #endif 227 /****** rf_ctrl *****/ 228 u8 rf_chip; 229 u8 rf_type; 230 u8 PackageType; 231 u8 NumTotalRFPath; 232 233 /****** Debug ******/ 234 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 235 u8 u1ForcedIgiLb; /* forced IGI lower bound */ 236 u8 bDumpRxPkt; 237 u8 bDumpTxPkt; 238 u8 bDisableTXPowerTraining; 239 240 241 /****** EEPROM setting.******/ 242 u8 bautoload_fail_flag; 243 u8 efuse_file_status; 244 u8 macaddr_file_status; 245 u8 EepromOrEfuse; 246 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 247 u8 InterfaceSel; /* board type kept in eFuse */ 248 u16 CustomerID; 249 250 u16 EEPROMVID; 251 u16 EEPROMSVID; 252 #ifdef CONFIG_USB_HCI 253 u16 EEPROMPID; 254 u16 EEPROMSDID; 255 #endif 256 #ifdef CONFIG_PCI_HCI 257 u16 EEPROMDID; 258 u16 EEPROMSMID; 259 #endif 260 261 u8 EEPROMCustomerID; 262 u8 EEPROMSubCustomerID; 263 u8 EEPROMVersion; 264 u8 EEPROMRegulatory; 265 u8 EEPROMThermalMeter; 266 u8 EEPROMBluetoothCoexist; 267 u8 EEPROMBluetoothType; 268 u8 EEPROMBluetoothAntNum; 269 u8 EEPROMBluetoothAntIsolation; 270 u8 EEPROMBluetoothRadioShared; 271 u8 bTXPowerDataReadFromEEPORM; 272 u8 EEPROMMACAddr[ETH_ALEN]; 273 274 #ifdef CONFIG_RF_GAIN_OFFSET 275 u8 EEPROMRFGainOffset; 276 u8 EEPROMRFGainVal; 277 struct kfree_data_t kfree_data; 278 #endif /*CONFIG_RF_GAIN_OFFSET*/ 279 280 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) 281 u8 adjuseVoltageVal; 282 #endif 283 u8 EfuseUsedPercentage; 284 u16 EfuseUsedBytes; 285 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 286 EFUSE_HAL EfuseHal; 287 288 /*---------------------------------------------------------------------------------*/ 289 //3 [2.4G] 290 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 291 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 292 //If only one tx, only BW20 and OFDM are used. 293 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 294 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 295 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 296 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 297 //3 [5G] 298 u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 299 u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 300 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 301 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 302 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 303 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 304 305 u8 Regulation2_4G; 306 u8 Regulation5G; 307 308 u8 TxPwrInPercentage; 309 310 /******************************** 311 * TX power by rate table at most 4RF path. 312 * The register is 313 * 314 * VHT TX power by rate off setArray = 315 * Band:-2G&5G = 0 / 1 316 * RF: at most 4*4 = ABCD=0/1/2/3 317 * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 318 **********************************/ 319 u8 TxPwrByRateTable; 320 u8 TxPwrByRateBand; 321 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 322 [TX_PWR_BY_RATE_NUM_RF] 323 [TX_PWR_BY_RATE_NUM_RF] 324 [TX_PWR_BY_RATE_NUM_RATE]; 325 //---------------------------------------------------------------------------------// 326 327 //2 Power Limit Table 328 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 329 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr 330 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr 331 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff 332 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff 333 334 // Power Limit Table for 2.4G 335 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] 336 [MAX_2_4G_BANDWITH_NUM] 337 [MAX_RATE_SECTION_NUM] 338 [CHANNEL_MAX_NUMBER_2G] 339 [MAX_RF_PATH_NUM]; 340 341 // Power Limit Table for 5G 342 s8 TxPwrLimit_5G[MAX_REGULATION_NUM] 343 [MAX_5G_BANDWITH_NUM] 344 [MAX_RATE_SECTION_NUM] 345 [CHANNEL_MAX_NUMBER_5G] 346 [MAX_RF_PATH_NUM]; 347 348 349 // Store the original power by rate value of the base of each rate section of rf path A & B 350 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 351 [TX_PWR_BY_RATE_NUM_RF] 352 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 353 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 354 [TX_PWR_BY_RATE_NUM_RF] 355 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 356 357 // For power group 358 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 359 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 360 u8 PGMaxGroup; 361 362 // The current Tx Power Level 363 u8 CurrentCckTxPwrIdx; 364 u8 CurrentOfdm24GTxPwrIdx; 365 u8 CurrentBW2024GTxPwrIdx; 366 u8 CurrentBW4024GTxPwrIdx; 367 368 // Read/write are allow for following hardware information variables 369 u8 pwrGroupCnt; 370 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 371 u32 CCKTxPowerLevelOriginalOffset; 372 373 u8 CrystalCap; 374 375 u8 PAType_2G; 376 u8 PAType_5G; 377 u8 LNAType_2G; 378 u8 LNAType_5G; 379 u8 ExternalPA_2G; 380 u8 ExternalLNA_2G; 381 u8 ExternalPA_5G; 382 u8 ExternalLNA_5G; 383 u8 TypeGLNA; 384 u8 TypeGPA; 385 u8 TypeALNA; 386 u8 TypeAPA; 387 u8 RFEType; 388 389 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 390 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 391 392 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D 393 394 u32 RfRegChnlVal[MAX_RF_PATH]; 395 396 //RDG enable 397 BOOLEAN bRDGEnable; 398 399 u8 RegTxPause; 400 // Beacon function related global variable. 401 u8 RegBcnCtrlVal; 402 u8 RegFwHwTxQCtrl; 403 u8 RegReg542; 404 u8 RegCR_1; 405 u8 Reg837; 406 u16 RegRRSR; 407 408 /****** antenna diversity ******/ 409 u8 CurAntenna; 410 u8 AntDivCfg; 411 u8 AntDetection; 412 u8 TRxAntDivType; 413 u8 ant_path; //for 8723B s0/s1 selection 414 u32 AntennaTxPath; /* Antenna path Tx */ 415 u32 AntennaRxPath; /* Antenna path Rx */ 416 417 /******** PHY DM & DM Section **********/ 418 u8 DM_Type; 419 _lock IQKSpinLock; 420 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 421 /* Upper and Lower Signal threshold for Rate Adaptive*/ 422 int EntryMinUndecoratedSmoothedPWDB; 423 int EntryMaxUndecoratedSmoothedPWDB; 424 int MinUndecoratedPWDBForDM; 425 DM_ODM_T odmpriv; 426 u8 bIQKInitialized; 427 u8 bNeedIQK; 428 /******** PHY DM & DM Section **********/ 429 430 431 432 // 2010/08/09 MH Add CU power down mode. 433 BOOLEAN pwrdown; 434 435 // Add for dual MAC 0--Mac0 1--Mac1 436 u32 interfaceIndex; 437 438 #ifdef CONFIG_P2P 439 u8 p2p_ps_offload; 440 #endif 441 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 442 u8 bMacPwrCtrlOn; 443 u8 hci_sus_state; 444 445 u8 RegIQKFWOffload; 446 struct submit_ctx iqk_sctx; 447 448 RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully 449 450 u8 OutEpQueueSel; 451 u8 OutEpNumber; 452 453 #if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 454 // 455 // For SDIO Interface HAL related 456 // 457 458 // 459 // SDIO ISR Related 460 // 461 // u32 IntrMask[1]; 462 // u32 IntrMaskToSet[1]; 463 // LOG_INTERRUPT InterruptLog; 464 u32 sdio_himr; 465 u32 sdio_hisr; 466 467 // 468 // SDIO Tx FIFO related. 469 // 470 // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg 471 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 472 _lock SdioTxFIFOFreePageLock; 473 u8 SdioTxOQTMaxFreeSpace; 474 u8 SdioTxOQTFreeSpace; 475 476 // 477 // SDIO Rx FIFO related. 478 // 479 u8 SdioRxFIFOCnt; 480 u16 SdioRxFIFOSize; 481 482 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue 483 #endif //CONFIG_SDIO_HCI 484 485 #ifdef CONFIG_USB_HCI 486 487 // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. 488 BOOLEAN UsbRxHighSpeedMode; 489 BOOLEAN UsbTxVeryHighSpeedMode; 490 u32 UsbBulkOutSize; 491 BOOLEAN bSupportUSB3; 492 493 // Interrupt relatd register information. 494 u32 IntArray[3];//HISR0,HISR1,HSISR 495 u32 IntrMask[3]; 496 u8 C2hArray[16]; 497 #ifdef CONFIG_USB_TX_AGGREGATION 498 u8 UsbTxAggMode; 499 u8 UsbTxAggDescNum; 500 #endif // CONFIG_USB_TX_AGGREGATION 501 502 #ifdef CONFIG_USB_RX_AGGREGATION 503 u16 HwRxPageSize; // Hardware setting 504 u32 MaxUsbRxAggBlock; 505 506 USB_RX_AGG_MODE UsbRxAggMode; 507 u8 UsbRxAggBlockCount; /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */ 508 u8 UsbRxAggBlockTimeout; 509 u8 UsbRxAggPageCount; /* FOR DMA Mode, 8192C DMA page count*/ 510 u8 UsbRxAggPageTimeout; 511 512 u8 RegAcUsbDmaSize; 513 u8 RegAcUsbDmaTime; 514 #endif//CONFIG_USB_RX_AGGREGATION 515 #endif //CONFIG_USB_HCI 516 517 518 #ifdef CONFIG_PCI_HCI 519 // 520 // EEPROM setting. 521 // 522 u32 TransmitConfig; 523 u32 IntrMaskToSet[2]; 524 u32 IntArray[2]; 525 u32 IntrMask[2]; 526 u32 SysIntArray[1]; 527 u32 SysIntrMask[1]; 528 u32 IntrMaskReg[2]; 529 u32 IntrMaskDefault[2]; 530 531 BOOLEAN bL1OffSupport; 532 BOOLEAN bSupportBackDoor; 533 534 u8 bDefaultAntenna; 535 536 u8 bInterruptMigration; 537 u8 bDisableTxInt; 538 539 u16 RxTag; 540 #endif //CONFIG_PCI_HCI 541 542 543 #ifdef DBG_CONFIG_ERROR_DETECT 544 struct sreset_priv srestpriv; 545 #endif //#ifdef DBG_CONFIG_ERROR_DETECT 546 547 #ifdef CONFIG_BT_COEXIST 548 // For bluetooth co-existance 549 BT_COEXIST bt_coexist; 550 #endif // CONFIG_BT_COEXIST 551 552 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F) 553 #ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI 554 // Interrupt relatd register information. 555 u32 SysIntrStatus; 556 u32 SysIntrMask; 557 #endif 558 #endif /*endif CONFIG_RTL8723B */ 559 560 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 561 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 562 char *mac_reg; 563 u32 mac_reg_len; 564 char *bb_phy_reg; 565 u32 bb_phy_reg_len; 566 char *bb_agc_tab; 567 u32 bb_agc_tab_len; 568 char *bb_phy_reg_pg; 569 u32 bb_phy_reg_pg_len; 570 char *bb_phy_reg_mp; 571 u32 bb_phy_reg_mp_len; 572 char *rf_radio_a; 573 u32 rf_radio_a_len; 574 char *rf_radio_b; 575 u32 rf_radio_b_len; 576 char *rf_tx_pwr_track; 577 u32 rf_tx_pwr_track_len; 578 char *rf_tx_pwr_lmt; 579 u32 rf_tx_pwr_lmt_len; 580 #endif 581 582 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 583 s16 noise[ODM_MAX_CHANNEL_NUM]; 584 #endif 585 586 u8 macid_num; 587 u8 cam_entry_num; 588 u8 sec_cap; 589 u8 RfKFreeEnable; 590 BOOLEAN bCCKinCH14; 591 BB_INIT_REGISTER BBRegForRecover[6]; 592 593 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 594 595 596 597 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 598 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) 599 600 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath ) 601 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 602 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) 603 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 604 605 #define SUPPORT_HW_RADIO_DETECT(Adapter) ( RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\ 606 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\ 607 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 608 609 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 610 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 611 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 612 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 613 #endif 614 615 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 616 #define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) 617 #define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) 618 #define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) 619 #define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) 620 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 621 622 #endif //__HAL_DATA_H__ 623 624