1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef __AW_PID_2049_REG_H__ 4 #define __AW_PID_2049_REG_H__ 5 6 /* registers list */ 7 #define AW_PID_2049_ID_REG (0x00) 8 #define AW_PID_2049_SYSST_REG (0x01) 9 #define AW_PID_2049_SYSINT_REG (0x02) 10 #define AW_PID_2049_SYSINTM_REG (0x03) 11 #define AW_PID_2049_SYSCTRL_REG (0x04) 12 #define AW_PID_2049_SYSCTRL2_REG (0x05) 13 #define AW_PID_2049_I2SCTRL_REG (0x06) 14 #define AW_PID_2049_I2SCFG1_REG (0x07) 15 #define AW_PID_2049_I2SCFG2_REG (0x08) 16 #define AW_PID_2049_HAGCCFG1_REG (0x09) 17 #define AW_PID_2049_HAGCCFG2_REG (0x0A) 18 #define AW_PID_2049_HAGCCFG3_REG (0x0B) 19 #define AW_PID_2049_HAGCCFG4_REG (0x0C) 20 #define AW_PID_2049_HAGCCFG5_REG (0x0D) 21 #define AW_PID_2049_HAGCCFG6_REG (0x0E) 22 #define AW_PID_2049_HAGCCFG7_REG (0x0F) 23 #define AW_PID_2049_MPDCFG_REG (0x10) 24 #define AW_PID_2049_PWMCTRL_REG (0x11) 25 #define AW_PID_2049_I2SCFG3_REG (0x12) 26 #define AW_PID_2049_DBGCTRL_REG (0x13) 27 #define AW_PID_2049_HAGCST_REG (0x20) 28 #define AW_PID_2049_VBAT_REG (0x21) 29 #define AW_PID_2049_TEMP_REG (0x22) 30 #define AW_PID_2049_PVDD_REG (0x23) 31 #define AW_PID_2049_ISNDAT_REG (0x24) 32 #define AW_PID_2049_VSNDAT_REG (0x25) 33 #define AW_PID_2049_I2SINT_REG (0x26) 34 #define AW_PID_2049_I2SCAPCNT_REG (0x27) 35 #define AW_PID_2049_ANASTA1_REG (0x28) 36 #define AW_PID_2049_ANASTA2_REG (0x29) 37 #define AW_PID_2049_ANASTA3_REG (0x2A) 38 #define AW_PID_2049_ANASTA4_REG (0x2B) 39 #define AW_PID_2049_TESTDET_REG (0x2C) 40 #define AW_PID_2049_TESTIN_REG (0x38) 41 #define AW_PID_2049_TESTOUT_REG (0x39) 42 #define AW_PID_2049_DSPMADD_REG (0x40) 43 #define AW_PID_2049_DSPMDAT_REG (0x41) 44 #define AW_PID_2049_WDT_REG (0x42) 45 #define AW_PID_2049_ACR1_REG (0x43) 46 #define AW_PID_2049_ACR2_REG (0x44) 47 #define AW_PID_2049_ASR1_REG (0x45) 48 #define AW_PID_2049_ASR2_REG (0x46) 49 #define AW_PID_2049_DSPCFG_REG (0x47) 50 #define AW_PID_2049_ASR3_REG (0x48) 51 #define AW_PID_2049_ASR4_REG (0x49) 52 #define AW_PID_2049_VSNCTRL1_REG (0x50) 53 #define AW_PID_2049_ISNCTRL1_REG (0x51) 54 #define AW_PID_2049_PLLCTRL1_REG (0x52) 55 #define AW_PID_2049_PLLCTRL2_REG (0x53) 56 #define AW_PID_2049_PLLCTRL3_REG (0x54) 57 #define AW_PID_2049_CDACTRL1_REG (0x55) 58 #define AW_PID_2049_CDACTRL2_REG (0x56) 59 #define AW_PID_2049_SADCCTRL1_REG (0x57) 60 #define AW_PID_2049_SADCCTRL2_REG (0x58) 61 #define AW_PID_2049_CPCTRL1_REG (0x59) 62 #define AW_PID_2049_BSTCTRL1_REG (0x60) 63 #define AW_PID_2049_BSTCTRL2_REG (0x61) 64 #define AW_PID_2049_BSTCTRL3_REG (0x62) 65 #define AW_PID_2049_BSTCTRL4_REG (0x63) 66 #define AW_PID_2049_BSTCTRL5_REG (0x64) 67 #define AW_PID_2049_BSTCTRL6_REG (0x65) 68 #define AW_PID_2049_BSTCTRL7_REG (0x66) 69 #define AW_PID_2049_DSMCFG1_REG (0x67) 70 #define AW_PID_2049_DSMCFG2_REG (0x68) 71 #define AW_PID_2049_DSMCFG3_REG (0x69) 72 #define AW_PID_2049_DSMCFG4_REG (0x6A) 73 #define AW_PID_2049_DSMCFG5_REG (0x6B) 74 #define AW_PID_2049_DSMCFG6_REG (0x6C) 75 #define AW_PID_2049_DSMCFG7_REG (0x6D) 76 #define AW_PID_2049_DSMCFG8_REG (0x6E) 77 #define AW_PID_2049_TESTCTRL1_REG (0x70) 78 #define AW_PID_2049_TESTCTRL2_REG (0x71) 79 #define AW_PID_2049_EFCTRL1_REG (0x72) 80 #define AW_PID_2049_EFCTRL2_REG (0x73) 81 #define AW_PID_2049_EFWH_REG (0x74) 82 #define AW_PID_2049_EFWM2_REG (0x75) 83 #define AW_PID_2049_EFWM1_REG (0x76) 84 #define AW_PID_2049_EFWL_REG (0x77) 85 #define AW_PID_2049_EFRH_REG (0x78) 86 #define AW_PID_2049_EFRM2_REG (0x79) 87 #define AW_PID_2049_EFRM1_REG (0x7A) 88 #define AW_PID_2049_EFRL_REG (0x7B) 89 #define AW_PID_2049_TM_REG (0x7C) 90 91 /******************************************** 92 * Register Access 93 *******************************************/ 94 enum aw883xx_id { 95 AW883XX_PID_2049 = 0x2049, 96 }; 97 98 #define AW_PID_2049_REG_MAX (0x7D) 99 100 #define REG_NONE_ACCESS (0) 101 #define REG_RD_ACCESS (1 << 0) 102 #define REG_WR_ACCESS (1 << 1) 103 104 static const unsigned char aw_pid_2049_reg_access[AW_PID_2049_REG_MAX] = { 105 [AW_PID_2049_ID_REG] = (REG_RD_ACCESS), 106 [AW_PID_2049_SYSST_REG] = (REG_RD_ACCESS), 107 [AW_PID_2049_SYSINT_REG] = (REG_RD_ACCESS), 108 [AW_PID_2049_SYSINTM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 109 [AW_PID_2049_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 110 [AW_PID_2049_SYSCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 111 [AW_PID_2049_I2SCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 112 [AW_PID_2049_I2SCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 113 [AW_PID_2049_I2SCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 114 [AW_PID_2049_HAGCCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 115 [AW_PID_2049_HAGCCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 116 [AW_PID_2049_HAGCCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 117 [AW_PID_2049_HAGCCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 118 [AW_PID_2049_HAGCCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 119 [AW_PID_2049_HAGCCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 120 [AW_PID_2049_HAGCCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 121 [AW_PID_2049_MPDCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 122 [AW_PID_2049_PWMCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 123 [AW_PID_2049_I2SCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 124 [AW_PID_2049_DBGCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 125 [AW_PID_2049_HAGCST_REG] = (REG_RD_ACCESS), 126 [AW_PID_2049_VBAT_REG] = (REG_RD_ACCESS), 127 [AW_PID_2049_TEMP_REG] = (REG_RD_ACCESS), 128 [AW_PID_2049_PVDD_REG] = (REG_RD_ACCESS), 129 [AW_PID_2049_ISNDAT_REG] = (REG_RD_ACCESS), 130 [AW_PID_2049_VSNDAT_REG] = (REG_RD_ACCESS), 131 [AW_PID_2049_I2SINT_REG] = (REG_RD_ACCESS), 132 [AW_PID_2049_I2SCAPCNT_REG] = (REG_RD_ACCESS), 133 [AW_PID_2049_ANASTA1_REG] = (REG_RD_ACCESS), 134 [AW_PID_2049_ANASTA2_REG] = (REG_RD_ACCESS), 135 [AW_PID_2049_ANASTA3_REG] = (REG_RD_ACCESS), 136 [AW_PID_2049_ANASTA4_REG] = (REG_RD_ACCESS), 137 [AW_PID_2049_TESTDET_REG] = (REG_RD_ACCESS), 138 [AW_PID_2049_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 139 [AW_PID_2049_TESTOUT_REG] = (REG_RD_ACCESS), 140 [AW_PID_2049_DSPMADD_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 141 [AW_PID_2049_DSPMDAT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 142 [AW_PID_2049_WDT_REG] = (REG_RD_ACCESS), 143 [AW_PID_2049_ACR1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 144 [AW_PID_2049_ACR2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 145 [AW_PID_2049_ASR1_REG] = (REG_RD_ACCESS), 146 [AW_PID_2049_ASR2_REG] = (REG_RD_ACCESS), 147 [AW_PID_2049_DSPCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 148 [AW_PID_2049_ASR3_REG] = (REG_RD_ACCESS), 149 [AW_PID_2049_ASR4_REG] = (REG_RD_ACCESS), 150 [AW_PID_2049_VSNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 151 [AW_PID_2049_ISNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 152 [AW_PID_2049_PLLCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 153 [AW_PID_2049_PLLCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 154 [AW_PID_2049_PLLCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 155 [AW_PID_2049_CDACTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 156 [AW_PID_2049_CDACTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 157 [AW_PID_2049_SADCCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 158 [AW_PID_2049_SADCCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 159 [AW_PID_2049_CPCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 160 [AW_PID_2049_BSTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 161 [AW_PID_2049_BSTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 162 [AW_PID_2049_BSTCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 163 [AW_PID_2049_BSTCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 164 [AW_PID_2049_BSTCTRL5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 165 [AW_PID_2049_BSTCTRL6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 166 [AW_PID_2049_BSTCTRL7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 167 [AW_PID_2049_DSMCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 168 [AW_PID_2049_DSMCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 169 [AW_PID_2049_DSMCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 170 [AW_PID_2049_DSMCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 171 [AW_PID_2049_DSMCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 172 [AW_PID_2049_DSMCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 173 [AW_PID_2049_DSMCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 174 [AW_PID_2049_DSMCFG8_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 175 [AW_PID_2049_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 176 [AW_PID_2049_TESTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 177 [AW_PID_2049_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 178 [AW_PID_2049_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 179 [AW_PID_2049_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 180 [AW_PID_2049_EFWM2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 181 [AW_PID_2049_EFWM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 182 [AW_PID_2049_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 183 [AW_PID_2049_EFRH_REG] = (REG_RD_ACCESS), 184 [AW_PID_2049_EFRM2_REG] = (REG_RD_ACCESS), 185 [AW_PID_2049_EFRM1_REG] = (REG_RD_ACCESS), 186 [AW_PID_2049_EFRL_REG] = (REG_RD_ACCESS), 187 [AW_PID_2049_TM_REG] = (REG_NONE_ACCESS), 188 }; 189 190 #define AW_PID_2049_VOLUME_STEP_DB (6 * 8) 191 192 193 /* detail information of registers begin */ 194 /* ID (0x00) detail */ 195 /* IDCODE bit 15:0 (ID 0x00) */ 196 #define AW_PID_2049_IDCODE_START_BIT (0) 197 #define AW_PID_2049_IDCODE_BITS_LEN (16) 198 #define AW_PID_2049_IDCODE_MASK \ 199 (~(((1<<AW_PID_2049_IDCODE_BITS_LEN)-1) << AW_PID_2049_IDCODE_START_BIT)) 200 201 #define AW_PID_2049_IDCODE_DEFAULT_VALUE (0x2049) 202 #define AW_PID_2049_IDCODE_DEFAULT \ 203 (AW_PID_2049_IDCODE_DEFAULT_VALUE << AW_PID_2049_IDCODE_START_BIT) 204 205 #define AW_PID_2049_SOFT_RESET_VALUE (0x55aa) 206 207 /* default value of ID (0x00) */ 208 /* #define AW_PID_2049_ID_DEFAULT (0x2049) */ 209 210 /* SYSST (0x01) detail */ 211 /* OVP2S bit 15 (SYSST 0x01) */ 212 #define AW_PID_2049_OVP2S_START_BIT (15) 213 #define AW_PID_2049_OVP2S_BITS_LEN (1) 214 #define AW_PID_2049_OVP2S_MASK \ 215 (~(((1<<AW_PID_2049_OVP2S_BITS_LEN)-1) << AW_PID_2049_OVP2S_START_BIT)) 216 217 #define AW_PID_2049_OVP2S_NORMAL (0) 218 #define AW_PID_2049_OVP2S_NORMAL_VALUE \ 219 (AW_PID_2049_OVP2S_NORMAL << AW_PID_2049_OVP2S_START_BIT) 220 221 #define AW_PID_2049_OVP2S_OVP (1) 222 #define AW_PID_2049_OVP2S_OVP_VALUE \ 223 (AW_PID_2049_OVP2S_OVP << AW_PID_2049_OVP2S_START_BIT) 224 225 #define AW_PID_2049_OVP2S_DEFAULT_VALUE (0) 226 #define AW_PID_2049_OVP2S_DEFAULT \ 227 (AW_PID_2049_OVP2S_DEFAULT_VALUE << AW_PID_2049_OVP2S_START_BIT) 228 229 /* UVLS bit 14 (SYSST 0x01) */ 230 #define AW_PID_2049_UVLS_START_BIT (14) 231 #define AW_PID_2049_UVLS_BITS_LEN (1) 232 #define AW_PID_2049_UVLS_MASK \ 233 (~(((1<<AW_PID_2049_UVLS_BITS_LEN)-1) << AW_PID_2049_UVLS_START_BIT)) 234 235 #define AW_PID_2049_UVLS_NORMAL (0) 236 #define AW_PID_2049_UVLS_NORMAL_VALUE \ 237 (AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT) 238 239 #define AW_PID_2049_UVLS_UVLO (1) 240 #define AW_PID_2049_UVLS_UVLO_VALUE \ 241 (AW_PID_2049_UVLS_UVLO << AW_PID_2049_UVLS_START_BIT) 242 243 #define AW_PID_2049_UVLS_DEFAULT_VALUE (0) 244 #define AW_PID_2049_UVLS_DEFAULT \ 245 (AW_PID_2049_UVLS_DEFAULT_VALUE << AW_PID_2049_UVLS_START_BIT) 246 247 /* ADPS bit 13 (SYSST 0x01) */ 248 #define AW_PID_2049_ADPS_START_BIT (13) 249 #define AW_PID_2049_ADPS_BITS_LEN (1) 250 #define AW_PID_2049_ADPS_MASK \ 251 (~(((1<<AW_PID_2049_ADPS_BITS_LEN)-1) << AW_PID_2049_ADPS_START_BIT)) 252 253 #define AW_PID_2049_ADPS_TRANSPARENT (0) 254 #define AW_PID_2049_ADPS_TRANSPARENT_VALUE \ 255 (AW_PID_2049_ADPS_TRANSPARENT << AW_PID_2049_ADPS_START_BIT) 256 257 #define AW_PID_2049_ADPS_BOOST (1) 258 #define AW_PID_2049_ADPS_BOOST_VALUE \ 259 (AW_PID_2049_ADPS_BOOST << AW_PID_2049_ADPS_START_BIT) 260 261 #define AW_PID_2049_ADPS_DEFAULT_VALUE (0) 262 #define AW_PID_2049_ADPS_DEFAULT \ 263 (AW_PID_2049_ADPS_DEFAULT_VALUE << AW_PID_2049_ADPS_START_BIT) 264 265 /* DSPS bit 12 (SYSST 0x01) */ 266 #define AW_PID_2049_DSPS_START_BIT (12) 267 #define AW_PID_2049_DSPS_BITS_LEN (1) 268 #define AW_PID_2049_DSPS_MASK \ 269 (~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT)) 270 271 #define AW_PID_2049_DSPS_NORMAL (0) 272 #define AW_PID_2049_DSPS_NORMAL_VALUE \ 273 (AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT) 274 275 #define AW_PID_2049_DSPS_DSP_STABLE (1) 276 #define AW_PID_2049_DSPS_DSP_STABLE_VALUE \ 277 (AW_PID_2049_DSPS_DSP_STABLE << AW_PID_2049_DSPS_START_BIT) 278 279 #define AW_PID_2049_DSPS_DEFAULT_VALUE (0) 280 #define AW_PID_2049_DSPS_DEFAULT \ 281 (AW_PID_2049_DSPS_DEFAULT_VALUE << AW_PID_2049_DSPS_START_BIT) 282 283 /* BSTOCS bit 11 (SYSST 0x01) */ 284 #define AW_PID_2049_BSTOCS_START_BIT (11) 285 #define AW_PID_2049_BSTOCS_BITS_LEN (1) 286 #define AW_PID_2049_BSTOCS_MASK \ 287 (~(((1<<AW_PID_2049_BSTOCS_BITS_LEN)-1) << AW_PID_2049_BSTOCS_START_BIT)) 288 289 #define AW_PID_2049_BSTOCS_NORMAL (0) 290 #define AW_PID_2049_BSTOCS_NORMAL_VALUE \ 291 (AW_PID_2049_BSTOCS_NORMAL << AW_PID_2049_BSTOCS_START_BIT) 292 293 #define AW_PID_2049_BSTOCS_OVER_CURRENT (1) 294 #define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE \ 295 (AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT) 296 297 #define AW_PID_2049_BSTOCS_DEFAULT_VALUE (0) 298 #define AW_PID_2049_BSTOCS_DEFAULT \ 299 (AW_PID_2049_BSTOCS_DEFAULT_VALUE << AW_PID_2049_BSTOCS_START_BIT) 300 301 /* OVPS bit 10 (SYSST 0x01) */ 302 #define AW_PID_2049_OVPS_START_BIT (10) 303 #define AW_PID_2049_OVPS_BITS_LEN (1) 304 #define AW_PID_2049_OVPS_MASK \ 305 (~(((1<<AW_PID_2049_OVPS_BITS_LEN)-1) << AW_PID_2049_OVPS_START_BIT)) 306 307 #define AW_PID_2049_OVPS_NORMAL (0) 308 #define AW_PID_2049_OVPS_NORMAL_VALUE \ 309 (AW_PID_2049_OVPS_NORMAL << AW_PID_2049_OVPS_START_BIT) 310 311 #define AW_PID_2049_OVPS_OVP (1) 312 #define AW_PID_2049_OVPS_OVP_VALUE \ 313 (AW_PID_2049_OVPS_OVP << AW_PID_2049_OVPS_START_BIT) 314 315 #define AW_PID_2049_OVPS_DEFAULT_VALUE (0) 316 #define AW_PID_2049_OVPS_DEFAULT \ 317 (AW_PID_2049_OVPS_DEFAULT_VALUE << AW_PID_2049_OVPS_START_BIT) 318 319 /* BSTS bit 9 (SYSST 0x01) */ 320 #define AW_PID_2049_BSTS_START_BIT (9) 321 #define AW_PID_2049_BSTS_BITS_LEN (1) 322 #define AW_PID_2049_BSTS_MASK \ 323 (~(((1<<AW_PID_2049_BSTS_BITS_LEN)-1) << AW_PID_2049_BSTS_START_BIT)) 324 325 #define AW_PID_2049_BSTS_NOT_FINISHED (0) 326 #define AW_PID_2049_BSTS_NOT_FINISHED_VALUE \ 327 (AW_PID_2049_BSTS_NOT_FINISHED << AW_PID_2049_BSTS_START_BIT) 328 329 #define AW_PID_2049_BSTS_FINISHED (1) 330 #define AW_PID_2049_BSTS_FINISHED_VALUE \ 331 (AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT) 332 333 #define AW_PID_2049_BSTS_DEFAULT_VALUE (0) 334 #define AW_PID_2049_BSTS_DEFAULT \ 335 (AW_PID_2049_BSTS_DEFAULT_VALUE << AW_PID_2049_BSTS_START_BIT) 336 337 /* SWS bit 8 (SYSST 0x01) */ 338 #define AW_PID_2049_SWS_START_BIT (8) 339 #define AW_PID_2049_SWS_BITS_LEN (1) 340 #define AW_PID_2049_SWS_MASK \ 341 (~(((1<<AW_PID_2049_SWS_BITS_LEN)-1) << AW_PID_2049_SWS_START_BIT)) 342 343 #define AW_PID_2049_SWS_NOT_SWITCHING (0) 344 #define AW_PID_2049_SWS_NOT_SWITCHING_VALUE \ 345 (AW_PID_2049_SWS_NOT_SWITCHING << AW_PID_2049_SWS_START_BIT) 346 347 #define AW_PID_2049_SWS_SWITCHING (1) 348 #define AW_PID_2049_SWS_SWITCHING_VALUE \ 349 (AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT) 350 351 #define AW_PID_2049_SWS_DEFAULT_VALUE (0) 352 #define AW_PID_2049_SWS_DEFAULT \ 353 (AW_PID_2049_SWS_DEFAULT_VALUE << AW_PID_2049_SWS_START_BIT) 354 355 /* CLIPS bit 7 (SYSST 0x01) */ 356 #define AW_PID_2049_CLIPS_START_BIT (7) 357 #define AW_PID_2049_CLIPS_BITS_LEN (1) 358 #define AW_PID_2049_CLIPS_MASK \ 359 (~(((1<<AW_PID_2049_CLIPS_BITS_LEN)-1) << AW_PID_2049_CLIPS_START_BIT)) 360 361 #define AW_PID_2049_CLIPS_NOT_CLIPPING (0) 362 #define AW_PID_2049_CLIPS_NOT_CLIPPING_VALUE \ 363 (AW_PID_2049_CLIPS_NOT_CLIPPING << AW_PID_2049_CLIPS_START_BIT) 364 365 #define AW_PID_2049_CLIPS_CLIPPING (1) 366 #define AW_PID_2049_CLIPS_CLIPPING_VALUE \ 367 (AW_PID_2049_CLIPS_CLIPPING << AW_PID_2049_CLIPS_START_BIT) 368 369 #define AW_PID_2049_CLIPS_DEFAULT_VALUE (0) 370 #define AW_PID_2049_CLIPS_DEFAULT \ 371 (AW_PID_2049_CLIPS_DEFAULT_VALUE << AW_PID_2049_CLIPS_START_BIT) 372 373 /* WDS bit 6 (SYSST 0x01) */ 374 #define AW_PID_2049_WDS_START_BIT (6) 375 #define AW_PID_2049_WDS_BITS_LEN (1) 376 #define AW_PID_2049_WDS_MASK \ 377 (~(((1<<AW_PID_2049_WDS_BITS_LEN)-1) << AW_PID_2049_WDS_START_BIT)) 378 379 #define AW_PID_2049_WDS_NORMAL (0) 380 #define AW_PID_2049_WDS_NORMAL_VALUE \ 381 (AW_PID_2049_WDS_NORMAL << AW_PID_2049_WDS_START_BIT) 382 383 #define AW_PID_2049_WDS_ABNORMAL (1) 384 #define AW_PID_2049_WDS_ABNORMAL_VALUE \ 385 (AW_PID_2049_WDS_ABNORMAL << AW_PID_2049_WDS_START_BIT) 386 387 #define AW_PID_2049_WDS_DEFAULT_VALUE (0) 388 #define AW_PID_2049_WDS_DEFAULT \ 389 (AW_PID_2049_WDS_DEFAULT_VALUE << AW_PID_2049_WDS_START_BIT) 390 391 /* NOCLKS bit 5 (SYSST 0x01) */ 392 #define AW_PID_2049_NOCLKS_START_BIT (5) 393 #define AW_PID_2049_NOCLKS_BITS_LEN (1) 394 #define AW_PID_2049_NOCLKS_MASK \ 395 (~(((1<<AW_PID_2049_NOCLKS_BITS_LEN)-1) << AW_PID_2049_NOCLKS_START_BIT)) 396 397 #define AW_PID_2049_NOCLKS_CLOCK_OK (0) 398 #define AW_PID_2049_NOCLKS_CLOCK_OK_VALUE \ 399 (AW_PID_2049_NOCLKS_CLOCK_OK << AW_PID_2049_NOCLKS_START_BIT) 400 401 #define AW_PID_2049_NOCLKS_NO_CLOCK (1) 402 #define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE \ 403 (AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT) 404 405 #define AW_PID_2049_NOCLKS_DEFAULT_VALUE (0) 406 #define AW_PID_2049_NOCLKS_DEFAULT \ 407 (AW_PID_2049_NOCLKS_DEFAULT_VALUE << AW_PID_2049_NOCLKS_START_BIT) 408 409 /* CLKS bit 4 (SYSST 0x01) */ 410 #define AW_PID_2049_CLKS_START_BIT (4) 411 #define AW_PID_2049_CLKS_BITS_LEN (1) 412 #define AW_PID_2049_CLKS_MASK \ 413 (~(((1<<AW_PID_2049_CLKS_BITS_LEN)-1) << AW_PID_2049_CLKS_START_BIT)) 414 415 #define AW_PID_2049_CLKS_NOT_STABLE (0) 416 #define AW_PID_2049_CLKS_NOT_STABLE_VALUE \ 417 (AW_PID_2049_CLKS_NOT_STABLE << AW_PID_2049_CLKS_START_BIT) 418 419 #define AW_PID_2049_CLKS_STABLE (1) 420 #define AW_PID_2049_CLKS_STABLE_VALUE \ 421 (AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT) 422 423 #define AW_PID_2049_CLKS_DEFAULT_VALUE (0) 424 #define AW_PID_2049_CLKS_DEFAULT \ 425 (AW_PID_2049_CLKS_DEFAULT_VALUE << AW_PID_2049_CLKS_START_BIT) 426 427 /* OCDS bit 3 (SYSST 0x01) */ 428 #define AW_PID_2049_OCDS_START_BIT (3) 429 #define AW_PID_2049_OCDS_BITS_LEN (1) 430 #define AW_PID_2049_OCDS_MASK \ 431 (~(((1<<AW_PID_2049_OCDS_BITS_LEN)-1) << AW_PID_2049_OCDS_START_BIT)) 432 433 #define AW_PID_2049_OCDS_NORAML (0) 434 #define AW_PID_2049_OCDS_NORAML_VALUE \ 435 (AW_PID_2049_OCDS_NORAML << AW_PID_2049_OCDS_START_BIT) 436 437 #define AW_PID_2049_OCDS_OC (1) 438 #define AW_PID_2049_OCDS_OC_VALUE \ 439 (AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT) 440 441 #define AW_PID_2049_OCDS_DEFAULT_VALUE (0) 442 #define AW_PID_2049_OCDS_DEFAULT \ 443 (AW_PID_2049_OCDS_DEFAULT_VALUE << AW_PID_2049_OCDS_START_BIT) 444 445 /* CLIP_PRES bit 2 (SYSST 0x01) */ 446 #define AW_PID_2049_CLIP_PRES_START_BIT (2) 447 #define AW_PID_2049_CLIP_PRES_BITS_LEN (1) 448 #define AW_PID_2049_CLIP_PRES_MASK \ 449 (~(((1<<AW_PID_2049_CLIP_PRES_BITS_LEN)-1) << AW_PID_2049_CLIP_PRES_START_BIT)) 450 451 #define AW_PID_2049_CLIP_PRES_NOT_CLIPPING (0) 452 #define AW_PID_2049_CLIP_PRES_NOT_CLIPPING_VALUE \ 453 (AW_PID_2049_CLIP_PRES_NOT_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) 454 455 #define AW_PID_2049_CLIP_PRES_CLIPPING (1) 456 #define AW_PID_2049_CLIP_PRES_CLIPPING_VALUE \ 457 (AW_PID_2049_CLIP_PRES_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) 458 459 #define AW_PID_2049_CLIP_PRES_DEFAULT_VALUE (0) 460 #define AW_PID_2049_CLIP_PRES_DEFAULT \ 461 (AW_PID_2049_CLIP_PRES_DEFAULT_VALUE << AW_PID_2049_CLIP_PRES_START_BIT) 462 463 /* OTHS bit 1 (SYSST 0x01) */ 464 #define AW_PID_2049_OTHS_START_BIT (1) 465 #define AW_PID_2049_OTHS_BITS_LEN (1) 466 #define AW_PID_2049_OTHS_MASK \ 467 (~(((1<<AW_PID_2049_OTHS_BITS_LEN)-1) << AW_PID_2049_OTHS_START_BIT)) 468 469 #define AW_PID_2049_OTHS_NORMAL (0) 470 #define AW_PID_2049_OTHS_NORMAL_VALUE \ 471 (AW_PID_2049_OTHS_NORMAL << AW_PID_2049_OTHS_START_BIT) 472 473 #define AW_PID_2049_OTHS_OT (1) 474 #define AW_PID_2049_OTHS_OT_VALUE \ 475 (AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT) 476 477 #define AW_PID_2049_OTHS_DEFAULT_VALUE (0) 478 #define AW_PID_2049_OTHS_DEFAULT \ 479 (AW_PID_2049_OTHS_DEFAULT_VALUE << AW_PID_2049_OTHS_START_BIT) 480 481 /* PLLS bit 0 (SYSST 0x01) */ 482 #define AW_PID_2049_PLLS_START_BIT (0) 483 #define AW_PID_2049_PLLS_BITS_LEN (1) 484 #define AW_PID_2049_PLLS_MASK \ 485 (~(((1<<AW_PID_2049_PLLS_BITS_LEN)-1) << AW_PID_2049_PLLS_START_BIT)) 486 487 #define AW_PID_2049_PLLS_UNLOCKED (0) 488 #define AW_PID_2049_PLLS_UNLOCKED_VALUE \ 489 (AW_PID_2049_PLLS_UNLOCKED << AW_PID_2049_PLLS_START_BIT) 490 491 #define AW_PID_2049_PLLS_LOCKED (1) 492 #define AW_PID_2049_PLLS_LOCKED_VALUE \ 493 (AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT) 494 495 #define AW_PID_2049_PLLS_DEFAULT_VALUE (0) 496 #define AW_PID_2049_PLLS_DEFAULT \ 497 (AW_PID_2049_PLLS_DEFAULT_VALUE << AW_PID_2049_PLLS_START_BIT) 498 499 500 501 #define AW_PID_2049_BIT_PLL_CHECK \ 502 (AW_PID_2049_CLKS_STABLE_VALUE | \ 503 AW_PID_2049_PLLS_LOCKED_VALUE) 504 505 506 #define AW_PID_2049_BIT_SYSST_CHECK_MASK \ 507 (~(AW_PID_2049_UVLS_NORMAL_VALUE | \ 508 AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \ 509 AW_PID_2049_BSTS_FINISHED_VALUE | \ 510 AW_PID_2049_SWS_SWITCHING_VALUE | \ 511 AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \ 512 AW_PID_2049_CLKS_STABLE_VALUE | \ 513 AW_PID_2049_OCDS_OC_VALUE | \ 514 AW_PID_2049_OTHS_OT_VALUE | \ 515 AW_PID_2049_PLLS_LOCKED_VALUE)) 516 517 #define AW_PID_2049_BIT_SYSST_CHECK \ 518 (AW_PID_2049_BSTS_FINISHED_VALUE | \ 519 AW_PID_2049_SWS_SWITCHING_VALUE | \ 520 AW_PID_2049_CLKS_STABLE_VALUE | \ 521 AW_PID_2049_PLLS_LOCKED_VALUE) 522 523 /* default value of SYSST (0x01) */ 524 /* #define AW_PID_2049_SYSST_DEFAULT (0x0000) */ 525 526 /* SYSINT (0x02) detail */ 527 /* OVP2I bit 15 (SYSINT 0x02) */ 528 #define AW_PID_2049_OVP2I_START_BIT (15) 529 #define AW_PID_2049_OVP2I_BITS_LEN (1) 530 #define AW_PID_2049_OVP2I_MASK \ 531 (~(((1<<AW_PID_2049_OVP2I_BITS_LEN)-1) << AW_PID_2049_OVP2I_START_BIT)) 532 533 #define AW_PID_2049_OVP2I_DEFAULT_VALUE (0) 534 #define AW_PID_2049_OVP2I_DEFAULT \ 535 (AW_PID_2049_OVP2I_DEFAULT_VALUE << AW_PID_2049_OVP2I_START_BIT) 536 537 /* UVLI bit 14 (SYSINT 0x02) */ 538 #define AW_PID_2049_UVLI_START_BIT (14) 539 #define AW_PID_2049_UVLI_BITS_LEN (1) 540 #define AW_PID_2049_UVLI_MASK \ 541 (~(((1<<AW_PID_2049_UVLI_BITS_LEN)-1) << AW_PID_2049_UVLI_START_BIT)) 542 543 #define AW_PID_2049_UVLI_DEFAULT_VALUE (0) 544 #define AW_PID_2049_UVLI_DEFAULT \ 545 (AW_PID_2049_UVLI_DEFAULT_VALUE << AW_PID_2049_UVLI_START_BIT) 546 547 /* ADPI bit 13 (SYSINT 0x02) */ 548 #define AW_PID_2049_ADPI_START_BIT (13) 549 #define AW_PID_2049_ADPI_BITS_LEN (1) 550 #define AW_PID_2049_ADPI_MASK \ 551 (~(((1<<AW_PID_2049_ADPI_BITS_LEN)-1) << AW_PID_2049_ADPI_START_BIT)) 552 553 #define AW_PID_2049_ADPI_DEFAULT_VALUE (0) 554 #define AW_PID_2049_ADPI_DEFAULT \ 555 (AW_PID_2049_ADPI_DEFAULT_VALUE << AW_PID_2049_ADPI_START_BIT) 556 557 /* DSPI bit 12 (SYSINT 0x02) */ 558 #define AW_PID_2049_DSPI_START_BIT (12) 559 #define AW_PID_2049_DSPI_BITS_LEN (1) 560 #define AW_PID_2049_DSPI_MASK \ 561 (~(((1<<AW_PID_2049_DSPI_BITS_LEN)-1) << AW_PID_2049_DSPI_START_BIT)) 562 563 #define AW_PID_2049_DSPI_DEFAULT_VALUE (0) 564 #define AW_PID_2049_DSPI_DEFAULT \ 565 (AW_PID_2049_DSPI_DEFAULT_VALUE << AW_PID_2049_DSPI_START_BIT) 566 567 /* BSTOCI bit 11 (SYSINT 0x02) */ 568 #define AW_PID_2049_BSTOCI_START_BIT (11) 569 #define AW_PID_2049_BSTOCI_BITS_LEN (1) 570 #define AW_PID_2049_BSTOCI_MASK \ 571 (~(((1<<AW_PID_2049_BSTOCI_BITS_LEN)-1) << AW_PID_2049_BSTOCI_START_BIT)) 572 573 #define AW_PID_2049_BSTOCI_DEFAULT_VALUE (0) 574 #define AW_PID_2049_BSTOCI_DEFAULT \ 575 (AW_PID_2049_BSTOCI_DEFAULT_VALUE << AW_PID_2049_BSTOCI_START_BIT) 576 577 /* OVPI bit 10 (SYSINT 0x02) */ 578 #define AW_PID_2049_OVPI_START_BIT (10) 579 #define AW_PID_2049_OVPI_BITS_LEN (1) 580 #define AW_PID_2049_OVPI_MASK \ 581 (~(((1<<AW_PID_2049_OVPI_BITS_LEN)-1) << AW_PID_2049_OVPI_START_BIT)) 582 583 #define AW_PID_2049_OVPI_DEFAULT_VALUE (0) 584 #define AW_PID_2049_OVPI_DEFAULT \ 585 (AW_PID_2049_OVPI_DEFAULT_VALUE << AW_PID_2049_OVPI_START_BIT) 586 587 /* BSTI bit 9 (SYSINT 0x02) */ 588 #define AW_PID_2049_BSTI_START_BIT (9) 589 #define AW_PID_2049_BSTI_BITS_LEN (1) 590 #define AW_PID_2049_BSTI_MASK \ 591 (~(((1<<AW_PID_2049_BSTI_BITS_LEN)-1) << AW_PID_2049_BSTI_START_BIT)) 592 593 #define AW_PID_2049_BSTI_DEFAULT_VALUE (0) 594 #define AW_PID_2049_BSTI_DEFAULT \ 595 (AW_PID_2049_BSTI_DEFAULT_VALUE << AW_PID_2049_BSTI_START_BIT) 596 597 /* SWI bit 8 (SYSINT 0x02) */ 598 #define AW_PID_2049_SWI_START_BIT (8) 599 #define AW_PID_2049_SWI_BITS_LEN (1) 600 #define AW_PID_2049_SWI_MASK \ 601 (~(((1<<AW_PID_2049_SWI_BITS_LEN)-1) << AW_PID_2049_SWI_START_BIT)) 602 603 #define AW_PID_2049_SWI_DEFAULT_VALUE (0) 604 #define AW_PID_2049_SWI_DEFAULT \ 605 (AW_PID_2049_SWI_DEFAULT_VALUE << AW_PID_2049_SWI_START_BIT) 606 607 /* CLIPI bit 7 (SYSINT 0x02) */ 608 #define AW_PID_2049_CLIPI_START_BIT (7) 609 #define AW_PID_2049_CLIPI_BITS_LEN (1) 610 #define AW_PID_2049_CLIPI_MASK \ 611 (~(((1<<AW_PID_2049_CLIPI_BITS_LEN)-1) << AW_PID_2049_CLIPI_START_BIT)) 612 613 #define AW_PID_2049_CLIPI_DEFAULT_VALUE (0) 614 #define AW_PID_2049_CLIPI_DEFAULT \ 615 (AW_PID_2049_CLIPI_DEFAULT_VALUE << AW_PID_2049_CLIPI_START_BIT) 616 617 /* WDI bit 6 (SYSINT 0x02) */ 618 #define AW_PID_2049_WDI_START_BIT (6) 619 #define AW_PID_2049_WDI_BITS_LEN (1) 620 #define AW_PID_2049_WDI_MASK \ 621 (~(((1<<AW_PID_2049_WDI_BITS_LEN)-1) << AW_PID_2049_WDI_START_BIT)) 622 623 #define AW_PID_2049_WDI_DEFAULT_VALUE (0) 624 #define AW_PID_2049_WDI_INT_VALUE (1) 625 #define AW_PID_2049_WDI_DEFAULT \ 626 (AW_PID_2049_WDI_DEFAULT_VALUE << AW_PID_2049_WDI_START_BIT) 627 #define AW_PID_2049_WDI_INTERRUPT \ 628 (AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT) 629 630 /* NOCLKI bit 5 (SYSINT 0x02) */ 631 #define AW_PID_2049_NOCLKI_START_BIT (5) 632 #define AW_PID_2049_NOCLKI_BITS_LEN (1) 633 #define AW_PID_2049_NOCLKI_MASK \ 634 (~(((1<<AW_PID_2049_NOCLKI_BITS_LEN)-1) << AW_PID_2049_NOCLKI_START_BIT)) 635 636 #define AW_PID_2049_NOCLKI_DEFAULT_VALUE (0) 637 #define AW_PID_2049_NOCLKI_INT_VALUE (1) 638 #define AW_PID_2049_NOCLKI_DEFAULT \ 639 (AW_PID_2049_NOCLKI_DEFAULT_VALUE << AW_PID_2049_NOCLKI_START_BIT) 640 #define AW_PID_2049_NOCLKI_INTERRUPT \ 641 (AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT) 642 643 /* CLKI bit 4 (SYSINT 0x02) */ 644 #define AW_PID_2049_CLKI_START_BIT (4) 645 #define AW_PID_2049_CLKI_BITS_LEN (1) 646 #define AW_PID_2049_CLKI_MASK \ 647 (~(((1<<AW_PID_2049_CLKI_BITS_LEN)-1) << AW_PID_2049_CLKI_START_BIT)) 648 649 #define AW_PID_2049_CLKI_DEFAULT_VALUE (0) 650 #define AW_PID_2049_CLKI_INT_VALUE (1) 651 #define AW_PID_2049_CLKI_DEFAULT \ 652 (AW_PID_2049_CLKI_DEFAULT_VALUE << AW_PID_2049_CLKI_START_BIT) 653 #define AW_PID_2049_CLKI_INTERRUPT \ 654 (AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT) 655 656 /* OCDI bit 3 (SYSINT 0x02) */ 657 #define AW_PID_2049_OCDI_START_BIT (3) 658 #define AW_PID_2049_OCDI_BITS_LEN (1) 659 #define AW_PID_2049_OCDI_MASK \ 660 (~(((1<<AW_PID_2049_OCDI_BITS_LEN)-1) << AW_PID_2049_OCDI_START_BIT)) 661 662 #define AW_PID_2049_OCDI_DEFAULT_VALUE (0) 663 #define AW_PID_2049_OCDI_DEFAULT \ 664 (AW_PID_2049_OCDI_DEFAULT_VALUE << AW_PID_2049_OCDI_START_BIT) 665 666 /* CLIP_PREI bit 2 (SYSINT 0x02) */ 667 #define AW_PID_2049_CLIP_PREI_START_BIT (2) 668 #define AW_PID_2049_CLIP_PREI_BITS_LEN (1) 669 #define AW_PID_2049_CLIP_PREI_MASK \ 670 (~(((1<<AW_PID_2049_CLIP_PREI_BITS_LEN)-1) << AW_PID_2049_CLIP_PREI_START_BIT)) 671 672 #define AW_PID_2049_CLIP_PREI_DEFAULT_VALUE (0) 673 #define AW_PID_2049_CLIP_PREI_DEFAULT \ 674 (AW_PID_2049_CLIP_PREI_DEFAULT_VALUE << AW_PID_2049_CLIP_PREI_START_BIT) 675 676 /* OTHI bit 1 (SYSINT 0x02) */ 677 #define AW_PID_2049_OTHI_START_BIT (1) 678 #define AW_PID_2049_OTHI_BITS_LEN (1) 679 #define AW_PID_2049_OTHI_MASK \ 680 (~(((1<<AW_PID_2049_OTHI_BITS_LEN)-1) << AW_PID_2049_OTHI_START_BIT)) 681 682 #define AW_PID_2049_OTHI_DEFAULT_VALUE (0) 683 #define AW_PID_2049_OTHI_DEFAULT \ 684 (AW_PID_2049_OTHI_DEFAULT_VALUE << AW_PID_2049_OTHI_START_BIT) 685 686 /* PLLI bit 0 (SYSINT 0x02) */ 687 #define AW_PID_2049_PLLI_START_BIT (0) 688 #define AW_PID_2049_PLLI_BITS_LEN (1) 689 #define AW_PID_2049_PLLI_MASK \ 690 (~(((1<<AW_PID_2049_PLLI_BITS_LEN)-1) << AW_PID_2049_PLLI_START_BIT)) 691 692 #define AW_PID_2049_PLLI_DEFAULT_VALUE (0) 693 #define AW_PID_2049_PLLI_INT_VALUE (1) 694 #define AW_PID_2049_PLLI_DEFAULT \ 695 (AW_PID_2049_PLLI_DEFAULT_VALUE << AW_PID_2049_PLLI_START_BIT) 696 #define AW_PID_2049_PLLI_INTERRUPT \ 697 (AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT) 698 699 /* default value of SYSINT (0x02) */ 700 /* #define AW_PID_2049_SYSINT_DEFAULT (0x0000) */ 701 702 #define AW_PID_2049_BIT_SYSINT_CHECK \ 703 (AW_PID_2049_WDI_INTERRUPT | \ 704 AW_PID_2049_CLKI_INTERRUPT | \ 705 AW_PID_2049_NOCLKI_INTERRUPT | \ 706 AW_PID_2049_PLLI_INTERRUPT) 707 708 /* SYSINTM (0x03) detail */ 709 /* OVP2M bit 15 (SYSINTM 0x03) */ 710 #define AW_PID_2049_OVP2M_START_BIT (15) 711 #define AW_PID_2049_OVP2M_BITS_LEN (1) 712 #define AW_PID_2049_OVP2M_MASK \ 713 (~(((1<<AW_PID_2049_OVP2M_BITS_LEN)-1) << AW_PID_2049_OVP2M_START_BIT)) 714 715 #define AW_PID_2049_OVP2M_DEFAULT_VALUE (1) 716 #define AW_PID_2049_OVP2M_DEFAULT \ 717 (AW_PID_2049_OVP2M_DEFAULT_VALUE << AW_PID_2049_OVP2M_START_BIT) 718 719 /* UVLM bit 14 (SYSINTM 0x03) */ 720 #define AW_PID_2049_UVLM_START_BIT (14) 721 #define AW_PID_2049_UVLM_BITS_LEN (1) 722 #define AW_PID_2049_UVLM_MASK \ 723 (~(((1<<AW_PID_2049_UVLM_BITS_LEN)-1) << AW_PID_2049_UVLM_START_BIT)) 724 725 #define AW_PID_2049_UVLM_DEFAULT_VALUE (1) 726 #define AW_PID_2049_UVLM_DEFAULT \ 727 (AW_PID_2049_UVLM_DEFAULT_VALUE << AW_PID_2049_UVLM_START_BIT) 728 729 /* ADPM bit 13 (SYSINTM 0x03) */ 730 #define AW_PID_2049_ADPM_START_BIT (13) 731 #define AW_PID_2049_ADPM_BITS_LEN (1) 732 #define AW_PID_2049_ADPM_MASK \ 733 (~(((1<<AW_PID_2049_ADPM_BITS_LEN)-1) << AW_PID_2049_ADPM_START_BIT)) 734 735 #define AW_PID_2049_ADPM_DEFAULT_VALUE (1) 736 #define AW_PID_2049_ADPM_DEFAULT \ 737 (AW_PID_2049_ADPM_DEFAULT_VALUE << AW_PID_2049_ADPM_START_BIT) 738 739 /* DSPM bit 12 (SYSINTM 0x03) */ 740 #define AW_PID_2049_DSPM_START_BIT (12) 741 #define AW_PID_2049_DSPM_BITS_LEN (1) 742 #define AW_PID_2049_DSPM_MASK \ 743 (~(((1<<AW_PID_2049_DSPM_BITS_LEN)-1) << AW_PID_2049_DSPM_START_BIT)) 744 745 #define AW_PID_2049_DSPM_DEFAULT_VALUE (1) 746 #define AW_PID_2049_DSPM_DEFAULT \ 747 (AW_PID_2049_DSPM_DEFAULT_VALUE << AW_PID_2049_DSPM_START_BIT) 748 749 /* BSTOCM bit 11 (SYSINTM 0x03) */ 750 #define AW_PID_2049_BSTOCM_START_BIT (11) 751 #define AW_PID_2049_BSTOCM_BITS_LEN (1) 752 #define AW_PID_2049_BSTOCM_MASK \ 753 (~(((1<<AW_PID_2049_BSTOCM_BITS_LEN)-1) << AW_PID_2049_BSTOCM_START_BIT)) 754 755 #define AW_PID_2049_BSTOCM_DEFAULT_VALUE (1) 756 #define AW_PID_2049_BSTOCM_DEFAULT \ 757 (AW_PID_2049_BSTOCM_DEFAULT_VALUE << AW_PID_2049_BSTOCM_START_BIT) 758 759 /* OVPM bit 10 (SYSINTM 0x03) */ 760 #define AW_PID_2049_OVPM_START_BIT (10) 761 #define AW_PID_2049_OVPM_BITS_LEN (1) 762 #define AW_PID_2049_OVPM_MASK \ 763 (~(((1<<AW_PID_2049_OVPM_BITS_LEN)-1) << AW_PID_2049_OVPM_START_BIT)) 764 765 #define AW_PID_2049_OVPM_DEFAULT_VALUE (1) 766 #define AW_PID_2049_OVPM_DEFAULT \ 767 (AW_PID_2049_OVPM_DEFAULT_VALUE << AW_PID_2049_OVPM_START_BIT) 768 769 /* BSTM bit 9 (SYSINTM 0x03) */ 770 #define AW_PID_2049_BSTM_START_BIT (9) 771 #define AW_PID_2049_BSTM_BITS_LEN (1) 772 #define AW_PID_2049_BSTM_MASK \ 773 (~(((1<<AW_PID_2049_BSTM_BITS_LEN)-1) << AW_PID_2049_BSTM_START_BIT)) 774 775 #define AW_PID_2049_BSTM_DEFAULT_VALUE (1) 776 #define AW_PID_2049_BSTM_DEFAULT \ 777 (AW_PID_2049_BSTM_DEFAULT_VALUE << AW_PID_2049_BSTM_START_BIT) 778 779 /* SWM bit 8 (SYSINTM 0x03) */ 780 #define AW_PID_2049_SWM_START_BIT (8) 781 #define AW_PID_2049_SWM_BITS_LEN (1) 782 #define AW_PID_2049_SWM_MASK \ 783 (~(((1<<AW_PID_2049_SWM_BITS_LEN)-1) << AW_PID_2049_SWM_START_BIT)) 784 785 #define AW_PID_2049_SWM_DEFAULT_VALUE (1) 786 #define AW_PID_2049_SWM_DEFAULT \ 787 (AW_PID_2049_SWM_DEFAULT_VALUE << AW_PID_2049_SWM_START_BIT) 788 789 /* CLIPM bit 7 (SYSINTM 0x03) */ 790 #define AW_PID_2049_CLIPM_START_BIT (7) 791 #define AW_PID_2049_CLIPM_BITS_LEN (1) 792 #define AW_PID_2049_CLIPM_MASK \ 793 (~(((1<<AW_PID_2049_CLIPM_BITS_LEN)-1) << AW_PID_2049_CLIPM_START_BIT)) 794 795 #define AW_PID_2049_CLIPM_DEFAULT_VALUE (1) 796 #define AW_PID_2049_CLIPM_DEFAULT \ 797 (AW_PID_2049_CLIPM_DEFAULT_VALUE << AW_PID_2049_CLIPM_START_BIT) 798 799 /* WDM bit 6 (SYSINTM 0x03) */ 800 #define AW_PID_2049_WDM_START_BIT (6) 801 #define AW_PID_2049_WDM_BITS_LEN (1) 802 #define AW_PID_2049_WDM_MASK \ 803 (~(((1<<AW_PID_2049_WDM_BITS_LEN)-1) << AW_PID_2049_WDM_START_BIT)) 804 805 #define AW_PID_2049_WDM_DEFAULT_VALUE (1) 806 #define AW_PID_2049_WDM_DEFAULT \ 807 (AW_PID_2049_WDM_DEFAULT_VALUE << AW_PID_2049_WDM_START_BIT) 808 809 /* NOCLKM bit 5 (SYSINTM 0x03) */ 810 #define AW_PID_2049_NOCLKM_START_BIT (5) 811 #define AW_PID_2049_NOCLKM_BITS_LEN (1) 812 #define AW_PID_2049_NOCLKM_MASK \ 813 (~(((1<<AW_PID_2049_NOCLKM_BITS_LEN)-1) << AW_PID_2049_NOCLKM_START_BIT)) 814 815 #define AW_PID_2049_NOCLKM_DEFAULT_VALUE (1) 816 #define AW_PID_2049_NOCLKM_DEFAULT \ 817 (AW_PID_2049_NOCLKM_DEFAULT_VALUE << AW_PID_2049_NOCLKM_START_BIT) 818 819 /* CLKM bit 4 (SYSINTM 0x03) */ 820 #define AW_PID_2049_CLKM_START_BIT (4) 821 #define AW_PID_2049_CLKM_BITS_LEN (1) 822 #define AW_PID_2049_CLKM_MASK \ 823 (~(((1<<AW_PID_2049_CLKM_BITS_LEN)-1) << AW_PID_2049_CLKM_START_BIT)) 824 825 #define AW_PID_2049_CLKM_DEFAULT_VALUE (1) 826 #define AW_PID_2049_CLKM_DEFAULT \ 827 (AW_PID_2049_CLKM_DEFAULT_VALUE << AW_PID_2049_CLKM_START_BIT) 828 829 /* OCDM bit 3 (SYSINTM 0x03) */ 830 #define AW_PID_2049_OCDM_START_BIT (3) 831 #define AW_PID_2049_OCDM_BITS_LEN (1) 832 #define AW_PID_2049_OCDM_MASK \ 833 (~(((1<<AW_PID_2049_OCDM_BITS_LEN)-1) << AW_PID_2049_OCDM_START_BIT)) 834 835 #define AW_PID_2049_OCDM_DEFAULT_VALUE (1) 836 #define AW_PID_2049_OCDM_DEFAULT \ 837 (AW_PID_2049_OCDM_DEFAULT_VALUE << AW_PID_2049_OCDM_START_BIT) 838 839 /* CLIP_PREM bit 2 (SYSINTM 0x03) */ 840 #define AW_PID_2049_CLIP_PREM_START_BIT (2) 841 #define AW_PID_2049_CLIP_PREM_BITS_LEN (1) 842 #define AW_PID_2049_CLIP_PREM_MASK \ 843 (~(((1<<AW_PID_2049_CLIP_PREM_BITS_LEN)-1) << AW_PID_2049_CLIP_PREM_START_BIT)) 844 845 #define AW_PID_2049_CLIP_PREM_DEFAULT_VALUE (1) 846 #define AW_PID_2049_CLIP_PREM_DEFAULT \ 847 (AW_PID_2049_CLIP_PREM_DEFAULT_VALUE << AW_PID_2049_CLIP_PREM_START_BIT) 848 849 /* OTHM bit 1 (SYSINTM 0x03) */ 850 #define AW_PID_2049_OTHM_START_BIT (1) 851 #define AW_PID_2049_OTHM_BITS_LEN (1) 852 #define AW_PID_2049_OTHM_MASK \ 853 (~(((1<<AW_PID_2049_OTHM_BITS_LEN)-1) << AW_PID_2049_OTHM_START_BIT)) 854 855 #define AW_PID_2049_OTHM_DEFAULT_VALUE (1) 856 #define AW_PID_2049_OTHM_DEFAULT \ 857 (AW_PID_2049_OTHM_DEFAULT_VALUE << AW_PID_2049_OTHM_START_BIT) 858 859 /* PLLM bit 0 (SYSINTM 0x03) */ 860 #define AW_PID_2049_PLLM_START_BIT (0) 861 #define AW_PID_2049_PLLM_BITS_LEN (1) 862 #define AW_PID_2049_PLLM_MASK \ 863 (~(((1<<AW_PID_2049_PLLM_BITS_LEN)-1) << AW_PID_2049_PLLM_START_BIT)) 864 865 #define AW_PID_2049_PLLM_DEFAULT_VALUE (1) 866 #define AW_PID_2049_PLLM_DEFAULT \ 867 (AW_PID_2049_PLLM_DEFAULT_VALUE << AW_PID_2049_PLLM_START_BIT) 868 869 /* default value of SYSINTM (0x03) */ 870 #define AW_PID_2049_SYSINTM_DEFAULT (0xFFFF) 871 872 /* SYSCTRL (0x04) detail */ 873 /* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */ 874 #define AW_PID_2049_SPK_GAIN_START_BIT (12) 875 #define AW_PID_2049_SPK_GAIN_BITS_LEN (3) 876 #define AW_PID_2049_SPK_GAIN_MASK \ 877 (~(((1<<AW_PID_2049_SPK_GAIN_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_START_BIT)) 878 879 #define AW_PID_2049_SPK_GAIN_4_AV (0) 880 #define AW_PID_2049_SPK_GAIN_4_AV_VALUE \ 881 (AW_PID_2049_SPK_GAIN_4_AV << AW_PID_2049_SPK_GAIN_START_BIT) 882 883 #define AW_PID_2049_SPK_GAIN_4P67_AV (1) 884 #define AW_PID_2049_SPK_GAIN_4P67_AV_VALUE \ 885 (AW_PID_2049_SPK_GAIN_4P67_AV << AW_PID_2049_SPK_GAIN_START_BIT) 886 887 #define AW_PID_2049_SPK_GAIN_6_AV (2) 888 #define AW_PID_2049_SPK_GAIN_6_AV_VALUE \ 889 (AW_PID_2049_SPK_GAIN_6_AV << AW_PID_2049_SPK_GAIN_START_BIT) 890 891 #define AW_PID_2049_SPK_GAIN_7_AV (3) 892 #define AW_PID_2049_SPK_GAIN_7_AV_VALUE \ 893 (AW_PID_2049_SPK_GAIN_7_AV << AW_PID_2049_SPK_GAIN_START_BIT) 894 895 #define AW_PID_2049_SPK_GAIN_12_AV (4) 896 #define AW_PID_2049_SPK_GAIN_12_AV_VALUE \ 897 (AW_PID_2049_SPK_GAIN_12_AV << AW_PID_2049_SPK_GAIN_START_BIT) 898 899 #define AW_PID_2049_SPK_GAIN_14_AV (5) 900 #define AW_PID_2049_SPK_GAIN_14_AV_VALUE \ 901 (AW_PID_2049_SPK_GAIN_14_AV << AW_PID_2049_SPK_GAIN_START_BIT) 902 903 #define AW_PID_2049_SPK_GAIN_DEFAULT_VALUE (0x5) 904 #define AW_PID_2049_SPK_GAIN_DEFAULT \ 905 (AW_PID_2049_SPK_GAIN_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_START_BIT) 906 907 /* RMSE bit 11 (SYSCTRL 0x04) */ 908 #define AW_PID_2049_RMSE_START_BIT (11) 909 #define AW_PID_2049_RMSE_BITS_LEN (1) 910 #define AW_PID_2049_RMSE_MASK \ 911 (~(((1<<AW_PID_2049_RMSE_BITS_LEN)-1) << AW_PID_2049_RMSE_START_BIT)) 912 913 #define AW_PID_2049_RMSE_PEAK_AGC (0) 914 #define AW_PID_2049_RMSE_PEAK_AGC_VALUE \ 915 (AW_PID_2049_RMSE_PEAK_AGC << AW_PID_2049_RMSE_START_BIT) 916 917 #define AW_PID_2049_RMSE_RMS_AGC (1) 918 #define AW_PID_2049_RMSE_RMS_AGC_VALUE \ 919 (AW_PID_2049_RMSE_RMS_AGC << AW_PID_2049_RMSE_START_BIT) 920 921 #define AW_PID_2049_RMSE_DEFAULT_VALUE (0) 922 #define AW_PID_2049_RMSE_DEFAULT \ 923 (AW_PID_2049_RMSE_DEFAULT_VALUE << AW_PID_2049_RMSE_START_BIT) 924 925 /* HAGCE bit 10 (SYSCTRL 0x04) */ 926 #define AW_PID_2049_HAGCE_START_BIT (10) 927 #define AW_PID_2049_HAGCE_BITS_LEN (1) 928 #define AW_PID_2049_HAGCE_MASK \ 929 (~(((1<<AW_PID_2049_HAGCE_BITS_LEN)-1) << AW_PID_2049_HAGCE_START_BIT)) 930 931 #define AW_PID_2049_HAGCE_DISABLE (0) 932 #define AW_PID_2049_HAGCE_DISABLE_VALUE \ 933 (AW_PID_2049_HAGCE_DISABLE << AW_PID_2049_HAGCE_START_BIT) 934 935 #define AW_PID_2049_HAGCE_ENABLE (1) 936 #define AW_PID_2049_HAGCE_ENABLE_VALUE \ 937 (AW_PID_2049_HAGCE_ENABLE << AW_PID_2049_HAGCE_START_BIT) 938 939 #define AW_PID_2049_HAGCE_DEFAULT_VALUE (0) 940 #define AW_PID_2049_HAGCE_DEFAULT \ 941 (AW_PID_2049_HAGCE_DEFAULT_VALUE << AW_PID_2049_HAGCE_START_BIT) 942 943 /* HDCCE bit 9 (SYSCTRL 0x04) */ 944 #define AW_PID_2049_HDCCE_START_BIT (9) 945 #define AW_PID_2049_HDCCE_BITS_LEN (1) 946 #define AW_PID_2049_HDCCE_MASK \ 947 (~(((1<<AW_PID_2049_HDCCE_BITS_LEN)-1) << AW_PID_2049_HDCCE_START_BIT)) 948 949 #define AW_PID_2049_HDCCE_DISABLE (0) 950 #define AW_PID_2049_HDCCE_DISABLE_VALUE \ 951 (AW_PID_2049_HDCCE_DISABLE << AW_PID_2049_HDCCE_START_BIT) 952 953 #define AW_PID_2049_HDCCE_ENABLE (1) 954 #define AW_PID_2049_HDCCE_ENABLE_VALUE \ 955 (AW_PID_2049_HDCCE_ENABLE << AW_PID_2049_HDCCE_START_BIT) 956 957 #define AW_PID_2049_HDCCE_DEFAULT_VALUE (1) 958 #define AW_PID_2049_HDCCE_DEFAULT \ 959 (AW_PID_2049_HDCCE_DEFAULT_VALUE << AW_PID_2049_HDCCE_START_BIT) 960 961 /* HMUTE bit 8 (SYSCTRL 0x04) */ 962 #define AW_PID_2049_HMUTE_START_BIT (8) 963 #define AW_PID_2049_HMUTE_BITS_LEN (1) 964 #define AW_PID_2049_HMUTE_MASK \ 965 (~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT)) 966 967 #define AW_PID_2049_HMUTE_DISABLE (0) 968 #define AW_PID_2049_HMUTE_DISABLE_VALUE \ 969 (AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT) 970 971 #define AW_PID_2049_HMUTE_ENABLE (1) 972 #define AW_PID_2049_HMUTE_ENABLE_VALUE \ 973 (AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT) 974 975 #define AW_PID_2049_HMUTE_DEFAULT_VALUE (1) 976 #define AW_PID_2049_HMUTE_DEFAULT \ 977 (AW_PID_2049_HMUTE_DEFAULT_VALUE << AW_PID_2049_HMUTE_START_BIT) 978 979 /* RCV_MODE bit 7 (SYSCTRL 0x04) */ 980 #define AW_PID_2049_RCV_MODE_START_BIT (7) 981 #define AW_PID_2049_RCV_MODE_BITS_LEN (1) 982 #define AW_PID_2049_RCV_MODE_MASK \ 983 (~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT)) 984 985 #define AW_PID_2049_RCV_MODE_SPEAKER (0) 986 #define AW_PID_2049_RCV_MODE_SPEAKER_VALUE \ 987 (AW_PID_2049_RCV_MODE_SPEAKER << AW_PID_2049_RCV_MODE_START_BIT) 988 989 #define AW_PID_2049_RCV_MODE_RECEIVER (1) 990 #define AW_PID_2049_RCV_MODE_RECEIVER_VALUE \ 991 (AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT) 992 993 #define AW_PID_2049_RCV_MODE_DEFAULT_VALUE (0) 994 #define AW_PID_2049_RCV_MODE_DEFAULT \ 995 (AW_PID_2049_RCV_MODE_DEFAULT_VALUE << AW_PID_2049_RCV_MODE_START_BIT) 996 997 /* I2SEN bit 6 (SYSCTRL 0x04) */ 998 #define AW_PID_2049_I2SEN_START_BIT (6) 999 #define AW_PID_2049_I2SEN_BITS_LEN (1) 1000 #define AW_PID_2049_I2SEN_MASK \ 1001 (~(((1<<AW_PID_2049_I2SEN_BITS_LEN)-1) << AW_PID_2049_I2SEN_START_BIT)) 1002 1003 #define AW_PID_2049_I2SEN_DISABLE (0) 1004 #define AW_PID_2049_I2SEN_DISABLE_VALUE \ 1005 (AW_PID_2049_I2SEN_DISABLE << AW_PID_2049_I2SEN_START_BIT) 1006 1007 #define AW_PID_2049_I2SEN_ENABLE (1) 1008 #define AW_PID_2049_I2SEN_ENABLE_VALUE \ 1009 (AW_PID_2049_I2SEN_ENABLE << AW_PID_2049_I2SEN_START_BIT) 1010 1011 #define AW_PID_2049_I2SEN_DEFAULT_VALUE (0) 1012 #define AW_PID_2049_I2SEN_DEFAULT \ 1013 (AW_PID_2049_I2SEN_DEFAULT_VALUE << AW_PID_2049_I2SEN_START_BIT) 1014 1015 /* WSINV bit 5 (SYSCTRL 0x04) */ 1016 #define AW_PID_2049_WSINV_START_BIT (5) 1017 #define AW_PID_2049_WSINV_BITS_LEN (1) 1018 #define AW_PID_2049_WSINV_MASK \ 1019 (~(((1<<AW_PID_2049_WSINV_BITS_LEN)-1) << AW_PID_2049_WSINV_START_BIT)) 1020 1021 #define AW_PID_2049_WSINV_NOT_SWITCH (0) 1022 #define AW_PID_2049_WSINV_NOT_SWITCH_VALUE \ 1023 (AW_PID_2049_WSINV_NOT_SWITCH << AW_PID_2049_WSINV_START_BIT) 1024 1025 #define AW_PID_2049_WSINV_SWITCH (1) 1026 #define AW_PID_2049_WSINV_SWITCH_VALUE \ 1027 (AW_PID_2049_WSINV_SWITCH << AW_PID_2049_WSINV_START_BIT) 1028 1029 #define AW_PID_2049_WSINV_DEFAULT_VALUE (0) 1030 #define AW_PID_2049_WSINV_DEFAULT \ 1031 (AW_PID_2049_WSINV_DEFAULT_VALUE << AW_PID_2049_WSINV_START_BIT) 1032 1033 /* BCKINV bit 4 (SYSCTRL 0x04) */ 1034 #define AW_PID_2049_BCKINV_START_BIT (4) 1035 #define AW_PID_2049_BCKINV_BITS_LEN (1) 1036 #define AW_PID_2049_BCKINV_MASK \ 1037 (~(((1<<AW_PID_2049_BCKINV_BITS_LEN)-1) << AW_PID_2049_BCKINV_START_BIT)) 1038 1039 #define AW_PID_2049_BCKINV_NOT_INVERT (0) 1040 #define AW_PID_2049_BCKINV_NOT_INVERT_VALUE \ 1041 (AW_PID_2049_BCKINV_NOT_INVERT << AW_PID_2049_BCKINV_START_BIT) 1042 1043 #define AW_PID_2049_BCKINV_INVERTED (1) 1044 #define AW_PID_2049_BCKINV_INVERTED_VALUE \ 1045 (AW_PID_2049_BCKINV_INVERTED << AW_PID_2049_BCKINV_START_BIT) 1046 1047 #define AW_PID_2049_BCKINV_DEFAULT_VALUE (0) 1048 #define AW_PID_2049_BCKINV_DEFAULT \ 1049 (AW_PID_2049_BCKINV_DEFAULT_VALUE << AW_PID_2049_BCKINV_START_BIT) 1050 1051 /* IPLL bit 3 (SYSCTRL 0x04) */ 1052 #define AW_PID_2049_IPLL_START_BIT (3) 1053 #define AW_PID_2049_IPLL_BITS_LEN (1) 1054 #define AW_PID_2049_IPLL_MASK \ 1055 (~(((1<<AW_PID_2049_IPLL_BITS_LEN)-1) << AW_PID_2049_IPLL_START_BIT)) 1056 1057 #define AW_PID_2049_IPLL_BCK (0) 1058 #define AW_PID_2049_IPLL_BCK_VALUE \ 1059 (AW_PID_2049_IPLL_BCK << AW_PID_2049_IPLL_START_BIT) 1060 1061 #define AW_PID_2049_IPLL_WCK (1) 1062 #define AW_PID_2049_IPLL_WCK_VALUE \ 1063 (AW_PID_2049_IPLL_WCK << AW_PID_2049_IPLL_START_BIT) 1064 1065 #define AW_PID_2049_IPLL_DEFAULT_VALUE (0) 1066 #define AW_PID_2049_IPLL_DEFAULT \ 1067 (AW_PID_2049_IPLL_DEFAULT_VALUE << AW_PID_2049_IPLL_START_BIT) 1068 1069 /* DSPBY bit 2 (SYSCTRL 0x04) */ 1070 #define AW_PID_2049_DSPBY_START_BIT (2) 1071 #define AW_PID_2049_DSPBY_BITS_LEN (1) 1072 #define AW_PID_2049_DSPBY_MASK \ 1073 (~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT)) 1074 1075 #define AW_PID_2049_DSPBY_WORKING (0) 1076 #define AW_PID_2049_DSPBY_WORKING_VALUE \ 1077 (AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT) 1078 1079 #define AW_PID_2049_DSPBY_BYPASS (1) 1080 #define AW_PID_2049_DSPBY_BYPASS_VALUE \ 1081 (AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT) 1082 1083 #define AW_PID_2049_DSPBY_DEFAULT_VALUE (1) 1084 #define AW_PID_2049_DSPBY_DEFAULT \ 1085 (AW_PID_2049_DSPBY_DEFAULT_VALUE << AW_PID_2049_DSPBY_START_BIT) 1086 1087 /* AMPPD bit 1 (SYSCTRL 0x04) */ 1088 #define AW_PID_2049_AMPPD_START_BIT (1) 1089 #define AW_PID_2049_AMPPD_BITS_LEN (1) 1090 #define AW_PID_2049_AMPPD_MASK \ 1091 (~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT)) 1092 1093 #define AW_PID_2049_AMPPD_WORKING (0) 1094 #define AW_PID_2049_AMPPD_WORKING_VALUE \ 1095 (AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT) 1096 1097 #define AW_PID_2049_AMPPD_POWER_DOWN (1) 1098 #define AW_PID_2049_AMPPD_POWER_DOWN_VALUE \ 1099 (AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT) 1100 1101 #define AW_PID_2049_AMPPD_DEFAULT_VALUE (1) 1102 #define AW_PID_2049_AMPPD_DEFAULT \ 1103 (AW_PID_2049_AMPPD_DEFAULT_VALUE << AW_PID_2049_AMPPD_START_BIT) 1104 1105 /* PWDN bit 0 (SYSCTRL 0x04) */ 1106 #define AW_PID_2049_PWDN_START_BIT (0) 1107 #define AW_PID_2049_PWDN_BITS_LEN (1) 1108 #define AW_PID_2049_PWDN_MASK \ 1109 (~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT)) 1110 1111 #define AW_PID_2049_PWDN_WORKING (0) 1112 #define AW_PID_2049_PWDN_WORKING_VALUE \ 1113 (AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT) 1114 1115 #define AW_PID_2049_PWDN_POWER_DOWN (1) 1116 #define AW_PID_2049_PWDN_POWER_DOWN_VALUE \ 1117 (AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT) 1118 1119 #define AW_PID_2049_PWDN_DEFAULT_VALUE (1) 1120 #define AW_PID_2049_PWDN_DEFAULT \ 1121 (AW_PID_2049_PWDN_DEFAULT_VALUE << AW_PID_2049_PWDN_START_BIT) 1122 1123 /* default value of SYSCTRL (0x04) */ 1124 /* #define AW_PID_2049_SYSCTRL_DEFAULT (0x5307) */ 1125 1126 /* SYSCTRL2 (0x05) detail */ 1127 /* VOL bit 15:6 (SYSCTRL2 0x05) */ 1128 #define AW_PID_2049_MUTE_VOL (90 * 8) 1129 #define AW_PID_2049_VOLUME_STEP_DB (6 * 8) 1130 1131 #define AW_PID_2049_VOL_6DB_START (6) 1132 #define AW_PID_2049_VOL_START_BIT (6) 1133 #define AW_PID_2049_VOL_BITS_LEN (10) 1134 #define AW_PID_2049_VOL_MASK \ 1135 (~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT)) 1136 1137 #define AW_PID_2049_VOL_DEFAULT_VALUE (0) 1138 #define AW_PID_2049_VOL_DEFAULT \ 1139 (AW_PID_2049_VOL_DEFAULT_VALUE << AW_PID_2049_VOL_START_BIT) 1140 1141 /* INTMODE bit 5 (SYSCTRL2 0x05) */ 1142 #define AW_PID_2049_INTMODE_START_BIT (5) 1143 #define AW_PID_2049_INTMODE_BITS_LEN (1) 1144 #define AW_PID_2049_INTMODE_MASK \ 1145 (~(((1<<AW_PID_2049_INTMODE_BITS_LEN)-1) << AW_PID_2049_INTMODE_START_BIT)) 1146 1147 #define AW_PID_2049_INTMODE_OPENMINUS_DRAIN (0) 1148 #define AW_PID_2049_INTMODE_OPENMINUS_DRAIN_VALUE \ 1149 (AW_PID_2049_INTMODE_OPENMINUS_DRAIN << AW_PID_2049_INTMODE_START_BIT) 1150 1151 #define AW_PID_2049_INTMODE_PUSHPULL (1) 1152 #define AW_PID_2049_INTMODE_PUSHPULL_VALUE \ 1153 (AW_PID_2049_INTMODE_PUSHPULL << AW_PID_2049_INTMODE_START_BIT) 1154 1155 #define AW_PID_2049_INTMODE_DEFAULT_VALUE (0) 1156 #define AW_PID_2049_INTMODE_DEFAULT \ 1157 (AW_PID_2049_INTMODE_DEFAULT_VALUE << AW_PID_2049_INTMODE_START_BIT) 1158 1159 /* INTN bit 4 (SYSCTRL2 0x05) */ 1160 #define AW_PID_2049_INTN_START_BIT (4) 1161 #define AW_PID_2049_INTN_BITS_LEN (1) 1162 #define AW_PID_2049_INTN_MASK \ 1163 (~(((1<<AW_PID_2049_INTN_BITS_LEN)-1) << AW_PID_2049_INTN_START_BIT)) 1164 1165 #define AW_PID_2049_INTN_SYSINT (0) 1166 #define AW_PID_2049_INTN_SYSINT_VALUE \ 1167 (AW_PID_2049_INTN_SYSINT << AW_PID_2049_INTN_START_BIT) 1168 1169 #define AW_PID_2049_INTN_SYSST (1) 1170 #define AW_PID_2049_INTN_SYSST_VALUE \ 1171 (AW_PID_2049_INTN_SYSST << AW_PID_2049_INTN_START_BIT) 1172 1173 #define AW_PID_2049_INTN_DEFAULT_VALUE (0) 1174 #define AW_PID_2049_INTN_DEFAULT \ 1175 (AW_PID_2049_INTN_DEFAULT_VALUE << AW_PID_2049_INTN_START_BIT) 1176 1177 /* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */ 1178 #define AW_PID_2049_BST_IPEAK_START_BIT (0) 1179 #define AW_PID_2049_BST_IPEAK_BITS_LEN (4) 1180 #define AW_PID_2049_BST_IPEAK_MASK \ 1181 (~(((1<<AW_PID_2049_BST_IPEAK_BITS_LEN)-1) << AW_PID_2049_BST_IPEAK_START_BIT)) 1182 1183 #define AW_PID_2049_BST_IPEAK_1P50A (0) 1184 #define AW_PID_2049_BST_IPEAK_1P50A_VALUE \ 1185 (AW_PID_2049_BST_IPEAK_1P50A << AW_PID_2049_BST_IPEAK_START_BIT) 1186 1187 #define AW_PID_2049_BST_IPEAK_1P75A (1) 1188 #define AW_PID_2049_BST_IPEAK_1P75A_VALUE \ 1189 (AW_PID_2049_BST_IPEAK_1P75A << AW_PID_2049_BST_IPEAK_START_BIT) 1190 1191 #define AW_PID_2049_BST_IPEAK_2P00A (2) 1192 #define AW_PID_2049_BST_IPEAK_2P00A_VALUE \ 1193 (AW_PID_2049_BST_IPEAK_2P00A << AW_PID_2049_BST_IPEAK_START_BIT) 1194 1195 #define AW_PID_2049_BST_IPEAK_2P25A (3) 1196 #define AW_PID_2049_BST_IPEAK_2P25A_VALUE \ 1197 (AW_PID_2049_BST_IPEAK_2P25A << AW_PID_2049_BST_IPEAK_START_BIT) 1198 1199 #define AW_PID_2049_BST_IPEAK_2P50A (4) 1200 #define AW_PID_2049_BST_IPEAK_2P50A_VALUE \ 1201 (AW_PID_2049_BST_IPEAK_2P50A << AW_PID_2049_BST_IPEAK_START_BIT) 1202 1203 #define AW_PID_2049_BST_IPEAK_2P75A (5) 1204 #define AW_PID_2049_BST_IPEAK_2P75A_VALUE \ 1205 (AW_PID_2049_BST_IPEAK_2P75A << AW_PID_2049_BST_IPEAK_START_BIT) 1206 1207 #define AW_PID_2049_BST_IPEAK_3P00A (6) 1208 #define AW_PID_2049_BST_IPEAK_3P00A_VALUE \ 1209 (AW_PID_2049_BST_IPEAK_3P00A << AW_PID_2049_BST_IPEAK_START_BIT) 1210 1211 #define AW_PID_2049_BST_IPEAK_3P25A (7) 1212 #define AW_PID_2049_BST_IPEAK_3P25A_VALUE \ 1213 (AW_PID_2049_BST_IPEAK_3P25A << AW_PID_2049_BST_IPEAK_START_BIT) 1214 1215 #define AW_PID_2049_BST_IPEAK_3P50A (8) 1216 #define AW_PID_2049_BST_IPEAK_3P50A_VALUE \ 1217 (AW_PID_2049_BST_IPEAK_3P50A << AW_PID_2049_BST_IPEAK_START_BIT) 1218 1219 #define AW_PID_2049_BST_IPEAK_3P75A (9) 1220 #define AW_PID_2049_BST_IPEAK_3P75A_VALUE \ 1221 (AW_PID_2049_BST_IPEAK_3P75A << AW_PID_2049_BST_IPEAK_START_BIT) 1222 1223 #define AW_PID_2049_BST_IPEAK_4P00A (10) 1224 #define AW_PID_2049_BST_IPEAK_4P00A_VALUE \ 1225 (AW_PID_2049_BST_IPEAK_4P00A << AW_PID_2049_BST_IPEAK_START_BIT) 1226 1227 #define AW_PID_2049_BST_IPEAK_4P25A (11) 1228 #define AW_PID_2049_BST_IPEAK_4P25A_VALUE \ 1229 (AW_PID_2049_BST_IPEAK_4P25A << AW_PID_2049_BST_IPEAK_START_BIT) 1230 1231 #define AW_PID_2049_BST_IPEAK_4P50A (12) 1232 #define AW_PID_2049_BST_IPEAK_4P50A_VALUE \ 1233 (AW_PID_2049_BST_IPEAK_4P50A << AW_PID_2049_BST_IPEAK_START_BIT) 1234 1235 #define AW_PID_2049_BST_IPEAK_DEFAULT_VALUE (9) 1236 #define AW_PID_2049_BST_IPEAK_DEFAULT \ 1237 (AW_PID_2049_BST_IPEAK_DEFAULT_VALUE << AW_PID_2049_BST_IPEAK_START_BIT) 1238 1239 /* default value of SYSCTRL2 (0x05) */ 1240 /* #define AW_PID_2049_SYSCTRL2_DEFAULT (0x0009) */ 1241 1242 /* I2SCTRL (0x06) detail */ 1243 /* SLOT_NUM bit 14:12 (I2SCTRL 0x06) */ 1244 #define AW_PID_2049_SLOT_NUM_START_BIT (12) 1245 #define AW_PID_2049_SLOT_NUM_BITS_LEN (3) 1246 #define AW_PID_2049_SLOT_NUM_MASK \ 1247 (~(((1<<AW_PID_2049_SLOT_NUM_BITS_LEN)-1) << AW_PID_2049_SLOT_NUM_START_BIT)) 1248 1249 #define AW_PID_2049_SLOT_NUM_I2S_MODE (0) 1250 #define AW_PID_2049_SLOT_NUM_I2S_MODE_VALUE \ 1251 (AW_PID_2049_SLOT_NUM_I2S_MODE << AW_PID_2049_SLOT_NUM_START_BIT) 1252 1253 #define AW_PID_2049_SLOT_NUM_TDM1S (1) 1254 #define AW_PID_2049_SLOT_NUM_TDM1S_VALUE \ 1255 (AW_PID_2049_SLOT_NUM_TDM1S << AW_PID_2049_SLOT_NUM_START_BIT) 1256 1257 #define AW_PID_2049_SLOT_NUM_TDM2S (2) 1258 #define AW_PID_2049_SLOT_NUM_TDM2S_VALUE \ 1259 (AW_PID_2049_SLOT_NUM_TDM2S << AW_PID_2049_SLOT_NUM_START_BIT) 1260 1261 #define AW_PID_2049_SLOT_NUM_TDM4S (3) 1262 #define AW_PID_2049_SLOT_NUM_TDM4S_VALUE \ 1263 (AW_PID_2049_SLOT_NUM_TDM4S << AW_PID_2049_SLOT_NUM_START_BIT) 1264 1265 #define AW_PID_2049_SLOT_NUM_TDM6S (4) 1266 #define AW_PID_2049_SLOT_NUM_TDM6S_VALUE \ 1267 (AW_PID_2049_SLOT_NUM_TDM6S << AW_PID_2049_SLOT_NUM_START_BIT) 1268 1269 #define AW_PID_2049_SLOT_NUM_TDM8S (5) 1270 #define AW_PID_2049_SLOT_NUM_TDM8S_VALUE \ 1271 (AW_PID_2049_SLOT_NUM_TDM8S << AW_PID_2049_SLOT_NUM_START_BIT) 1272 1273 #define AW_PID_2049_SLOT_NUM_TDM16S (6) 1274 #define AW_PID_2049_SLOT_NUM_TDM16S_VALUE \ 1275 (AW_PID_2049_SLOT_NUM_TDM16S << AW_PID_2049_SLOT_NUM_START_BIT) 1276 1277 #define AW_PID_2049_SLOT_NUM_RESERVED (7) 1278 #define AW_PID_2049_SLOT_NUM_RESERVED_VALUE \ 1279 (AW_PID_2049_SLOT_NUM_RESERVED << AW_PID_2049_SLOT_NUM_START_BIT) 1280 1281 #define AW_PID_2049_SLOT_NUM_DEFAULT_VALUE (0) 1282 #define AW_PID_2049_SLOT_NUM_DEFAULT \ 1283 (AW_PID_2049_SLOT_NUM_DEFAULT_VALUE << AW_PID_2049_SLOT_NUM_START_BIT) 1284 1285 /* CHSEL bit 11:10 (I2SCTRL 0x06) */ 1286 #define AW_PID_2049_CHSEL_START_BIT (10) 1287 #define AW_PID_2049_CHSEL_BITS_LEN (2) 1288 #define AW_PID_2049_CHSEL_MASK \ 1289 (~(((1<<AW_PID_2049_CHSEL_BITS_LEN)-1) << AW_PID_2049_CHSEL_START_BIT)) 1290 1291 #define AW_PID_2049_CHSEL_RESERVED (0) 1292 #define AW_PID_2049_CHSEL_RESERVED_VALUE \ 1293 (AW_PID_2049_CHSEL_RESERVED << AW_PID_2049_CHSEL_START_BIT) 1294 1295 #define AW_PID_2049_CHSEL_LEFT (1) 1296 #define AW_PID_2049_CHSEL_LEFT_VALUE \ 1297 (AW_PID_2049_CHSEL_LEFT << AW_PID_2049_CHSEL_START_BIT) 1298 1299 #define AW_PID_2049_CHSEL_RIGHT (2) 1300 #define AW_PID_2049_CHSEL_RIGHT_VALUE \ 1301 (AW_PID_2049_CHSEL_RIGHT << AW_PID_2049_CHSEL_START_BIT) 1302 1303 #define AW_PID_2049_CHSEL_MONO (3) 1304 #define AW_PID_2049_CHSEL_MONO_VALUE \ 1305 (AW_PID_2049_CHSEL_MONO << AW_PID_2049_CHSEL_START_BIT) 1306 1307 #define AW_PID_2049_CHSEL_DEFAULT_VALUE (1) 1308 #define AW_PID_2049_CHSEL_DEFAULT \ 1309 (AW_PID_2049_CHSEL_DEFAULT_VALUE << AW_PID_2049_CHSEL_START_BIT) 1310 1311 /* I2SMD bit 9:8 (I2SCTRL 0x06) */ 1312 #define AW_PID_2049_I2SMD_START_BIT (8) 1313 #define AW_PID_2049_I2SMD_BITS_LEN (2) 1314 #define AW_PID_2049_I2SMD_MASK \ 1315 (~(((1<<AW_PID_2049_I2SMD_BITS_LEN)-1) << AW_PID_2049_I2SMD_START_BIT)) 1316 1317 #define AW_PID_2049_I2SMD_PHILIP_STANDARD (0) 1318 #define AW_PID_2049_I2SMD_PHILIP_STANDARD_VALUE \ 1319 (AW_PID_2049_I2SMD_PHILIP_STANDARD << AW_PID_2049_I2SMD_START_BIT) 1320 1321 #define AW_PID_2049_I2SMD_MSB_JUSTIFIED (1) 1322 #define AW_PID_2049_I2SMD_MSB_JUSTIFIED_VALUE \ 1323 (AW_PID_2049_I2SMD_MSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) 1324 1325 #define AW_PID_2049_I2SMD_LSB_JUSTIFIED (2) 1326 #define AW_PID_2049_I2SMD_LSB_JUSTIFIED_VALUE \ 1327 (AW_PID_2049_I2SMD_LSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) 1328 1329 #define AW_PID_2049_I2SMD_RESERVED (3) 1330 #define AW_PID_2049_I2SMD_RESERVED_VALUE \ 1331 (AW_PID_2049_I2SMD_RESERVED << AW_PID_2049_I2SMD_START_BIT) 1332 1333 #define AW_PID_2049_I2SMD_DEFAULT_VALUE (0) 1334 #define AW_PID_2049_I2SMD_DEFAULT \ 1335 (AW_PID_2049_I2SMD_DEFAULT_VALUE << AW_PID_2049_I2SMD_START_BIT) 1336 1337 /* I2SFS bit 7:6 (I2SCTRL 0x06) */ 1338 #define AW_PID_2049_I2SFS_START_BIT (6) 1339 #define AW_PID_2049_I2SFS_BITS_LEN (2) 1340 #define AW_PID_2049_I2SFS_MASK \ 1341 (~(((1<<AW_PID_2049_I2SFS_BITS_LEN)-1) << AW_PID_2049_I2SFS_START_BIT)) 1342 1343 #define AW_PID_2049_I2SFS_16_BITS (0) 1344 #define AW_PID_2049_I2SFS_16_BITS_VALUE \ 1345 (AW_PID_2049_I2SFS_16_BITS << AW_PID_2049_I2SFS_START_BIT) 1346 1347 #define AW_PID_2049_I2SFS_20_BITS (1) 1348 #define AW_PID_2049_I2SFS_20_BITS_VALUE \ 1349 (AW_PID_2049_I2SFS_20_BITS << AW_PID_2049_I2SFS_START_BIT) 1350 1351 #define AW_PID_2049_I2SFS_24_BITS (2) 1352 #define AW_PID_2049_I2SFS_24_BITS_VALUE \ 1353 (AW_PID_2049_I2SFS_24_BITS << AW_PID_2049_I2SFS_START_BIT) 1354 1355 #define AW_PID_2049_I2SFS_32_BITS (3) 1356 #define AW_PID_2049_I2SFS_32_BITS_VALUE \ 1357 (AW_PID_2049_I2SFS_32_BITS << AW_PID_2049_I2SFS_START_BIT) 1358 1359 #define AW_PID_2049_I2SFS_DEFAULT_VALUE (3) 1360 #define AW_PID_2049_I2SFS_DEFAULT \ 1361 (AW_PID_2049_I2SFS_DEFAULT_VALUE << AW_PID_2049_I2SFS_START_BIT) 1362 1363 /* I2SBCK bit 5:4 (I2SCTRL 0x06) */ 1364 #define AW_PID_2049_I2SBCK_START_BIT (4) 1365 #define AW_PID_2049_I2SBCK_BITS_LEN (2) 1366 #define AW_PID_2049_I2SBCK_MASK \ 1367 (~(((1<<AW_PID_2049_I2SBCK_BITS_LEN)-1) << AW_PID_2049_I2SBCK_START_BIT)) 1368 1369 #define AW_PID_2049_I2SBCK_32FS (0) 1370 #define AW_PID_2049_I2SBCK_32FS_VALUE \ 1371 (AW_PID_2049_I2SBCK_32FS << AW_PID_2049_I2SBCK_START_BIT) 1372 1373 #define AW_PID_2049_I2SBCK_48FS (1) 1374 #define AW_PID_2049_I2SBCK_48FS_VALUE \ 1375 (AW_PID_2049_I2SBCK_48FS << AW_PID_2049_I2SBCK_START_BIT) 1376 1377 #define AW_PID_2049_I2SBCK_64FS (2) 1378 #define AW_PID_2049_I2SBCK_64FS_VALUE \ 1379 (AW_PID_2049_I2SBCK_64FS << AW_PID_2049_I2SBCK_START_BIT) 1380 1381 #define AW_PID_2049_I2SBCK_RESERVED (3) 1382 #define AW_PID_2049_I2SBCK_RESERVED_VALUE \ 1383 (AW_PID_2049_I2SBCK_RESERVED << AW_PID_2049_I2SBCK_START_BIT) 1384 1385 #define AW_PID_2049_I2SBCK_DEFAULT_VALUE (2) 1386 #define AW_PID_2049_I2SBCK_DEFAULT \ 1387 (AW_PID_2049_I2SBCK_DEFAULT_VALUE << AW_PID_2049_I2SBCK_START_BIT) 1388 1389 /* I2SSR bit 3:0 (I2SCTRL 0x06) */ 1390 #define AW_PID_2049_I2SSR_START_BIT (0) 1391 #define AW_PID_2049_I2SSR_BITS_LEN (4) 1392 #define AW_PID_2049_I2SSR_MASK \ 1393 (~(((1<<AW_PID_2049_I2SSR_BITS_LEN)-1) << AW_PID_2049_I2SSR_START_BIT)) 1394 1395 #define AW_PID_2049_I2SSR_8_KHZ (0) 1396 #define AW_PID_2049_I2SSR_8_KHZ_VALUE \ 1397 (AW_PID_2049_I2SSR_8_KHZ << AW_PID_2049_I2SSR_START_BIT) 1398 1399 #define AW_PID_2049_I2SSR_11_KHZ (1) 1400 #define AW_PID_2049_I2SSR_11_KHZ_VALUE \ 1401 (AW_PID_2049_I2SSR_11_KHZ << AW_PID_2049_I2SSR_START_BIT) 1402 1403 #define AW_PID_2049_I2SSR_12_KHZ (2) 1404 #define AW_PID_2049_I2SSR_12_KHZ_VALUE \ 1405 (AW_PID_2049_I2SSR_12_KHZ << AW_PID_2049_I2SSR_START_BIT) 1406 1407 #define AW_PID_2049_I2SSR_16_KHZ (3) 1408 #define AW_PID_2049_I2SSR_16_KHZ_VALUE \ 1409 (AW_PID_2049_I2SSR_16_KHZ << AW_PID_2049_I2SSR_START_BIT) 1410 1411 #define AW_PID_2049_I2SSR_22_KHZ (4) 1412 #define AW_PID_2049_I2SSR_22_KHZ_VALUE \ 1413 (AW_PID_2049_I2SSR_22_KHZ << AW_PID_2049_I2SSR_START_BIT) 1414 1415 #define AW_PID_2049_I2SSR_24_KHZ (5) 1416 #define AW_PID_2049_I2SSR_24_KHZ_VALUE \ 1417 (AW_PID_2049_I2SSR_24_KHZ << AW_PID_2049_I2SSR_START_BIT) 1418 1419 #define AW_PID_2049_I2SSR_32_KHZ (6) 1420 #define AW_PID_2049_I2SSR_32_KHZ_VALUE \ 1421 (AW_PID_2049_I2SSR_32_KHZ << AW_PID_2049_I2SSR_START_BIT) 1422 1423 #define AW_PID_2049_I2SSR_44_KHZ (7) 1424 #define AW_PID_2049_I2SSR_44_KHZ_VALUE \ 1425 (AW_PID_2049_I2SSR_44_KHZ << AW_PID_2049_I2SSR_START_BIT) 1426 1427 #define AW_PID_2049_I2SSR_48_KHZ (8) 1428 #define AW_PID_2049_I2SSR_48_KHZ_VALUE \ 1429 (AW_PID_2049_I2SSR_48_KHZ << AW_PID_2049_I2SSR_START_BIT) 1430 1431 #define AW_PID_2049_I2SSR_96_KHZ (9) 1432 #define AW_PID_2049_I2SSR_96_KHZ_VALUE \ 1433 (AW_PID_2049_I2SSR_96_KHZ << AW_PID_2049_I2SSR_START_BIT) 1434 1435 #define AW_PID_2049_I2SSR_192KHZ (10) 1436 #define AW_PID_2049_I2SSR_192KHZ_VALUE \ 1437 (AW_PID_2049_I2SSR_192KHZ << AW_PID_2049_I2SSR_START_BIT) 1438 1439 #define AW_PID_2049_I2SSR_DEFAULT_VALUE (8) 1440 #define AW_PID_2049_I2SSR_DEFAULT \ 1441 (AW_PID_2049_I2SSR_DEFAULT_VALUE << AW_PID_2049_I2SSR_START_BIT) 1442 1443 /* default value of I2SCTRL (0x06) */ 1444 /* #define AW_PID_2049_I2SCTRL_DEFAULT (0x04E8) */ 1445 1446 /* I2SCFG1 (0x07) detail */ 1447 /* I2S_RXL_SLOTVLD bit 15:12 (I2SCFG1 0x07) */ 1448 #define AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT (12) 1449 #define AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN (4) 1450 #define AW_PID_2049_I2S_RXL_SLOTVLD_MASK \ 1451 (~(((1<<AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)) 1452 1453 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 (0) 1454 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0_VALUE \ 1455 (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1456 1457 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 (1) 1458 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1_VALUE \ 1459 (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1460 1461 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 (2) 1462 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2_VALUE \ 1463 (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1464 1465 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 (3) 1466 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3_VALUE \ 1467 (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1468 1469 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 (15) 1470 #define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15_VALUE \ 1471 (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1472 1473 #define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0) 1474 #define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT \ 1475 (AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) 1476 1477 /* I2S_RXR_SLOTVLD bit 11:8 (I2SCFG1 0x07) */ 1478 #define AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT (8) 1479 #define AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN (4) 1480 #define AW_PID_2049_I2S_RXR_SLOTVLD_MASK \ 1481 (~(((1<<AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)) 1482 1483 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 (0) 1484 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0_VALUE \ 1485 (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1486 1487 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 (1) 1488 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1_VALUE \ 1489 (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1490 1491 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 (2) 1492 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2_VALUE \ 1493 (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1494 1495 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 (3) 1496 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3_VALUE \ 1497 (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1498 1499 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 (15) 1500 #define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15_VALUE \ 1501 (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1502 1503 #define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE (1) 1504 #define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT \ 1505 (AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) 1506 1507 /* I2S_TX_SLOTVLD bit 7:4 (I2SCFG1 0x07) */ 1508 #define AW_PID_2049_I2S_TX_SLOTVLD_START_BIT (4) 1509 #define AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN (4) 1510 #define AW_PID_2049_I2S_TX_SLOTVLD_MASK \ 1511 (~(((1<<AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)) 1512 1513 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 (0) 1514 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0_VALUE \ 1515 (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1516 1517 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 (1) 1518 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1_VALUE \ 1519 (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1520 1521 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 (2) 1522 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2_VALUE \ 1523 (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1524 1525 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 (3) 1526 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3_VALUE \ 1527 (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1528 1529 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 (15) 1530 #define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15_VALUE \ 1531 (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1532 1533 #define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE (0) 1534 #define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT \ 1535 (AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) 1536 1537 /* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */ 1538 #define AW_PID_2049_FSYNC_TYPE_START_BIT (3) 1539 #define AW_PID_2049_FSYNC_TYPE_BITS_LEN (1) 1540 #define AW_PID_2049_FSYNC_TYPE_MASK \ 1541 (~(((1<<AW_PID_2049_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2049_FSYNC_TYPE_START_BIT)) 1542 1543 #define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT (0) 1544 #define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \ 1545 (AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2049_FSYNC_TYPE_START_BIT) 1546 1547 #define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK (1) 1548 #define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK_VALUE \ 1549 (AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2049_FSYNC_TYPE_START_BIT) 1550 1551 #define AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE (0) 1552 #define AW_PID_2049_FSYNC_TYPE_DEFAULT \ 1553 (AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2049_FSYNC_TYPE_START_BIT) 1554 1555 /* I2SCHS bit 2 (I2SCFG1 0x07) */ 1556 #define AW_PID_2049_I2SCHS_START_BIT (2) 1557 #define AW_PID_2049_I2SCHS_BITS_LEN (1) 1558 #define AW_PID_2049_I2SCHS_MASK \ 1559 (~(((1<<AW_PID_2049_I2SCHS_BITS_LEN)-1) << AW_PID_2049_I2SCHS_START_BIT)) 1560 1561 #define AW_PID_2049_I2SCHS_LEFT (0) 1562 #define AW_PID_2049_I2SCHS_LEFT_VALUE \ 1563 (AW_PID_2049_I2SCHS_LEFT << AW_PID_2049_I2SCHS_START_BIT) 1564 1565 #define AW_PID_2049_I2SCHS_RIGHT (1) 1566 #define AW_PID_2049_I2SCHS_RIGHT_VALUE \ 1567 (AW_PID_2049_I2SCHS_RIGHT << AW_PID_2049_I2SCHS_START_BIT) 1568 1569 #define AW_PID_2049_I2SCHS_DEFAULT_VALUE (0) 1570 #define AW_PID_2049_I2SCHS_DEFAULT \ 1571 (AW_PID_2049_I2SCHS_DEFAULT_VALUE << AW_PID_2049_I2SCHS_START_BIT) 1572 1573 /* I2SRXEN bit 1 (I2SCFG1 0x07) */ 1574 #define AW_PID_2049_I2SRXEN_START_BIT (1) 1575 #define AW_PID_2049_I2SRXEN_BITS_LEN (1) 1576 #define AW_PID_2049_I2SRXEN_MASK \ 1577 (~(((1<<AW_PID_2049_I2SRXEN_BITS_LEN)-1) << AW_PID_2049_I2SRXEN_START_BIT)) 1578 1579 #define AW_PID_2049_I2SRXEN_DISABLE (0) 1580 #define AW_PID_2049_I2SRXEN_DISABLE_VALUE \ 1581 (AW_PID_2049_I2SRXEN_DISABLE << AW_PID_2049_I2SRXEN_START_BIT) 1582 1583 #define AW_PID_2049_I2SRXEN_ENABLE (1) 1584 #define AW_PID_2049_I2SRXEN_ENABLE_VALUE \ 1585 (AW_PID_2049_I2SRXEN_ENABLE << AW_PID_2049_I2SRXEN_START_BIT) 1586 1587 #define AW_PID_2049_I2SRXEN_DEFAULT_VALUE (1) 1588 #define AW_PID_2049_I2SRXEN_DEFAULT \ 1589 (AW_PID_2049_I2SRXEN_DEFAULT_VALUE << AW_PID_2049_I2SRXEN_START_BIT) 1590 1591 /* I2STXEN bit 0 (I2SCFG1 0x07) */ 1592 #define AW_PID_2049_I2STXEN_START_BIT (0) 1593 #define AW_PID_2049_I2STXEN_BITS_LEN (1) 1594 #define AW_PID_2049_I2STXEN_MASK \ 1595 (~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT)) 1596 1597 #define AW_PID_2049_I2STXEN_DISABLE (0) 1598 #define AW_PID_2049_I2STXEN_DISABLE_VALUE \ 1599 (AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT) 1600 1601 #define AW_PID_2049_I2STXEN_ENABLE (1) 1602 #define AW_PID_2049_I2STXEN_ENABLE_VALUE \ 1603 (AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT) 1604 1605 #define AW_PID_2049_I2STXEN_DEFAULT_VALUE (0) 1606 #define AW_PID_2049_I2STXEN_DEFAULT \ 1607 (AW_PID_2049_I2STXEN_DEFAULT_VALUE << AW_PID_2049_I2STXEN_START_BIT) 1608 1609 /* default value of I2SCFG1 (0x07) */ 1610 /* #define AW_PID_2049_I2SCFG1_DEFAULT (0x0102) */ 1611 1612 /* I2SCFG2 (0x08) detail */ 1613 /* ULS_FIR_MD bit 14 (I2SCFG2 0x08) */ 1614 #define AW_PID_2049_ULS_FIR_MD_START_BIT (14) 1615 #define AW_PID_2049_ULS_FIR_MD_BITS_LEN (1) 1616 #define AW_PID_2049_ULS_FIR_MD_MASK \ 1617 (~(((1<<AW_PID_2049_ULS_FIR_MD_BITS_LEN)-1) << AW_PID_2049_ULS_FIR_MD_START_BIT)) 1618 1619 #define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED (0) 1620 #define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED_VALUE \ 1621 (AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) 1622 1623 #define AW_PID_2049_ULS_FIR_MD_USED (1) 1624 #define AW_PID_2049_ULS_FIR_MD_USED_VALUE \ 1625 (AW_PID_2049_ULS_FIR_MD_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) 1626 1627 #define AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE (0) 1628 #define AW_PID_2049_ULS_FIR_MD_DEFAULT \ 1629 (AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE << AW_PID_2049_ULS_FIR_MD_START_BIT) 1630 1631 /* ULS_MODE bit 13 (I2SCFG2 0x08) */ 1632 #define AW_PID_2049_ULS_MODE_START_BIT (13) 1633 #define AW_PID_2049_ULS_MODE_BITS_LEN (1) 1634 #define AW_PID_2049_ULS_MODE_MASK \ 1635 (~(((1<<AW_PID_2049_ULS_MODE_BITS_LEN)-1) << AW_PID_2049_ULS_MODE_START_BIT)) 1636 1637 #define AW_PID_2049_ULS_MODE_LOWPASS (0) 1638 #define AW_PID_2049_ULS_MODE_LOWPASS_VALUE \ 1639 (AW_PID_2049_ULS_MODE_LOWPASS << AW_PID_2049_ULS_MODE_START_BIT) 1640 1641 #define AW_PID_2049_ULS_MODE_TDM (1) 1642 #define AW_PID_2049_ULS_MODE_TDM_VALUE \ 1643 (AW_PID_2049_ULS_MODE_TDM << AW_PID_2049_ULS_MODE_START_BIT) 1644 1645 #define AW_PID_2049_ULS_MODE_DEFAULT_VALUE (0) 1646 #define AW_PID_2049_ULS_MODE_DEFAULT \ 1647 (AW_PID_2049_ULS_MODE_DEFAULT_VALUE << AW_PID_2049_ULS_MODE_START_BIT) 1648 1649 /* ULS_EN bit 12 (I2SCFG2 0x08) */ 1650 #define AW_PID_2049_ULS_EN_START_BIT (12) 1651 #define AW_PID_2049_ULS_EN_BITS_LEN (1) 1652 #define AW_PID_2049_ULS_EN_MASK \ 1653 (~(((1<<AW_PID_2049_ULS_EN_BITS_LEN)-1) << AW_PID_2049_ULS_EN_START_BIT)) 1654 1655 #define AW_PID_2049_ULS_EN_DISABLE (0) 1656 #define AW_PID_2049_ULS_EN_DISABLE_VALUE \ 1657 (AW_PID_2049_ULS_EN_DISABLE << AW_PID_2049_ULS_EN_START_BIT) 1658 1659 #define AW_PID_2049_ULS_EN_ENABLE (1) 1660 #define AW_PID_2049_ULS_EN_ENABLE_VALUE \ 1661 (AW_PID_2049_ULS_EN_ENABLE << AW_PID_2049_ULS_EN_START_BIT) 1662 1663 #define AW_PID_2049_ULS_EN_DEFAULT_VALUE (0) 1664 #define AW_PID_2049_ULS_EN_DEFAULT \ 1665 (AW_PID_2049_ULS_EN_DEFAULT_VALUE << AW_PID_2049_ULS_EN_START_BIT) 1666 1667 /* IV2CH bit 9 (I2SCFG2 0x08) */ 1668 #define AW_PID_2049_IV2CH_START_BIT (9) 1669 #define AW_PID_2049_IV2CH_BITS_LEN (1) 1670 #define AW_PID_2049_IV2CH_MASK \ 1671 (~(((1<<AW_PID_2049_IV2CH_BITS_LEN)-1) << AW_PID_2049_IV2CH_START_BIT)) 1672 1673 #define AW_PID_2049_IV2CH_LEGACY (0) 1674 #define AW_PID_2049_IV2CH_LEGACY_VALUE \ 1675 (AW_PID_2049_IV2CH_LEGACY << AW_PID_2049_IV2CH_START_BIT) 1676 1677 #define AW_PID_2049_IV2CH_SPECIAL (1) 1678 #define AW_PID_2049_IV2CH_SPECIAL_VALUE \ 1679 (AW_PID_2049_IV2CH_SPECIAL << AW_PID_2049_IV2CH_START_BIT) 1680 1681 #define AW_PID_2049_IV2CH_DEFAULT_VALUE (0) 1682 #define AW_PID_2049_IV2CH_DEFAULT \ 1683 (AW_PID_2049_IV2CH_DEFAULT_VALUE << AW_PID_2049_IV2CH_START_BIT) 1684 1685 /* I2S_TXEDGE bit 8 (I2SCFG2 0x08) */ 1686 #define AW_PID_2049_I2S_TXEDGE_START_BIT (8) 1687 #define AW_PID_2049_I2S_TXEDGE_BITS_LEN (1) 1688 #define AW_PID_2049_I2S_TXEDGE_MASK \ 1689 (~(((1<<AW_PID_2049_I2S_TXEDGE_BITS_LEN)-1) << AW_PID_2049_I2S_TXEDGE_START_BIT)) 1690 1691 #define AW_PID_2049_I2S_TXEDGE_NEGEDGE (0) 1692 #define AW_PID_2049_I2S_TXEDGE_NEGEDGE_VALUE \ 1693 (AW_PID_2049_I2S_TXEDGE_NEGEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) 1694 1695 #define AW_PID_2049_I2S_TXEDGE_POSEDGE (1) 1696 #define AW_PID_2049_I2S_TXEDGE_POSEDGE_VALUE \ 1697 (AW_PID_2049_I2S_TXEDGE_POSEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) 1698 1699 #define AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE (0) 1700 #define AW_PID_2049_I2S_TXEDGE_DEFAULT \ 1701 (AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE << AW_PID_2049_I2S_TXEDGE_START_BIT) 1702 1703 /* I2SDOSEL bit 7 (I2SCFG2 0x08) */ 1704 #define AW_PID_2049_I2SDOSEL_START_BIT (7) 1705 #define AW_PID_2049_I2SDOSEL_BITS_LEN (1) 1706 #define AW_PID_2049_I2SDOSEL_MASK \ 1707 (~(((1<<AW_PID_2049_I2SDOSEL_BITS_LEN)-1) << AW_PID_2049_I2SDOSEL_START_BIT)) 1708 1709 #define AW_PID_2049_I2SDOSEL_ZEROS (0) 1710 #define AW_PID_2049_I2SDOSEL_ZEROS_VALUE \ 1711 (AW_PID_2049_I2SDOSEL_ZEROS << AW_PID_2049_I2SDOSEL_START_BIT) 1712 1713 #define AW_PID_2049_I2SDOSEL_TXDATA (1) 1714 #define AW_PID_2049_I2SDOSEL_TXDATA_VALUE \ 1715 (AW_PID_2049_I2SDOSEL_TXDATA << AW_PID_2049_I2SDOSEL_START_BIT) 1716 1717 #define AW_PID_2049_I2SDOSEL_DEFAULT_VALUE (0) 1718 #define AW_PID_2049_I2SDOSEL_DEFAULT \ 1719 (AW_PID_2049_I2SDOSEL_DEFAULT_VALUE << AW_PID_2049_I2SDOSEL_START_BIT) 1720 1721 /* DOHZ bit 6 (I2SCFG2 0x08) */ 1722 #define AW_PID_2049_DOHZ_START_BIT (6) 1723 #define AW_PID_2049_DOHZ_BITS_LEN (1) 1724 #define AW_PID_2049_DOHZ_MASK \ 1725 (~(((1<<AW_PID_2049_DOHZ_BITS_LEN)-1) << AW_PID_2049_DOHZ_START_BIT)) 1726 1727 #define AW_PID_2049_DOHZ_ALL (0) 1728 #define AW_PID_2049_DOHZ_ALL_VALUE \ 1729 (AW_PID_2049_DOHZ_ALL << AW_PID_2049_DOHZ_START_BIT) 1730 1731 #define AW_PID_2049_DOHZ_HIZ (1) 1732 #define AW_PID_2049_DOHZ_HIZ_VALUE \ 1733 (AW_PID_2049_DOHZ_HIZ << AW_PID_2049_DOHZ_START_BIT) 1734 1735 #define AW_PID_2049_DOHZ_DEFAULT_VALUE (1) 1736 #define AW_PID_2049_DOHZ_DEFAULT \ 1737 (AW_PID_2049_DOHZ_DEFAULT_VALUE << AW_PID_2049_DOHZ_START_BIT) 1738 1739 /* DRVSTREN bit 5 (I2SCFG2 0x08) */ 1740 #define AW_PID_2049_DRVSTREN_START_BIT (5) 1741 #define AW_PID_2049_DRVSTREN_BITS_LEN (1) 1742 #define AW_PID_2049_DRVSTREN_MASK \ 1743 (~(((1<<AW_PID_2049_DRVSTREN_BITS_LEN)-1) << AW_PID_2049_DRVSTREN_START_BIT)) 1744 1745 #define AW_PID_2049_DRVSTREN_4MA (0) 1746 #define AW_PID_2049_DRVSTREN_4MA_VALUE \ 1747 (AW_PID_2049_DRVSTREN_4MA << AW_PID_2049_DRVSTREN_START_BIT) 1748 1749 #define AW_PID_2049_DRVSTREN_12MA (1) 1750 #define AW_PID_2049_DRVSTREN_12MA_VALUE \ 1751 (AW_PID_2049_DRVSTREN_12MA << AW_PID_2049_DRVSTREN_START_BIT) 1752 1753 #define AW_PID_2049_DRVSTREN_DEFAULT_VALUE (1) 1754 #define AW_PID_2049_DRVSTREN_DEFAULT \ 1755 (AW_PID_2049_DRVSTREN_DEFAULT_VALUE << AW_PID_2049_DRVSTREN_START_BIT) 1756 1757 /* INPLEV bit 4 (I2SCFG2 0x08) */ 1758 #define AW_PID_2049_INPLEV_START_BIT (4) 1759 #define AW_PID_2049_INPLEV_BITS_LEN (1) 1760 #define AW_PID_2049_INPLEV_MASK \ 1761 (~(((1<<AW_PID_2049_INPLEV_BITS_LEN)-1) << AW_PID_2049_INPLEV_START_BIT)) 1762 1763 #define AW_PID_2049_INPLEV_NOT_ATTENUATED (0) 1764 #define AW_PID_2049_INPLEV_NOT_ATTENUATED_VALUE \ 1765 (AW_PID_2049_INPLEV_NOT_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) 1766 1767 #define AW_PID_2049_INPLEV_ATTENUATED (1) 1768 #define AW_PID_2049_INPLEV_ATTENUATED_VALUE \ 1769 (AW_PID_2049_INPLEV_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) 1770 1771 #define AW_PID_2049_INPLEV_DEFAULT_VALUE (0) 1772 #define AW_PID_2049_INPLEV_DEFAULT \ 1773 (AW_PID_2049_INPLEV_DEFAULT_VALUE << AW_PID_2049_INPLEV_START_BIT) 1774 1775 /* CFSEL bit 2:0 (I2SCFG2 0x08) */ 1776 #define AW_PID_2049_CFSEL_START_BIT (0) 1777 #define AW_PID_2049_CFSEL_BITS_LEN (3) 1778 #define AW_PID_2049_CFSEL_MASK \ 1779 (~(((1<<AW_PID_2049_CFSEL_BITS_LEN)-1) << AW_PID_2049_CFSEL_START_BIT)) 1780 1781 #define AW_PID_2049_CFSEL_HAGC (0) 1782 #define AW_PID_2049_CFSEL_HAGC_VALUE \ 1783 (AW_PID_2049_CFSEL_HAGC << AW_PID_2049_CFSEL_START_BIT) 1784 1785 #define AW_PID_2049_CFSEL_DFIFO (1) 1786 #define AW_PID_2049_CFSEL_DFIFO_VALUE \ 1787 (AW_PID_2049_CFSEL_DFIFO << AW_PID_2049_CFSEL_START_BIT) 1788 1789 #define AW_PID_2049_CFSEL_ULS (2) 1790 #define AW_PID_2049_CFSEL_ULS_VALUE \ 1791 (AW_PID_2049_CFSEL_ULS << AW_PID_2049_CFSEL_START_BIT) 1792 1793 #define AW_PID_2049_CFSEL_IVT_FS (3) 1794 #define AW_PID_2049_CFSEL_IVT_FS_VALUE \ 1795 (AW_PID_2049_CFSEL_IVT_FS << AW_PID_2049_CFSEL_START_BIT) 1796 1797 #define AW_PID_2049_CFSEL_IVT_IPVT (4) 1798 #define AW_PID_2049_CFSEL_IVT_IPVT_VALUE \ 1799 (AW_PID_2049_CFSEL_IVT_IPVT << AW_PID_2049_CFSEL_START_BIT) 1800 1801 #define AW_PID_2049_CFSEL_DEFAULT_VALUE (0) 1802 #define AW_PID_2049_CFSEL_DEFAULT \ 1803 (AW_PID_2049_CFSEL_DEFAULT_VALUE << AW_PID_2049_CFSEL_START_BIT) 1804 1805 /* default value of I2SCFG2 (0x08) */ 1806 /* #define AW_PID_2049_I2SCFG2_DEFAULT (0x0060) */ 1807 1808 /* HAGCCFG1 (0x09) detail */ 1809 /* RVTH bit 15:8 (HAGCCFG1 0x09) */ 1810 #define AW_PID_2049_RVTH_START_BIT (8) 1811 #define AW_PID_2049_RVTH_BITS_LEN (8) 1812 #define AW_PID_2049_RVTH_MASK \ 1813 (~(((1<<AW_PID_2049_RVTH_BITS_LEN)-1) << AW_PID_2049_RVTH_START_BIT)) 1814 1815 #define AW_PID_2049_RVTH_DEFAULT_VALUE (0x39) 1816 #define AW_PID_2049_RVTH_DEFAULT \ 1817 (AW_PID_2049_RVTH_DEFAULT_VALUE << AW_PID_2049_RVTH_START_BIT) 1818 1819 /* AVTH bit 7:0 (HAGCCFG1 0x09) */ 1820 #define AW_PID_2049_AVTH_START_BIT (0) 1821 #define AW_PID_2049_AVTH_BITS_LEN (8) 1822 #define AW_PID_2049_AVTH_MASK \ 1823 (~(((1<<AW_PID_2049_AVTH_BITS_LEN)-1) << AW_PID_2049_AVTH_START_BIT)) 1824 1825 #define AW_PID_2049_AVTH_DEFAULT_VALUE (0x40) 1826 #define AW_PID_2049_AVTH_DEFAULT \ 1827 (AW_PID_2049_AVTH_DEFAULT_VALUE << AW_PID_2049_AVTH_START_BIT) 1828 1829 /* default value of HAGCCFG1 (0x09) */ 1830 /* #define AW_PID_2049_HAGCCFG1_DEFAULT (0x3940) */ 1831 1832 /* HAGCCFG2 (0x0A) detail */ 1833 /* ATTH bit 15:0 (HAGCCFG2 0x0A) */ 1834 #define AW_PID_2049_ATTH_START_BIT (0) 1835 #define AW_PID_2049_ATTH_BITS_LEN (16) 1836 #define AW_PID_2049_ATTH_MASK \ 1837 (~(((1<<AW_PID_2049_ATTH_BITS_LEN)-1) << AW_PID_2049_ATTH_START_BIT)) 1838 1839 #define AW_PID_2049_ATTH_RESERVED (0) 1840 #define AW_PID_2049_ATTH_RESERVED_VALUE \ 1841 (AW_PID_2049_ATTH_RESERVED << AW_PID_2049_ATTH_START_BIT) 1842 1843 #define AW_PID_2049_ATTH_DEFAULT_VALUE (0x0030) 1844 #define AW_PID_2049_ATTH_DEFAULT \ 1845 (AW_PID_2049_ATTH_DEFAULT_VALUE << AW_PID_2049_ATTH_START_BIT) 1846 1847 /* default value of HAGCCFG2 (0x0A) */ 1848 /* #define AW_PID_2049_HAGCCFG2_DEFAULT (0x0030) */ 1849 1850 /* HAGCCFG3 (0x0B) detail */ 1851 /* RTTH bit 15:0 (HAGCCFG3 0x0B) */ 1852 #define AW_PID_2049_RTTH_START_BIT (0) 1853 #define AW_PID_2049_RTTH_BITS_LEN (16) 1854 #define AW_PID_2049_RTTH_MASK \ 1855 (~(((1<<AW_PID_2049_RTTH_BITS_LEN)-1) << AW_PID_2049_RTTH_START_BIT)) 1856 1857 #define AW_PID_2049_RTTH_RESERVED (0) 1858 #define AW_PID_2049_RTTH_RESERVED_VALUE \ 1859 (AW_PID_2049_RTTH_RESERVED << AW_PID_2049_RTTH_START_BIT) 1860 1861 #define AW_PID_2049_RTTH_DEFAULT_VALUE (0x01E0) 1862 #define AW_PID_2049_RTTH_DEFAULT \ 1863 (AW_PID_2049_RTTH_DEFAULT_VALUE << AW_PID_2049_RTTH_START_BIT) 1864 1865 /* default value of HAGCCFG3 (0x0B) */ 1866 /* #define AW_PID_2049_HAGCCFG3_DEFAULT (0x01E0) */ 1867 1868 /* HAGCCFG4 (0x0C) detail */ 1869 /* IIC_GEN_ADDR bit 15:9 (HAGCCFG4 0x0C) */ 1870 #define AW_PID_2049_IIC_GEN_ADDR_START_BIT (9) 1871 #define AW_PID_2049_IIC_GEN_ADDR_BITS_LEN (7) 1872 #define AW_PID_2049_IIC_GEN_ADDR_MASK \ 1873 (~(((1<<AW_PID_2049_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_ADDR_START_BIT)) 1874 1875 #define AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE (0x0E) 1876 #define AW_PID_2049_IIC_GEN_ADDR_DEFAULT \ 1877 (AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_ADDR_START_BIT) 1878 1879 /* IIC_GEN_EN bit 8 (HAGCCFG4 0x0C) */ 1880 #define AW_PID_2049_IIC_GEN_EN_START_BIT (8) 1881 #define AW_PID_2049_IIC_GEN_EN_BITS_LEN (1) 1882 #define AW_PID_2049_IIC_GEN_EN_MASK \ 1883 (~(((1<<AW_PID_2049_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_EN_START_BIT)) 1884 1885 #define AW_PID_2049_IIC_GEN_EN_DISABLE (0) 1886 #define AW_PID_2049_IIC_GEN_EN_DISABLE_VALUE \ 1887 (AW_PID_2049_IIC_GEN_EN_DISABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) 1888 1889 #define AW_PID_2049_IIC_GEN_EN_ENABLE (1) 1890 #define AW_PID_2049_IIC_GEN_EN_ENABLE_VALUE \ 1891 (AW_PID_2049_IIC_GEN_EN_ENABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) 1892 1893 #define AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE (0) 1894 #define AW_PID_2049_IIC_GEN_EN_DEFAULT \ 1895 (AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_EN_START_BIT) 1896 1897 /* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */ 1898 #define AW_PID_2049_HOLDTH_START_BIT (0) 1899 #define AW_PID_2049_HOLDTH_BITS_LEN (8) 1900 #define AW_PID_2049_HOLDTH_MASK \ 1901 (~(((1<<AW_PID_2049_HOLDTH_BITS_LEN)-1) << AW_PID_2049_HOLDTH_START_BIT)) 1902 1903 #define AW_PID_2049_HOLDTH_RESERVED (0) 1904 #define AW_PID_2049_HOLDTH_RESERVED_VALUE \ 1905 (AW_PID_2049_HOLDTH_RESERVED << AW_PID_2049_HOLDTH_START_BIT) 1906 1907 #define AW_PID_2049_HOLDTH_DEFAULT_VALUE (0x64) 1908 #define AW_PID_2049_HOLDTH_DEFAULT \ 1909 (AW_PID_2049_HOLDTH_DEFAULT_VALUE << AW_PID_2049_HOLDTH_START_BIT) 1910 1911 /* default value of HAGCCFG4 (0x0C) */ 1912 /* #define AW_PID_2049_HAGCCFG4_DEFAULT (0x1C64) */ 1913 1914 /* AGC_DSP_CTL bit 15 (HAGCCFG7 0x0F) */ 1915 #define AW_PID_2049_AGC_DSP_CTL_START_BIT (15) 1916 #define AW_PID_2049_AGC_DSP_CTL_BITS_LEN (1) 1917 #define AW_PID_2049_AGC_DSP_CTL_MASK \ 1918 (~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT)) 1919 1920 #define AW_PID_2049_AGC_DSP_CTL_DISABLE (0) 1921 #define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE \ 1922 (AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) 1923 1924 #define AW_PID_2049_AGC_DSP_CTL_ENABLE (1) 1925 #define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE \ 1926 (AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) 1927 /* VDSEL bit 0 (I2SCFG3 0x12) */ 1928 #define AW_PID_2049_VDSEL_START_BIT (0) 1929 #define AW_PID_2049_VDSEL_BITS_LEN (1) 1930 #define AW_PID_2049_VDSEL_MASK \ 1931 (~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT)) 1932 1933 /* MEM_CLKSEL bit 3 (DBGCTRL 0x13) */ 1934 #define AW_PID_2049_MEM_CLKSEL_START_BIT (3) 1935 #define AW_PID_2049_MEM_CLKSEL_BITS_LEN (1) 1936 #define AW_PID_2049_MEM_CLKSEL_MASK \ 1937 (~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT)) 1938 1939 #define AW_PID_2049_MEM_CLKSEL_OSC_CLK (0) 1940 #define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE \ 1941 (AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT) 1942 1943 #define AW_PID_2049_MEM_CLKSEL_DAP_HCLK (1) 1944 #define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE \ 1945 (AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT) 1946 1947 /* HAGCST (0x20) detail */ 1948 /* SPK_GAIN_ST bit 10:8 (HAGCST 0x20) */ 1949 #define AW_PID_2049_SPK_GAIN_ST_START_BIT (8) 1950 #define AW_PID_2049_SPK_GAIN_ST_BITS_LEN (3) 1951 #define AW_PID_2049_SPK_GAIN_ST_MASK \ 1952 (~(((1<<AW_PID_2049_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_ST_START_BIT)) 1953 1954 #define AW_PID_2049_SPK_GAIN_ST_4_AV (0) 1955 #define AW_PID_2049_SPK_GAIN_ST_4_AV_VALUE \ 1956 (AW_PID_2049_SPK_GAIN_ST_4_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1957 1958 #define AW_PID_2049_SPK_GAIN_ST_4P67_AV (1) 1959 #define AW_PID_2049_SPK_GAIN_ST_4P67_AV_VALUE \ 1960 (AW_PID_2049_SPK_GAIN_ST_4P67_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1961 1962 #define AW_PID_2049_SPK_GAIN_ST_6_AV (2) 1963 #define AW_PID_2049_SPK_GAIN_ST_6_AV_VALUE \ 1964 (AW_PID_2049_SPK_GAIN_ST_6_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1965 1966 #define AW_PID_2049_SPK_GAIN_ST_7_AV (3) 1967 #define AW_PID_2049_SPK_GAIN_ST_7_AV_VALUE \ 1968 (AW_PID_2049_SPK_GAIN_ST_7_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1969 1970 #define AW_PID_2049_SPK_GAIN_ST_12_AV (4) 1971 #define AW_PID_2049_SPK_GAIN_ST_12_AV_VALUE \ 1972 (AW_PID_2049_SPK_GAIN_ST_12_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1973 1974 #define AW_PID_2049_SPK_GAIN_ST_14_AV (5) 1975 #define AW_PID_2049_SPK_GAIN_ST_14_AV_VALUE \ 1976 (AW_PID_2049_SPK_GAIN_ST_14_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1977 1978 #define AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE (5) 1979 #define AW_PID_2049_SPK_GAIN_ST_DEFAULT \ 1980 (AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_ST_START_BIT) 1981 1982 /* BSTVOUT_ST bit 5:0 (HAGCST 0x20) */ 1983 #define AW_PID_2049_BSTVOUT_ST_START_BIT (0) 1984 #define AW_PID_2049_BSTVOUT_ST_BITS_LEN (6) 1985 #define AW_PID_2049_BSTVOUT_ST_MASK \ 1986 (~(((1<<AW_PID_2049_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2049_BSTVOUT_ST_START_BIT)) 1987 1988 #define AW_PID_2049_BSTVOUT_ST_3P125V (0) 1989 #define AW_PID_2049_BSTVOUT_ST_3P125V_VALUE \ 1990 (AW_PID_2049_BSTVOUT_ST_3P125V << AW_PID_2049_BSTVOUT_ST_START_BIT) 1991 1992 #define AW_PID_2049_BSTVOUT_ST_3P250V (1) 1993 #define AW_PID_2049_BSTVOUT_ST_3P250V_VALUE \ 1994 (AW_PID_2049_BSTVOUT_ST_3P250V << AW_PID_2049_BSTVOUT_ST_START_BIT) 1995 1996 #define AW_PID_2049_BSTVOUT_ST_3P375V (2) 1997 #define AW_PID_2049_BSTVOUT_ST_3P375V_VALUE \ 1998 (AW_PID_2049_BSTVOUT_ST_3P375V << AW_PID_2049_BSTVOUT_ST_START_BIT) 1999 2000 #define AW_PID_2049_BSTVOUT_ST_3P500V (3) 2001 #define AW_PID_2049_BSTVOUT_ST_3P500V_VALUE \ 2002 (AW_PID_2049_BSTVOUT_ST_3P500V << AW_PID_2049_BSTVOUT_ST_START_BIT) 2003 2004 #define AW_PID_2049_BSTVOUT_ST_3P625V (4) 2005 #define AW_PID_2049_BSTVOUT_ST_3P625V_VALUE \ 2006 (AW_PID_2049_BSTVOUT_ST_3P625V << AW_PID_2049_BSTVOUT_ST_START_BIT) 2007 2008 #define AW_PID_2049_BSTVOUT_ST_3P750V (5) 2009 #define AW_PID_2049_BSTVOUT_ST_3P750V_VALUE \ 2010 (AW_PID_2049_BSTVOUT_ST_3P750V << AW_PID_2049_BSTVOUT_ST_START_BIT) 2011 2012 #define AW_PID_2049_BSTVOUT_ST_11P000V (63) 2013 #define AW_PID_2049_BSTVOUT_ST_11P000V_VALUE \ 2014 (AW_PID_2049_BSTVOUT_ST_11P000V << AW_PID_2049_BSTVOUT_ST_START_BIT) 2015 2016 #define AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE (0) 2017 #define AW_PID_2049_BSTVOUT_ST_DEFAULT \ 2018 (AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2049_BSTVOUT_ST_START_BIT) 2019 2020 /* default value of HAGCST (0x20) */ 2021 /* #define AW_PID_2049_HAGCST_DEFAULT (0x0500) */ 2022 2023 /* VBAT (0x21) detail */ 2024 /* VBAT_DET bit 9:0 (VBAT 0x21) */ 2025 #define AW_PID_2049_VBAT_DET_START_BIT (0) 2026 #define AW_PID_2049_VBAT_DET_BITS_LEN (10) 2027 #define AW_PID_2049_VBAT_DET_MASK \ 2028 (~(((1<<AW_PID_2049_VBAT_DET_BITS_LEN)-1) << AW_PID_2049_VBAT_DET_START_BIT)) 2029 2030 #define AW_PID_2049_VBAT_DET_DEFAULT_VALUE (0x263) 2031 #define AW_PID_2049_VBAT_DET_DEFAULT \ 2032 (AW_PID_2049_VBAT_DET_DEFAULT_VALUE << AW_PID_2049_VBAT_DET_START_BIT) 2033 2034 #define AW_PID_2049_VBAT_RANGE (6025) 2035 #define AW_PID_2049_INT_10BIT (1023) 2036 /* default value of VBAT (0x21) */ 2037 /* #define AW_PID_2049_VBAT_DEFAULT (0x0263) */ 2038 2039 /* TEMP (0x22) detail */ 2040 /* TEMP_DET bit 9:0 (TEMP 0x22) */ 2041 #define AW_PID_2049_TEMP_DET_START_BIT (0) 2042 #define AW_PID_2049_TEMP_DET_BITS_LEN (10) 2043 #define AW_PID_2049_TEMP_DET_MASK \ 2044 (~(((1<<AW_PID_2049_TEMP_DET_BITS_LEN)-1) << AW_PID_2049_TEMP_DET_START_BIT)) 2045 2046 #define AW_PID_2049_TEMP_DET_MINUS_40 (0x3D8) 2047 #define AW_PID_2049_TEMP_DET_MINUS_40_VALUE \ 2048 (AW_PID_2049_TEMP_DET_MINUS_40 << AW_PID_2049_TEMP_DET_START_BIT) 2049 2050 #define AW_PID_2049_TEMP_DET_0 (0x00) 2051 #define AW_PID_2049_TEMP_DET_0_VALUE \ 2052 (AW_PID_2049_TEMP_DET_0 << AW_PID_2049_TEMP_DET_START_BIT) 2053 2054 #define AW_PID_2049_TEMP_DET_1 (0x01) 2055 #define AW_PID_2049_TEMP_DET_1_VALUE \ 2056 (AW_PID_2049_TEMP_DET_1 << AW_PID_2049_TEMP_DET_START_BIT) 2057 2058 #define AW_PID_2049_TEMP_DET_25 (0x19) 2059 #define AW_PID_2049_TEMP_DET_25_VALUE \ 2060 (AW_PID_2049_TEMP_DET_25 << AW_PID_2049_TEMP_DET_START_BIT) 2061 2062 #define AW_PID_2049_TEMP_DET_55 (0x37) 2063 #define AW_PID_2049_TEMP_DET_55_VALUE \ 2064 (AW_PID_2049_TEMP_DET_55 << AW_PID_2049_TEMP_DET_START_BIT) 2065 2066 #define AW_PID_2049_TEMP_DET_DEFAULT_VALUE (0x019) 2067 #define AW_PID_2049_TEMP_DET_DEFAULT \ 2068 (AW_PID_2049_TEMP_DET_DEFAULT_VALUE << AW_PID_2049_TEMP_DET_START_BIT) 2069 #define AW_PID_2049_TEMP_SIGN_MASK (~(1 << 9)) 2070 #define AW_PID_2049_TEMP_NEG_MASK (0XFC00) 2071 2072 /* default value of TEMP (0x22) */ 2073 /* #define AW_PID_2049_TEMP_DEFAULT (0x0019) */ 2074 2075 /* PVDD (0x23) detail */ 2076 /* PVDD_DET bit 9:0 (PVDD 0x23) */ 2077 #define AW_PID_2049_PVDD_DET_START_BIT (0) 2078 #define AW_PID_2049_PVDD_DET_BITS_LEN (10) 2079 #define AW_PID_2049_PVDD_DET_MASK \ 2080 (~(((1<<AW_PID_2049_PVDD_DET_BITS_LEN)-1) << AW_PID_2049_PVDD_DET_START_BIT)) 2081 2082 #define AW_PID_2049_PVDD_DET_DEFAULT_VALUE (0x263) 2083 #define AW_PID_2049_PVDD_DET_DEFAULT \ 2084 (AW_PID_2049_PVDD_DET_DEFAULT_VALUE << AW_PID_2049_PVDD_DET_START_BIT) 2085 2086 /* default value of PVDD (0x23) */ 2087 /* #define AW_PID_2049_PVDD_DEFAULT (0x0263) */ 2088 2089 /* BSTCTRL1 (0x60) detail */ 2090 /* BST_RTH bit 13:8 (BSTCTRL1 0x60) */ 2091 #define AW_PID_2049_BST_RTH_START_BIT (8) 2092 #define AW_PID_2049_BST_RTH_BITS_LEN (6) 2093 #define AW_PID_2049_BST_RTH_MASK \ 2094 (~(((1<<AW_PID_2049_BST_RTH_BITS_LEN)-1) << AW_PID_2049_BST_RTH_START_BIT)) 2095 2096 #define AW_PID_2049_BST_RTH_DEFAULT_VALUE (4) 2097 #define AW_PID_2049_BST_RTH_DEFAULT \ 2098 (AW_PID_2049_BST_RTH_DEFAULT_VALUE << AW_PID_2049_BST_RTH_START_BIT) 2099 2100 /* BST_ATH bit 5:0 (BSTCTRL1 0x60) */ 2101 #define AW_PID_2049_BST_ATH_START_BIT (0) 2102 #define AW_PID_2049_BST_ATH_BITS_LEN (6) 2103 #define AW_PID_2049_BST_ATH_MASK \ 2104 (~(((1<<AW_PID_2049_BST_ATH_BITS_LEN)-1) << AW_PID_2049_BST_ATH_START_BIT)) 2105 2106 #define AW_PID_2049_BST_ATH_DEFAULT_VALUE (2) 2107 #define AW_PID_2049_BST_ATH_DEFAULT \ 2108 (AW_PID_2049_BST_ATH_DEFAULT_VALUE << AW_PID_2049_BST_ATH_START_BIT) 2109 2110 /* default value of BSTCTRL1 (0x60) */ 2111 /* #define AW_PID_2049_BSTCTRL1_DEFAULT (0x0402) */ 2112 2113 /* BSTCTRL2 (0x61) detail */ 2114 /* BST_MODE bit 14:12 (BSTCTRL2 0x61) */ 2115 #define AW_PID_2049_BST_MODE_START_BIT (12) 2116 #define AW_PID_2049_BST_MODE_BITS_LEN (3) 2117 #define AW_PID_2049_BST_MODE_MASK \ 2118 (~(((1<<AW_PID_2049_BST_MODE_BITS_LEN)-1) << AW_PID_2049_BST_MODE_START_BIT)) 2119 2120 #define AW_PID_2049_BST_MODE_TRANSPARENT (0) 2121 #define AW_PID_2049_BST_MODE_TRANSPARENT_VALUE \ 2122 (AW_PID_2049_BST_MODE_TRANSPARENT << AW_PID_2049_BST_MODE_START_BIT) 2123 2124 #define AW_PID_2049_BST_MODE_FORCE_BOOST (1) 2125 #define AW_PID_2049_BST_MODE_FORCE_BOOST_VALUE \ 2126 (AW_PID_2049_BST_MODE_FORCE_BOOST << AW_PID_2049_BST_MODE_START_BIT) 2127 2128 #define AW_PID_2049_BST_MODE_SMART_BOOST1 (5) 2129 #define AW_PID_2049_BST_MODE_SMART_BOOST1_VALUE \ 2130 (AW_PID_2049_BST_MODE_SMART_BOOST1 << AW_PID_2049_BST_MODE_START_BIT) 2131 2132 #define AW_PID_2049_BST_MODE_SMART_BOOST2 (6) 2133 #define AW_PID_2049_BST_MODE_SMART_BOOST2_VALUE \ 2134 (AW_PID_2049_BST_MODE_SMART_BOOST2 << AW_PID_2049_BST_MODE_START_BIT) 2135 2136 #define AW_PID_2049_BST_MODE_DEFAULT_VALUE (0x6) 2137 #define AW_PID_2049_BST_MODE_DEFAULT \ 2138 (AW_PID_2049_BST_MODE_DEFAULT_VALUE << AW_PID_2049_BST_MODE_START_BIT) 2139 2140 /* WDT_CNT bit 7:0 (WDT 0x42) */ 2141 #define AW_PID_2049_WDT_CNT_START_BIT (0) 2142 #define AW_PID_2049_WDT_CNT_BITS_LEN (8) 2143 #define AW_PID_2049_WDT_CNT_MASK \ 2144 (~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT)) 2145 2146 /* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */ 2147 #define AW_PID_2049_BST_TDEG_START_BIT (8) 2148 #define AW_PID_2049_BST_TDEG_BITS_LEN (4) 2149 #define AW_PID_2049_BST_TDEG_MASK \ 2150 (~(((1<<AW_PID_2049_BST_TDEG_BITS_LEN)-1) << AW_PID_2049_BST_TDEG_START_BIT)) 2151 2152 #define AW_PID_2049_BST_TDEG_0P50_MS (0) 2153 #define AW_PID_2049_BST_TDEG_0P50_MS_VALUE \ 2154 (AW_PID_2049_BST_TDEG_0P50_MS << AW_PID_2049_BST_TDEG_START_BIT) 2155 2156 #define AW_PID_2049_BST_TDEG_1P00_MS (1) 2157 #define AW_PID_2049_BST_TDEG_1P00_MS_VALUE \ 2158 (AW_PID_2049_BST_TDEG_1P00_MS << AW_PID_2049_BST_TDEG_START_BIT) 2159 2160 #define AW_PID_2049_BST_TDEG_2P00_MS (2) 2161 #define AW_PID_2049_BST_TDEG_2P00_MS_VALUE \ 2162 (AW_PID_2049_BST_TDEG_2P00_MS << AW_PID_2049_BST_TDEG_START_BIT) 2163 2164 #define AW_PID_2049_BST_TDEG_4P00_MS (3) 2165 #define AW_PID_2049_BST_TDEG_4P00_MS_VALUE \ 2166 (AW_PID_2049_BST_TDEG_4P00_MS << AW_PID_2049_BST_TDEG_START_BIT) 2167 2168 #define AW_PID_2049_BST_TDEG_8P00_MS (4) 2169 #define AW_PID_2049_BST_TDEG_8P00_MS_VALUE \ 2170 (AW_PID_2049_BST_TDEG_8P00_MS << AW_PID_2049_BST_TDEG_START_BIT) 2171 2172 #define AW_PID_2049_BST_TDEG_10P7_MS (5) 2173 #define AW_PID_2049_BST_TDEG_10P7_MS_VALUE \ 2174 (AW_PID_2049_BST_TDEG_10P7_MS << AW_PID_2049_BST_TDEG_START_BIT) 2175 2176 /* ReAbs bit 3 (ASR1 0x45) */ 2177 #define AW_PID_2049_ReAbs_START_BIT (3) 2178 #define AW_PID_2049_ReAbs_BITS_LEN (1) 2179 #define AW_PID_2049_ReAbs_MASK \ 2180 (~(((1<<AW_PID_2049_ReAbs_BITS_LEN)-1) << AW_PID_2049_ReAbs_START_BIT)) 2181 2182 #define AW_PID_2049_BST_TDEG_13P3_MS (6) 2183 #define AW_PID_2049_BST_TDEG_13P3_MS_VALUE \ 2184 (AW_PID_2049_BST_TDEG_13P3_MS << AW_PID_2049_BST_TDEG_START_BIT) 2185 2186 /* DSP_VOL bit 15:8 (DSPCFG 0x47) */ 2187 #define AW_PID_2049_DSP_VOL_START_BIT (8) 2188 #define AW_PID_2049_DSP_VOL_BITS_LEN (8) 2189 #define AW_PID_2049_DSP_VOL_MASK \ 2190 (~(((1<<AW_PID_2049_DSP_VOL_BITS_LEN)-1) << AW_PID_2049_DSP_VOL_START_BIT)) 2191 2192 #define AW_PID_2049_DSP_VOL_MUTE (0XFF00) 2193 #define AW_PID_2049_DSP_VOL_NOISE_ST (0X1800) 2194 2195 #define AW_PID_2049_BST_TDEG_16P0_MS (7) 2196 #define AW_PID_2049_BST_TDEG_16P0_MS_VALUE \ 2197 (AW_PID_2049_BST_TDEG_16P0_MS << AW_PID_2049_BST_TDEG_START_BIT) 2198 2199 #define AW_PID_2049_BST_TDEG_18P6_MS (8) 2200 #define AW_PID_2049_BST_TDEG_18P6_MS_VALUE \ 2201 (AW_PID_2049_BST_TDEG_18P6_MS << AW_PID_2049_BST_TDEG_START_BIT) 2202 2203 #define AW_PID_2049_BST_TDEG_21P3_MS (9) 2204 #define AW_PID_2049_BST_TDEG_21P3_MS_VALUE \ 2205 (AW_PID_2049_BST_TDEG_21P3_MS << AW_PID_2049_BST_TDEG_START_BIT) 2206 2207 #define AW_PID_2049_BST_TDEG_24P0_MS (10) 2208 #define AW_PID_2049_BST_TDEG_24P0_MS_VALUE \ 2209 (AW_PID_2049_BST_TDEG_24P0_MS << AW_PID_2049_BST_TDEG_START_BIT) 2210 2211 #define AW_PID_2049_BST_TDEG_32P0_MS (11) 2212 #define AW_PID_2049_BST_TDEG_32P0_MS_VALUE \ 2213 (AW_PID_2049_BST_TDEG_32P0_MS << AW_PID_2049_BST_TDEG_START_BIT) 2214 2215 #define AW_PID_2049_BST_TDEG_64P0_MS (12) 2216 #define AW_PID_2049_BST_TDEG_64P0_MS_VALUE \ 2217 (AW_PID_2049_BST_TDEG_64P0_MS << AW_PID_2049_BST_TDEG_START_BIT) 2218 2219 #define AW_PID_2049_BST_TDEG_128_MS (13) 2220 #define AW_PID_2049_BST_TDEG_128_MS_VALUE \ 2221 (AW_PID_2049_BST_TDEG_128_MS << AW_PID_2049_BST_TDEG_START_BIT) 2222 2223 #define AW_PID_2049_BST_TDEG_256_MS (14) 2224 #define AW_PID_2049_BST_TDEG_256_MS_VALUE \ 2225 (AW_PID_2049_BST_TDEG_256_MS << AW_PID_2049_BST_TDEG_START_BIT) 2226 2227 #define AW_PID_2049_BST_TDEG_1200_MS (15) 2228 #define AW_PID_2049_BST_TDEG_1200_MS_VALUE \ 2229 (AW_PID_2049_BST_TDEG_1200_MS << AW_PID_2049_BST_TDEG_START_BIT) 2230 2231 #define AW_PID_2049_BST_TDEG_DEFAULT_VALUE (11) 2232 #define AW_PID_2049_BST_TDEG_DEFAULT \ 2233 (AW_PID_2049_BST_TDEG_DEFAULT_VALUE << AW_PID_2049_BST_TDEG_START_BIT) 2234 2235 /* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */ 2236 /* CCO_MUX bit 14 (PLLCTRL1 0x52) */ 2237 #define AW_PID_2049_CCO_MUX_START_BIT (14) 2238 #define AW_PID_2049_CCO_MUX_BITS_LEN (1) 2239 #define AW_PID_2049_CCO_MUX_MASK \ 2240 (~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT)) 2241 2242 #define AW_PID_2049_CCO_MUX_DIVIDED (0) 2243 #define AW_PID_2049_CCO_MUX_DIVIDED_VALUE \ 2244 (AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT) 2245 2246 #define AW_PID_2049_CCO_MUX_BYPASS (1) 2247 #define AW_PID_2049_CCO_MUX_BYPASS_VALUE \ 2248 (AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT) 2249 2250 #define AW_PID_2049_VOUT_VREFSET_START_BIT (0) 2251 #define AW_PID_2049_VOUT_VREFSET_BITS_LEN (6) 2252 #define AW_PID_2049_VOUT_VREFSET_MASK \ 2253 (~(((1<<AW_PID_2049_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2049_VOUT_VREFSET_START_BIT)) 2254 2255 #define AW_PID_2049_VOUT_VREFSET_3P125V (0) 2256 #define AW_PID_2049_VOUT_VREFSET_3P125V_VALUE \ 2257 (AW_PID_2049_VOUT_VREFSET_3P125V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2258 2259 #define AW_PID_2049_VOUT_VREFSET_3P250V (1) 2260 #define AW_PID_2049_VOUT_VREFSET_3P250V_VALUE \ 2261 (AW_PID_2049_VOUT_VREFSET_3P250V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2262 2263 #define AW_PID_2049_VOUT_VREFSET_3P375V (2) 2264 #define AW_PID_2049_VOUT_VREFSET_3P375V_VALUE \ 2265 (AW_PID_2049_VOUT_VREFSET_3P375V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2266 2267 #define AW_PID_2049_VOUT_VREFSET_3P500V (3) 2268 #define AW_PID_2049_VOUT_VREFSET_3P500V_VALUE \ 2269 (AW_PID_2049_VOUT_VREFSET_3P500V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2270 2271 #define AW_PID_2049_VOUT_VREFSET_3P625V (4) 2272 #define AW_PID_2049_VOUT_VREFSET_3P625V_VALUE \ 2273 (AW_PID_2049_VOUT_VREFSET_3P625V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2274 2275 #define AW_PID_2049_VOUT_VREFSET_3P750V (5) 2276 #define AW_PID_2049_VOUT_VREFSET_3P750V_VALUE \ 2277 (AW_PID_2049_VOUT_VREFSET_3P750V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2278 2279 #define AW_PID_2049_VOUT_VREFSET_11P000V (63) 2280 #define AW_PID_2049_VOUT_VREFSET_11P000V_VALUE \ 2281 (AW_PID_2049_VOUT_VREFSET_11P000V << AW_PID_2049_VOUT_VREFSET_START_BIT) 2282 2283 #define AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE (0x33) 2284 #define AW_PID_2049_VOUT_VREFSET_DEFAULT \ 2285 (AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2049_VOUT_VREFSET_START_BIT) 2286 2287 /* default value of BSTCTRL2 (0x61) */ 2288 /* #define AW_PID_2049_BSTCTRL2_DEFAULT (0x6B33) */ 2289 2290 /* detail information of registers end */ 2291 2292 /* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */ 2293 #define AW_PID_2049_EF_VSN_GESLP_START_BIT (0) 2294 #define AW_PID_2049_EF_VSN_GESLP_BITS_LEN (10) 2295 #define AW_PID_2049_EF_VSN_GESLP_MASK \ 2296 (~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT)) 2297 2298 #define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) 2299 #define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG (0xfe00) 2300 /* EF_ISN_GESLP bit 9:0 (EFRM2 0x79) */ 2301 #define AW_PID_2049_EF_ISN_GESLP_START_BIT (0) 2302 #define AW_PID_2049_EF_ISN_GESLP_BITS_LEN (10) 2303 #define AW_PID_2049_EF_ISN_GESLP_MASK \ 2304 (~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT)) 2305 2306 #define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) 2307 #define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG (0xfe00) 2308 /******************************************** 2309 * Vcalb 2310 *******************************************/ 2311 2312 #define AW_PID_2049_CABL_BASE_VALUE (1000) 2313 #define AW_PID_2049_ICABLK_FACTOR (1) 2314 #define AW_PID_2049_VCABLK_FACTOR (1) 2315 #define AW_PID_2049_VCAL_FACTOR (1 << 12) 2316 #define AW_PID_2049_VSCAL_FACTOR (16500) 2317 #define AW_PID_2049_ISCAL_FACTOR (3667) 2318 #define AW_PID_2049_EF_VSENSE_GAIN_SHIFT (0) 2319 2320 #define AW_PID_2049_VCABLK_FACTOR_DAC (2) 2321 #define AW_PID_2049_VSCAL_FACTOR_DAC (11790) 2322 #define AW_PID_2049_EF_DAC_GESLP_SHIFT (10) 2323 #define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK (1 << 5) 2324 #define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG (0xffc0) 2325 2326 #define AW_PID_2049_VCALB_ADJ_FACTOR (12) 2327 2328 /******************************************** 2329 * AW883XX DSP 2330 *******************************************/ 2331 #define AW_PID_2049_DSP_CFG_ADDR (0x9C80) 2332 #define AW_PID_2049_DSP_FW_ADDR (0x8C00) 2333 2334 #define AW_PID_2049_DSP_REG_RESULT_F0 (0x9C58) 2335 #define AW_PID_2049_DSP_F0_SHIFT (1) 2336 2337 #define AW_PID_2049_DSP_REG_CALRE (0x9C5A) 2338 #define AW_PID_2049_DSP_REG_CALRE_SHIFT (10) 2339 #define AW_PID_2049_DSP_REG_RESULT_Q (0x9C5C) 2340 #define AW_PID_2049_DSP_Q_SHIFT (11) 2341 2342 #define AW_PID_2049_DSP_REG_VMAX (0x9C94) 2343 2344 2345 #define AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG (0x9CE2) 2346 /* bit 0 */ 2347 #define AW_PID_2049_DSP_MONITOR_MASK (~(1 << 0)) 2348 #define AW_PID_2049_DSP_MONITOR_ENABLE (1 << 0) 2349 #define AW_PID_2049_DSP_MONITOR_DISABLE (0 << 0) 2350 /*bit 4*/ 2351 #define AW_PID_2049_DSP_REG_NOISE_MASK (~(1 << 4)) 2352 2353 #define AW_PID_2049_DSP_TEMP_PEAK_MASK (~(1 << 4)) 2354 #define AW_PID_2049_DSP_TEMP_SEL_FLAG (~(1 << 14)) 2355 2356 #define AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH (0x9CE4)/*32bit*/ 2357 #define AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH (0x9CE6)/*32bit*/ 2358 #define AW_PID_2049_DSP_REG_VCALB (0x9CF7) 2359 2360 #define AW_PID_2049_DSP_REG_CFG_ADPZ_RE (0x9D00)/*32bit*/ 2361 #define AW_PID_2049_DSP_RE_SHIFT (12) 2362 2363 #define AW_PID_2049_DSP_REG_CFG_ADPZ_RA (0x9D02)/*32bit*/ 2364 2365 #define AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN (0x9D08) 2366 2367 2368 #define AW_PID_2049_DSP_REG_CRC_ADDR (0x9F42)/*32bit*/ 2369 #define AW_PID_2049_DSP_REG_CFGF0_FS (0x9F44)/*32bit*/ 2370 #define AW_PID_2049_DSP_REG_CFG_RE_ALPHA (0x9F47) 2371 #define AW_PID_2049_DSP_REG_TEMP_ADDR (0x9C5D) 2372 #define AW_PID_2049_DSP_REG_TEMP_SWITCH (0x9D71)/*16bit*/ 2373 #define AW_PID_2049_DSP_CALI_F0_DELAY (0x9CFD) 2374 #define AW_PID_2049_DSP_CFG_ADPZ_T0 (0x9D11)/*16bit*/ 2375 #define AW_PID_2049_DSP_CFG_ADPZ_COILALPHA (0x9D0F)/*16bit*/ 2376 #define AW_PID_2049_DSP_ST_S1 (0x8180) 2377 #define AW_PID_2049_DSP_ST_E1 (0x83FD) 2378 #define AW_PID_2049_DSP_ST_S2 (0x9C00) 2379 #define AW_PID_2049_DSP_ST_E2 (0x9C5D) 2380 2381 #endif /* #ifndef __AW_PID_2049_REG_H__ */ 2382