1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __AW_SPIN_H__ 3 #define __AW_SPIN_H__ 4 5 /*#define AW_MTK_PLATFORM_SPIN*/ 6 /*#define AW_QCOM_PLATFORM_SPIN*/ 7 8 #define AW_DSP_TRY_TIME (3) 9 10 #define AW_DSP_MSG_HDR_VER (1) 11 #define AFE_MSG_ID_MSG_0 (0X10013D2A) 12 #define AFE_MSG_ID_MSG_1 (0X10013D2B) 13 #define AW_RX_PORT_ID (0x1006) 14 #define AW_RX_TOPO_ID (0x1000FF01) 15 #define AW_MSG_ID_SPIN (0x10013D2E) 16 #define AW_INLINE_ID_AUDIO_MIX (0x0000000B) 17 18 enum { 19 AW_DEV_CH_PRI_L = 0, 20 AW_DEV_CH_PRI_R = 1, 21 AW_DEV_CH_SEC_L = 2, 22 AW_DEV_CH_SEC_R = 3, 23 AW_DEV_CHAN_MAX, 24 }; 25 26 enum aw_dsp_msg_type { 27 AW_DSP_MSG_TYPE_DATA = 0, 28 AW_DSP_MSG_TYPE_CMD = 1, 29 }; 30 31 enum { 32 AW_SPIN_OFF = 0, 33 AW_SPIN_ON = 1, 34 }; 35 36 enum { 37 AW_SPIN_0 = 0, 38 AW_SPIN_90, 39 AW_SPIN_180, 40 AW_SPIN_270, 41 AW_SPIN_MAX, 42 }; 43 44 enum { 45 AW_SPIN_OFF_MODE = 0, 46 AW_ADSP_SPIN_MODE, 47 AW_REG_SPIN_MODE, 48 AW_REG_MIXER_SPIN_MODE, 49 AW_SPIN_MODE_MAX, 50 }; 51 52 enum { 53 AW_AUDIO_MIX_DISABLE = 0, 54 AW_AUDIO_MIX_ENABLE, 55 }; 56 57 struct aw_spin_ch { 58 uint16_t rx_val; 59 uint16_t tx_val; 60 }; 61 62 struct aw_spin_desc { 63 struct aw_spin_ch spin_table[AW_SPIN_MAX]; 64 uint32_t spin_mode; 65 }; 66 67 int aw_check_spin_mode(struct aw_spin_desc *spin_desc); 68 int aw_hold_dsp_spin_st(struct aw_spin_desc *spin_desc); 69 int aw_hold_reg_spin_st(struct aw_spin_desc *spin_desc); 70 void aw_add_spin_controls(void *aw_dev); 71 void aw_spin_init(struct aw_spin_desc *spin_desc); 72 73 #endif 74