1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef __AW87XXX_PID_9B_REG_H__ 4 #define __AW87XXX_PID_9B_REG_H__ 5 6 #define AW87XXX_PID_9B_CHIPID_REG (0x00) 7 #define AW87XXX_PID_9B_SYSCTRL_REG (0x01) 8 #define AW87XXX_PID_9B_BATSAFE_REG (0x02) 9 #define AW87XXX_PID_9B_BOV_REG (0x03) 10 #define AW87XXX_PID_9B_BP_REG (0x04) 11 #define AW87XXX_PID_9B_GAIN_REG (0x05) 12 #define AW87XXX_PID_9B_AGC3_PO_REG (0x06) 13 #define AW87XXX_PID_9B_AGC3_REG (0x07) 14 #define AW87XXX_PID_9B_AGC2_REG (0x08) 15 #define AW87XXX_PID_9B_AGC1_REG (0x09) 16 17 #define AW87XXX_PID_9B_SYSCTRL_DEFAULT (0x03) 18 19 /******************************************** 20 * soft control info 21 * If you need to update this file, add this information manually 22 *******************************************/ 23 unsigned char aw87xxx_pid_9b_softrst_access[2] = {0x00, 0xaa}; 24 25 /******************************************** 26 * Register Access 27 *******************************************/ 28 #define AW87XXX_PID_9B_REG_MAX (0x64) 29 30 #define REG_NONE_ACCESS (0) 31 #define REG_RD_ACCESS (1 << 0) 32 #define REG_WR_ACCESS (1 << 1) 33 34 const unsigned char aw87xxx_pid_9b_reg_access[AW87XXX_PID_9B_REG_MAX] = { 35 [AW87XXX_PID_9B_CHIPID_REG] = (REG_RD_ACCESS), 36 [AW87XXX_PID_9B_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 37 [AW87XXX_PID_9B_BATSAFE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 38 [AW87XXX_PID_9B_BOV_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 39 [AW87XXX_PID_9B_BP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 40 [AW87XXX_PID_9B_GAIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 41 [AW87XXX_PID_9B_AGC3_PO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 42 [AW87XXX_PID_9B_AGC3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 43 [AW87XXX_PID_9B_AGC2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 44 [AW87XXX_PID_9B_AGC1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), 45 }; 46 47 48 #define AW87XXX_PID_9B_ENCRYPTION_REG (0x64) 49 #define AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET (0x2C) 50 51 /* REG_EN_SW bit 2 (SYSCTRL 0x01) */ 52 #define AW87XXX_PID_9B_REG_EN_SW_START_BIT (2) 53 #define AW87XXX_PID_9B_REG_EN_SW_BITS_LEN (1) 54 #define AW87XXX_PID_9B_REG_EN_SW_MASK \ 55 (~(((1<<AW87XXX_PID_9B_REG_EN_SW_BITS_LEN)-1) << AW87XXX_PID_9B_REG_EN_SW_START_BIT)) 56 57 #define AW87XXX_PID_9B_REG_EN_SW_DISABLE (0) 58 #define AW87XXX_PID_9B_REG_EN_SW_DISABLE_VALUE \ 59 (AW87XXX_PID_9B_REG_EN_SW_DISABLE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) 60 61 #define AW87XXX_PID_9B_REG_EN_SW_ENABLE (1) 62 #define AW87XXX_PID_9B_REG_EN_SW_ENABLE_VALUE \ 63 (AW87XXX_PID_9B_REG_EN_SW_ENABLE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) 64 65 #define AW87XXX_PID_9B_REG_EN_SW_DEFAULT_VALUE (1) 66 #define AW87XXX_PID_9B_REG_EN_SW_DEFAULT \ 67 (AW87XXX_PID_9B_REG_EN_SW_DEFAULT_VALUE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) 68 69 /* SPK_MODE bit 0 (SYSCTRL 0x01) */ 70 #define AW87XXX_PID_9B_SPK_MODE_START_BIT (0) 71 #define AW87XXX_PID_9B_SPK_MODE_BITS_LEN (1) 72 #define AW87XXX_PID_9B_SPK_MODE_MASK \ 73 (~(((1<<AW87XXX_PID_9B_SPK_MODE_BITS_LEN)-1) << AW87XXX_PID_9B_SPK_MODE_START_BIT)) 74 75 #define AW87XXX_PID_9B_SPK_MODE_DISABLE (0) 76 #define AW87XXX_PID_9B_SPK_MODE_DISABLE_VALUE \ 77 (AW87XXX_PID_9B_SPK_MODE_DISABLE << AW87XXX_PID_9B_SPK_MODE_START_BIT) 78 79 #define AW87XXX_PID_9B_SPK_MODE_ENABLE (1) 80 #define AW87XXX_PID_9B_SPK_MODE_ENABLE_VALUE \ 81 (AW87XXX_PID_9B_SPK_MODE_ENABLE << AW87XXX_PID_9B_SPK_MODE_START_BIT) 82 83 #endif 84