1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * @Descripttion: Header file of AW87XXX_PID_59_5X9_REG 4 * @version: V1.33 5 * @Author: zhaozhongbo 6 * @Date: 2021-03-10 7 * @LastEditors: Please set LastEditors 8 * @LastEditTime: 2021-03-10 9 */ 10 #ifndef __AW87XXX_PID_59_5X9_REG_H__ 11 #define __AW87XXX_PID_59_5X9_REG_H__ 12 13 14 #define AW87XXX_PID_59_5X9_REG_CHIPID (0x00) 15 #define AW87XXX_PID_59_5X9_REG_SYSCTRL (0x01) 16 #define AW87XXX_PID_59_5X9_REG_BATSAFE (0x02) 17 #define AW87XXX_PID_59_5X9_REG_BSTOVR (0x03) 18 #define AW87XXX_PID_59_5X9_REG_BSTVPR (0x04) 19 #define AW87XXX_PID_59_5X9_REG_PAGR (0x05) 20 #define AW87XXX_PID_59_5X9_REG_PAGC3OPR (0x06) 21 #define AW87XXX_PID_59_5X9_REG_PAGC3PR (0x07) 22 #define AW87XXX_PID_59_5X9_REG_PAGC2OPR (0x08) 23 #define AW87XXX_PID_59_5X9_REG_PAGC2PR (0x09) 24 #define AW87XXX_PID_59_5X9_REG_PAGC1PR (0x0A) 25 #define AW87XXX_PID_59_5X9_REG_SYSST (0x58) 26 #define AW87XXX_PID_59_5X9_REG_SYSINT (0x59) 27 #define AW87XXX_PID_59_5X9_REG_CPCR (0x60) 28 #define AW87XXX_PID_59_5X9_REG_DFT1R (0x61) 29 #define AW87XXX_PID_59_5X9_REG_DFT2R (0x62) 30 #define AW87XXX_PID_59_5X9_REG_DFT3R (0x63) 31 #define AW87XXX_PID_59_5X9_REG_DFT4R (0x64) 32 #define AW87XXX_PID_59_5X9_REG_DFT5R (0x65) 33 #define AW87XXX_PID_59_5X9_REG_DFT6R (0x66) 34 #define AW87XXX_PID_59_5X9_REG_DFT7R (0x67) 35 #define AW87XXX_PID_59_5X9_REG_DFT8R (0x68) 36 #define AW87XXX_PID_59_5X9_REG_ENCR (0x69) 37 38 #define AW87XXX_PID_59_5X9_ENCRY_DEFAULT (0x00) 39 40 /******************************************** 41 * soft control info 42 * If you need to update this file, add this information manually 43 *******************************************/ 44 unsigned char aw87xxx_pid_59_5x9_softrst_access[2] = {0x00, 0xaa}; 45 46 /******************************************** 47 * Register Access 48 *******************************************/ 49 #define AW87XXX_PID_59_5X9_REG_MAX (0x70) 50 51 #define REG_NONE_ACCESS (0) 52 #define REG_RD_ACCESS (1 << 0) 53 #define REG_WR_ACCESS (1 << 1) 54 55 const unsigned char aw87xxx_pid_59_5x9_reg_access[AW87XXX_PID_59_5X9_REG_MAX] = { 56 [AW87XXX_PID_59_5X9_REG_CHIPID] = (REG_RD_ACCESS), 57 [AW87XXX_PID_59_5X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 58 [AW87XXX_PID_59_5X9_REG_BATSAFE] = (REG_RD_ACCESS | REG_WR_ACCESS), 59 [AW87XXX_PID_59_5X9_REG_BSTOVR] = (REG_RD_ACCESS | REG_WR_ACCESS), 60 [AW87XXX_PID_59_5X9_REG_BSTVPR] = (REG_RD_ACCESS | REG_WR_ACCESS), 61 [AW87XXX_PID_59_5X9_REG_PAGR] = (REG_RD_ACCESS | REG_WR_ACCESS), 62 [AW87XXX_PID_59_5X9_REG_PAGC3OPR] = (REG_RD_ACCESS | REG_WR_ACCESS), 63 [AW87XXX_PID_59_5X9_REG_PAGC3PR] = (REG_RD_ACCESS | REG_WR_ACCESS), 64 [AW87XXX_PID_59_5X9_REG_PAGC2OPR] = (REG_RD_ACCESS | REG_WR_ACCESS), 65 [AW87XXX_PID_59_5X9_REG_PAGC2PR] = (REG_RD_ACCESS | REG_WR_ACCESS), 66 [AW87XXX_PID_59_5X9_REG_PAGC1PR] = (REG_RD_ACCESS | REG_WR_ACCESS), 67 [AW87XXX_PID_59_5X9_REG_SYSST] = (REG_RD_ACCESS), 68 [AW87XXX_PID_59_5X9_REG_SYSINT] = (REG_RD_ACCESS), 69 [AW87XXX_PID_59_5X9_REG_CPCR] = (REG_RD_ACCESS | REG_WR_ACCESS), 70 [AW87XXX_PID_59_5X9_REG_DFT1R] = (REG_RD_ACCESS | REG_WR_ACCESS), 71 [AW87XXX_PID_59_5X9_REG_DFT2R] = (REG_RD_ACCESS | REG_WR_ACCESS), 72 [AW87XXX_PID_59_5X9_REG_DFT3R] = (REG_RD_ACCESS | REG_WR_ACCESS), 73 [AW87XXX_PID_59_5X9_REG_DFT4R] = (REG_RD_ACCESS | REG_WR_ACCESS), 74 [AW87XXX_PID_59_5X9_REG_DFT5R] = (REG_RD_ACCESS | REG_WR_ACCESS), 75 [AW87XXX_PID_59_5X9_REG_DFT6R] = (REG_RD_ACCESS | REG_WR_ACCESS), 76 [AW87XXX_PID_59_5X9_REG_DFT7R] = (REG_RD_ACCESS | REG_WR_ACCESS), 77 [AW87XXX_PID_59_5X9_REG_DFT8R] = (REG_RD_ACCESS | REG_WR_ACCESS), 78 [AW87XXX_PID_59_5X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS), 79 }; 80 81 /* RCV_MODE bit 3 (SYSCTRL 0x01) */ 82 #define AW87XXX_PID_59_5X9_REC_MODE_START_BIT (3) 83 #define AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN (1) 84 #define AW87XXX_PID_59_5X9_REC_MODE_MASK \ 85 (~(((1<<AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_59_5X9_REC_MODE_START_BIT)) 86 87 #define AW87XXX_PID_59_5X9_REC_MODE_DISABLE (0) 88 #define AW87XXX_PID_59_5X9_REC_MODE_DISABLE_VALUE \ 89 (AW87XXX_PID_59_5X9_REC_MODE_DISABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT) 90 91 #define AW87XXX_PID_59_5X9_REC_MODE_ENABLE (1) 92 #define AW87XXX_PID_59_5X9_REC_MODE_ENABLE_VALUE \ 93 (AW87XXX_PID_59_5X9_REC_MODE_ENABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT) 94 95 #endif 96