1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * @Descripttion: Header file of AW87XXX_PID_59_3X9_REG 4 * @version: V1.33 5 * @Author: zhaozhongbo 6 * @Date: 2021-03-10 7 * @LastEditors: Please set LastEditors 8 * @LastEditTime: 2021-03-10 9 */ 10 #ifndef __AW87XXX_PID_59_3X9_REG_H__ 11 #define __AW87XXX_PID_59_3X9_REG_H__ 12 13 #define AW87XXX_PID_59_3X9_REG_CHIPID (0x00) 14 #define AW87XXX_PID_59_3X9_REG_SYSCTRL (0x01) 15 #define AW87XXX_PID_59_3X9_REG_MDCRTL (0x02) 16 #define AW87XXX_PID_59_3X9_REG_CPOVP (0x03) 17 #define AW87XXX_PID_59_3X9_REG_CPP (0x04) 18 #define AW87XXX_PID_59_3X9_REG_PAG (0x05) 19 #define AW87XXX_PID_59_3X9_REG_AGC3PO (0x06) 20 #define AW87XXX_PID_59_3X9_REG_AGC3PA (0x07) 21 #define AW87XXX_PID_59_3X9_REG_AGC2PO (0x08) 22 #define AW87XXX_PID_59_3X9_REG_AGC2PA (0x09) 23 #define AW87XXX_PID_59_3X9_REG_AGC1PA (0x0A) 24 #define AW87XXX_PID_59_3X9_REG_SYSST (0x59) 25 #define AW87XXX_PID_59_3X9_REG_SYSINT (0x60) 26 #define AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL (0x61) 27 #define AW87XXX_PID_59_3X9_REG_DFT_MDCTRL (0x62) 28 #define AW87XXX_PID_59_3X9_REG_DFT_CPOVP2 (0x63) 29 #define AW87XXX_PID_59_3X9_REG_DFT_AGCPA (0x64) 30 #define AW87XXX_PID_59_3X9_REG_DFT_POFR (0x65) 31 #define AW87XXX_PID_59_3X9_REG_DFT_OC (0x66) 32 #define AW87XXX_PID_59_3X9_REG_DFT_OTA (0x67) 33 #define AW87XXX_PID_59_3X9_REG_DFT_REF (0x68) 34 #define AW87XXX_PID_59_3X9_REG_DFT_LDO (0x69) 35 #define AW87XXX_PID_59_3X9_REG_ENCR (0x70) 36 37 #define AW87XXX_PID_59_3X9_ENCR_DEFAULT (0x00) 38 39 /******************************************** 40 * soft control info 41 * If you need to update this file, add this information manually 42 *******************************************/ 43 unsigned char aw87xxx_pid_59_3x9_softrst_access[2] = {0x00, 0xaa}; 44 45 /******************************************** 46 * Register Access 47 *******************************************/ 48 #define AW87XXX_PID_59_3X9_REG_MAX (0x71) 49 50 #define REG_NONE_ACCESS (0) 51 #define REG_RD_ACCESS (1 << 0) 52 #define REG_WR_ACCESS (1 << 1) 53 54 const unsigned char aw87xxx_pid_59_3x9_reg_access[AW87XXX_PID_59_3X9_REG_MAX] = { 55 [AW87XXX_PID_59_3X9_REG_CHIPID] = (REG_RD_ACCESS), 56 [AW87XXX_PID_59_3X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 57 [AW87XXX_PID_59_3X9_REG_MDCRTL] = (REG_RD_ACCESS | REG_WR_ACCESS), 58 [AW87XXX_PID_59_3X9_REG_CPOVP] = (REG_RD_ACCESS | REG_WR_ACCESS), 59 [AW87XXX_PID_59_3X9_REG_CPP] = (REG_RD_ACCESS | REG_WR_ACCESS), 60 [AW87XXX_PID_59_3X9_REG_PAG] = (REG_RD_ACCESS | REG_WR_ACCESS), 61 [AW87XXX_PID_59_3X9_REG_AGC3PO] = (REG_RD_ACCESS | REG_WR_ACCESS), 62 [AW87XXX_PID_59_3X9_REG_AGC3PA] = (REG_RD_ACCESS | REG_WR_ACCESS), 63 [AW87XXX_PID_59_3X9_REG_AGC2PO] = (REG_RD_ACCESS | REG_WR_ACCESS), 64 [AW87XXX_PID_59_3X9_REG_AGC2PA] = (REG_RD_ACCESS | REG_WR_ACCESS), 65 [AW87XXX_PID_59_3X9_REG_AGC1PA] = (REG_RD_ACCESS | REG_WR_ACCESS), 66 [AW87XXX_PID_59_3X9_REG_SYSST] = (REG_RD_ACCESS), 67 [AW87XXX_PID_59_3X9_REG_SYSINT] = (REG_RD_ACCESS), 68 [AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 69 [AW87XXX_PID_59_3X9_REG_DFT_MDCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 70 [AW87XXX_PID_59_3X9_REG_DFT_CPOVP2] = (REG_RD_ACCESS | REG_WR_ACCESS), 71 [AW87XXX_PID_59_3X9_REG_DFT_AGCPA] = (REG_RD_ACCESS | REG_WR_ACCESS), 72 [AW87XXX_PID_59_3X9_REG_DFT_POFR] = (REG_RD_ACCESS | REG_WR_ACCESS), 73 [AW87XXX_PID_59_3X9_REG_DFT_OC] = (REG_RD_ACCESS | REG_WR_ACCESS), 74 [AW87XXX_PID_59_3X9_REG_DFT_OTA] = (REG_RD_ACCESS | REG_WR_ACCESS), 75 [AW87XXX_PID_59_3X9_REG_DFT_REF] = (REG_RD_ACCESS | REG_WR_ACCESS), 76 [AW87XXX_PID_59_3X9_REG_DFT_LDO] = (REG_RD_ACCESS | REG_WR_ACCESS), 77 [AW87XXX_PID_59_3X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS), 78 }; 79 80 /* SPK_MODE bit 2 (MDCRTL 0x02) */ 81 #define AW87XXX_PID_59_3X9_SPK_MODE_START_BIT (2) 82 #define AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN (1) 83 #define AW87XXX_PID_59_3X9_SPK_MODE_MASK \ 84 (~(((1<<AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN)-1) << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT)) 85 86 #define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE (0) 87 #define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE_VALUE \ 88 (AW87XXX_PID_59_3X9_SPK_MODE_DISABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT) 89 90 #define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE (1) 91 #define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE_VALUE \ 92 (AW87XXX_PID_59_3X9_SPK_MODE_ENABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT) 93 94 #endif 95