1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef __AW87XXX_PID_39_REG_H__ 4 #define __AW87XXX_PID_39_REG_H__ 5 6 #define AW87XXX_PID_39_REG_CHIPID (0x00) 7 #define AW87XXX_PID_39_REG_SYSCTRL (0x01) 8 #define AW87XXX_PID_39_REG_MODECTRL (0x02) 9 #define AW87XXX_PID_39_REG_CPOVP (0x03) 10 #define AW87XXX_PID_39_REG_CPP (0x04) 11 #define AW87XXX_PID_39_REG_GAIN (0x05) 12 #define AW87XXX_PID_39_REG_AGC3_PO (0x06) 13 #define AW87XXX_PID_39_REG_AGC3 (0x07) 14 #define AW87XXX_PID_39_REG_AGC2_PO (0x08) 15 #define AW87XXX_PID_39_REG_AGC2 (0x09) 16 #define AW87XXX_PID_39_REG_AGC1 (0x0A) 17 #define AW87XXX_PID_39_REG_DFT1 (0x62) 18 #define AW87XXX_PID_39_REG_DFT2 (0x63) 19 #define AW87XXX_PID_39_REG_ENCRY (0x64) 20 21 #define AW87XXX_PID_39_MODECTRL_DEFAULT (0xa0) 22 23 /******************************************** 24 * soft control info 25 * If you need to update this file, add this information manually 26 *******************************************/ 27 unsigned char aw87xxx_pid_39_softrst_access[2] = {0x00, 0xaa}; 28 29 /******************************************** 30 * Register Access 31 *******************************************/ 32 #define AW87XXX_PID_39_REG_MAX (0x65) 33 34 #define REG_NONE_ACCESS (0) 35 #define REG_RD_ACCESS (1 << 0) 36 #define REG_WR_ACCESS (1 << 1) 37 38 const unsigned char aw87xxx_pid_39_reg_access[AW87XXX_PID_39_REG_MAX] = { 39 [AW87XXX_PID_39_REG_CHIPID] = (REG_RD_ACCESS), 40 [AW87XXX_PID_39_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 41 [AW87XXX_PID_39_REG_MODECTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), 42 [AW87XXX_PID_39_REG_CPOVP] = (REG_RD_ACCESS | REG_WR_ACCESS), 43 [AW87XXX_PID_39_REG_CPP] = (REG_RD_ACCESS | REG_WR_ACCESS), 44 [AW87XXX_PID_39_REG_GAIN] = (REG_RD_ACCESS | REG_WR_ACCESS), 45 [AW87XXX_PID_39_REG_AGC3_PO] = (REG_RD_ACCESS | REG_WR_ACCESS), 46 [AW87XXX_PID_39_REG_AGC3] = (REG_RD_ACCESS | REG_WR_ACCESS), 47 [AW87XXX_PID_39_REG_AGC2_PO] = (REG_RD_ACCESS | REG_WR_ACCESS), 48 [AW87XXX_PID_39_REG_AGC2] = (REG_RD_ACCESS | REG_WR_ACCESS), 49 [AW87XXX_PID_39_REG_AGC1] = (REG_RD_ACCESS | REG_WR_ACCESS), 50 [AW87XXX_PID_39_REG_DFT1] = (REG_RD_ACCESS), 51 [AW87XXX_PID_39_REG_DFT2] = (REG_RD_ACCESS), 52 [AW87XXX_PID_39_REG_ENCRY] = (REG_RD_ACCESS), 53 }; 54 55 /* RCV_MODE bit 3 (MODECTRL 0x02) */ 56 #define AW87XXX_PID_39_REC_MODE_START_BIT (3) 57 #define AW87XXX_PID_39_REC_MODE_BITS_LEN (1) 58 #define AW87XXX_PID_39_REC_MODE_MASK \ 59 (~(((1<<AW87XXX_PID_39_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_39_REC_MODE_START_BIT)) 60 61 #define AW87XXX_PID_39_REC_MODE_DISABLE (0) 62 #define AW87XXX_PID_39_REC_MODE_DISABLE_VALUE \ 63 (AW87XXX_PID_39_REC_MODE_DISABLE << AW87XXX_PID_39_REC_MODE_START_BIT) 64 65 #define AW87XXX_PID_39_REC_MODE_ENABLE (1) 66 #define AW87XXX_PID_39_REC_MODE_ENABLE_VALUE \ 67 (AW87XXX_PID_39_REC_MODE_ENABLE << AW87XXX_PID_39_REC_MODE_START_BIT) 68 69 #endif 70