1 /* 2 * rk1000_codec.h -- rk1000 ALSA Soc Audio driver 3 * 4 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 */ 19 #ifndef _RK1000_CODEC_H 20 #define _RK1000_CODEC_H 21 22 /* RK1000 register space */ 23 /* ADC High Pass Filter / DSM */ 24 #define ACCELCODEC_R00 0x00 25 /* DITHER power */ 26 #define ACCELCODEC_R01 0x01 27 /* DITHER power */ 28 #define ACCELCODEC_R02 0x02 29 /* DITHER power */ 30 #define ACCELCODEC_R03 0x03 31 /* Soft mute / sidetone gain control */ 32 #define ACCELCODEC_R04 0x04 33 /* Right interpolate filter volume control (MSB) */ 34 #define ACCELCODEC_R05 0x05 35 /* Right interpolate filter volume control (LSB) */ 36 #define ACCELCODEC_R06 0x06 37 /* Left interpolate filter volume control (MSB) */ 38 #define ACCELCODEC_R07 0x07 39 /* Left interpolate filter volume control (LSB) */ 40 #define ACCELCODEC_R08 0x08 41 /* Audio interface control */ 42 #define ACCELCODEC_R09 0x09 43 /* Sample Rate / CLK control */ 44 #define ACCELCODEC_R0A 0x0A 45 /* Decimation filter / Interpolate filter enable */ 46 #define ACCELCODEC_R0B 0x0B 47 /* LIN volume */ 48 #define ACCELCODEC_R0C 0x0C 49 /* LIP volume */ 50 #define ACCELCODEC_R0D 0x0D 51 /* AL volume */ 52 #define ACCELCODEC_R0E 0x0E 53 /* Input volume */ 54 #define ACCELCODEC_R12 0x12 55 /* Left out mix */ 56 #define ACCELCODEC_R13 0x13 57 /* Right out mix */ 58 #define ACCELCODEC_R14 0x14 59 /* LPF out mix / SCF */ 60 #define ACCELCODEC_R15 0x15 61 /* SCF control */ 62 #define ACCELCODEC_R16 0x16 63 /* LOUT (AOL) volume */ 64 #define ACCELCODEC_R17 0x17 65 /* ROUT (AOR) volume */ 66 #define ACCELCODEC_R18 0x18 67 /* MONOOUT (AOM) volume */ 68 #define ACCELCODEC_R19 0x19 69 /* MONOOUT / Reference control */ 70 #define ACCELCODEC_R1A 0x1A 71 /* Bias Current control */ 72 #define ACCELCODEC_R1B 0x1B 73 /* ADC control */ 74 #define ACCELCODEC_R1C 0x1C 75 /* Power Mrg 1 */ 76 #define ACCELCODEC_R1D 0x1D 77 /* Power Mrg 2 */ 78 #define ACCELCODEC_R1E 0x1E 79 /* Power Mrg 3 */ 80 #define ACCELCODEC_R1F 0x1F 81 82 /* ACCELCODEC_R00 */ 83 /* high_pass filter */ 84 #define ASC_HPF_ENABLE (0x1) 85 #define ASC_HPF_DISABLE (0x0) 86 87 #define ASC_DSM_MODE_ENABLE (0x1 << 1) 88 #define ASC_DSM_MODE_DISABLE (0x0 << 1) 89 90 #define ASC_SCRAMBLE_ENABLE (0x1 << 2) 91 #define ASC_SCRAMBLE_DISABLE (0x0 << 2) 92 93 #define ASC_DITHER_ENABLE (0x1 << 3) 94 #define ASC_DITHER_DISABLE (0x0 << 3) 95 96 #define ASC_BCLKDIV_4 (0x1 << 4) 97 #define ASC_BCLKDIV_8 (0x2 << 4) 98 #define ASC_BCLKDIV_16 (0x3 << 4) 99 100 /* ACCECODEC_R04 */ 101 #define ASC_INT_MUTE_L (0x1) 102 #define ASC_INT_ACTIVE_L (0x0) 103 #define ASC_INT_MUTE_R (0x1 << 1) 104 #define ASC_INT_ACTIVE_R (0x0 << 1) 105 106 #define ASC_SIDETONE_L_OFF (0x0 << 2) 107 #define ASC_SIDETONE_L_GAIN_MAX (0x1 << 2) 108 #define ASC_SIDETONE_R_OFF (0x0 << 5) 109 #define ASC_SIDETONE_R_GAIN_MAX (0x1 << 5) 110 111 /* ACCELCODEC_R05 */ 112 #define ASC_INT_VOL_0DB (0x0) 113 114 /* ACCELCODEC_R09 */ 115 #define ASC_DSP_MODE (0x3) 116 #define ASC_I2S_MODE (0x2) 117 #define ASC_LEFT_MODE (0x1) 118 #define ASC_RIGHT_MODE (0x0) 119 120 #define ASC_32BIT_MODE (0x3 << 2) 121 #define ASC_24BIT_MODE (0x2 << 2) 122 #define ASC_20BIT_MODE (0x1 << 2) 123 #define ASC_16BIT_MODE (0x0 << 2) 124 125 #define ASC_INVERT_LRCLK (0x1 << 4) 126 #define ASC_NORMAL_LRCLK (0x0 << 4) 127 128 #define ASC_LRSWAP_ENABLE (0x1 << 5) 129 #define ASC_LRSWAP_DISABLE (0x0 << 5) 130 131 #define ASC_MASTER_MODE (0x1 << 6) 132 #define ASC_SLAVE_MODE (0x0 << 6) 133 134 #define ASC_INVERT_BCLK (0x1 << 7) 135 #define ASC_NORMAL_BCLK (0x0 << 7) 136 137 /* ACCELCODEC_R0A */ 138 #define ASC_USB_MODE (0x1) 139 #define ASC_NORMAL_MODE (0x0) 140 141 #define ASC_CLKDIV2 (0x1 << 6) 142 #define ASC_CLKNODIV (0x0 << 6) 143 144 #define ASC_CLK_ENABLE (0x1 << 7) 145 #define ASC_CLK_DISABLE (0x0 << 7) 146 147 /* ACCELCODEC_R0B */ 148 #define ASC_DEC_ENABLE (0x1) 149 #define ASC_DEC_DISABLE (0x0) 150 #define ASC_INT_ENABLE (0x1 << 1) 151 #define ASC_INT_DISABLE (0x0 << 1) 152 153 #define ASC_INPUT_MUTE (0x1 << 7) 154 #define ASC_INPUT_ACTIVE (0x0 << 7) 155 #define ASC_INPUT_VOL_0DB (0x0) 156 157 /* ACCELCODEC_R12 */ 158 #define ASC_LINE_INPUT (0) 159 #define ASC_MIC_INPUT (1 << 7) 160 161 #define ASC_MIC_BOOST_0DB (0) 162 #define ASC_MIC_BOOST_20DB (1 << 5) 163 164 /* ACCELCODEC_R13 */ 165 #define ASC_LPGAMXVOL_0DB (0x5) 166 /* the left channel PGA output is directly fed into the left mixer */ 167 #define ASC_LPGAMX_ENABLE (0x1 << 3) 168 #define ASC_LPGAMX_DISABLE (0x0 << 3) 169 #define ASC_ALMXVOL_0DB (0x5 << 4) 170 /* the left second line input is directly fed into the left mixer */ 171 #define ASC_ALMX_ENABLE (0x1 << 7) 172 #define ASC_ALMX_DISABLE (0x0 << 7) 173 174 /* ACCELCODEC_R14 */ 175 #define ASC_RPGAMXVOL_0DB (0x5) 176 /* the right channel PGA output is directly fed into the right mixer */ 177 #define ASC_RPGAMX_ENABLE (0x1 << 3) 178 #define ASC_RPGAMX_DISABLE (0x0 << 3) 179 #define ASC_ARMXVOL_0DB (0x5 << 4) 180 /* the right second line input is directly fed into the right mixer */ 181 #define ASC_ARMX_ENABLE (0x1 << 7) 182 #define ASC_ARMX_DISABLE (0x0 << 7) 183 184 /*ACCELCODEC_R15 */ 185 /*the left differential signal from DAC is directly fed into the left mixer*/ 186 #define ASC_LDAMX_ENABLE (0x1 << 2) 187 #define ASC_LDAMX_DISABLE (0x0 << 2) 188 /* the right differential signal --> the right mixer */ 189 #define ASC_RDAMX_ENABLE (0x1 << 3) 190 #define ASC_RDAMX_DISABLE (0x0 << 3) 191 /* the left channel LPF is mute */ 192 #define ASC_LSCF_MUTE (0x1 << 4) 193 #define ASC_LSCF_ACTIVE (0x0 << 4) 194 /* the right channel LPF is mute */ 195 #define ASC_RSCF_MUTE (0x1 << 5) 196 #define ASC_RSCF_ACTIVE (0x0 << 5) 197 /* the left channel LPF output is fed into the left into the mixer */ 198 #define ASC_LLPFMX_ENABLE (0x1 << 6) 199 #define ASC_LLPFMX_DISABLE (0x0 << 6) 200 /* the right channel LPF output is fed into the right into the mixer. */ 201 #define ASC_RLPFMX_ENABLE (0x1 << 7) 202 #define ASC_RLPFMX_DISABLE (0x0 << 7) 203 204 /* ACCELCODEC_R17/R18 */ 205 #define ASC_OUTPUT_MUTE (0x1 << 6) 206 #define ASC_OUTPUT_ACTIVE (0x0 << 6) 207 #define ASC_CROSSZERO_EN (0x1 << 7) 208 #define ASC_OUTPUT_VOL_0DB (0x0F) 209 /* ACCELCODEC_R19 */ 210 #define ASC_MONO_OUTPUT_MUTE (0x1 << 7) 211 #define ASC_MONO_OUTPUT_ACTIVE (0x0 << 7) 212 #define ASC_MONO_CROSSZERO_EN (0x1 << 6) 213 214 /* ACCELCODEC_R1A */ 215 #define ASC_VMDSCL_SLOWEST (0x0 << 2) 216 #define ASC_VMDSCL_SLOW (0x1 << 2) 217 #define ASC_VMDSCL_FAST (0x2 << 2) 218 #define ASC_VMDSCL_FASTEST (0x3 << 2) 219 220 #define ASC_MICBIAS_09 (0x1 << 4) 221 #define ASC_MICBIAS_06 (0x0 << 4) 222 223 /* the right channel LPF output is fed to mono PA */ 224 #define ASC_L2M_ENABLE (0x1 << 5) 225 #define ASC_L2M_DISABLE (0x0 << 5) 226 /* the left channel LPF output is fed to mono PA */ 227 #define ASC_R2M_ENABLE (0x1 << 6) 228 #define ASC_R2M_DISABLE (0x0 << 6) 229 /* the capless connection is enable */ 230 #define ASC_CAPLESS_ENABLE (0x1 << 7) 231 #define ASC_CAPLESS_DISABLE (0x0 << 7) 232 233 /* ACCELCODEC_R1C */ 234 /* the amplitude setting of the ASDM dither(div=vdd/48) */ 235 #define ASC_DITH_0_DIV (0x0 << 3) 236 #define ASC_DITH_2_DIV (0x1 << 3) 237 #define ASC_DITH_4_DIV (0x2 << 3) 238 #define ASC_DITH_8_DIV (0x3 << 3) 239 240 /* the ASDM dither is enabled */ 241 #define ASC_DITH_ENABLE (0x1 << 5) 242 #define ASC_DITH_DISABLE (0x0 << 5) 243 244 /* the ASDM DEM is enabled */ 245 #define ASC_DEM_ENABLE (0x1 << 7) 246 #define ASC_DEM_DISABLE (0x0 << 7) 247 248 /* ACCELCODEC_R1D */ 249 /* the VMID reference is powered down. VMID is connected to GND */ 250 #define ASC_PDVMID_ENABLE (0x1) 251 #define ASC_PDVMID_DISABLE (0x0) 252 /* the PGA S2D buffer is power down */ 253 #define ASC_PDSDL_ENABLE (0x1 << 2) 254 #define ASC_PDSDL_DISABLE (0x0 << 2) 255 /* the micphone input Op-Amp is power down */ 256 #define ASC_PDBSTL_ENABLE (0x1 << 4) 257 #define ASC_PDBSTL_DISABLE (0x0 << 4) 258 /* the PGA is power down */ 259 #define ASC_PDPGAL_ENABLE (0x1 << 6) 260 #define ASC_PDPGAL_DISABLE (0x0 << 6) 261 /* reference generator is power down */ 262 #define ASC_PDREF_ENABLE (0x1 << 7) 263 #define ASC_PDREF_DISABLE (0x0 << 7) 264 265 /* ACCELCODEC_R1E */ 266 /* the right channel PA is power down */ 267 #define ASC_PDPAR_ENABLE (0x1) 268 #define ASC_PDPAR_DISABLE (0x0) 269 /* the left channel power amplifier is power down */ 270 #define ASC_PDPAL_ENABLE (0x1 << 1) 271 #define ASC_PDPAL_DISABLE (0x0 << 1) 272 /* the right mixer is power down */ 273 #define ASC_PDMIXR_ENABLE (0x1 << 2) 274 #define ASC_PDMIXR_DISABLE (0x0 << 2) 275 /* the left mixer is power down */ 276 #define ASC_PDMIXL_ENABLE (0x1 << 3) 277 #define ASC_PDMIXL_DISABLE (0x0 << 3) 278 /* the right RC LPF is power down */ 279 #define ASC_PDLPFR_ENABLE (0x1 << 4) 280 #define ASC_PDLPFR_DISABLE (0x0 << 4) 281 /* the left channel RC LPF is power down */ 282 #define ASC_PDLPFL_ENABLE (0x1 << 5) 283 #define ASC_PDLPFL_DISABLE (0x0 << 5) 284 /* the ASDM is power down */ 285 #define ASC_PDASDML_ENABLE (0x1 << 7) 286 #define ASC_PDASDML_DISABLE (0x0 << 7) 287 288 /* ACCELCODEC_R1F */ 289 /* the right channel DAC is power down */ 290 #define ASC_PDSCFR_ENABLE (0x1 << 1) 291 #define ASC_PDSCFR_DISABLE (0x0 << 1) 292 /* the left channel DAC is power down */ 293 #define ASC_PDSCFL_ENABLE (0x1 << 2) 294 #define ASC_PDSCFL_DISABLE (0x0 << 2) 295 /* the micbias is power down */ 296 #define ASC_PDMICB_ENABLE (0x1 << 4) 297 #define ASC_PDMICB_DISABLE (0x0 << 4) 298 /* the left channel LPF is power down */ 299 #define ASC_PDIB_ENABLE (0x1 << 5) 300 #define ASC_PDIB_DISABLE (0x0 << 5) 301 /* the mon mixer is power down */ 302 #define ASC_PDMIXM_ENABLE (0x1 << 6) 303 #define ASC_PDMIXM_DISABLE (0x0 << 6) 304 /* the mono PA is power down. */ 305 #define ASC_PDPAM_ENABLE (0x1 << 7) 306 #define ASC_PDPAM_DISABLE (0x0 << 7) 307 308 /* left and right PA gain */ 309 #define LINE_2_MIXER_GAIN (0x5) 310 #define RK1000_CODEC_NUM_REG 0x20 311 312 #define GPIO_HIGH 1 313 #define GPIO_LOW 0 314 315 /* rk1000 ctl register */ 316 #define CODEC_CON 0x01 317 #define CODEC_ON 0X00 318 #define CODEC_OFF 0x0d 319 320 #endif 321