1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/board/common/rotpk/rotpk_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 25 26 #define ARM_SYSTEM_COUNT U(1) 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 38 39 /* 40 * Macros for local power states in ARM platforms encoded by State-ID field 41 * within the power-state parameter. 42 */ 43 /* Local power state for power domains in Run state. */ 44 #define ARM_LOCAL_STATE_RUN U(0) 45 /* Local power state for retention. Valid only for CPU power domains */ 46 #define ARM_LOCAL_STATE_RET U(1) 47 /* Local power state for OFF/power-down. Valid for CPU and cluster power 48 domains */ 49 #define ARM_LOCAL_STATE_OFF U(2) 50 51 /* Memory location options for TSP */ 52 #define ARM_TRUSTED_SRAM_ID 0 53 #define ARM_TRUSTED_DRAM_ID 1 54 #define ARM_DRAM_ID 2 55 56 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 57 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 58 #else 59 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 60 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 61 62 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 63 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 64 65 #if ENABLE_FEAT_RME 66 /* Store level 0 GPT at the top of the Trusted SRAM */ 67 #define ARM_L0_GPT_BASE (ARM_TRUSTED_SRAM_BASE + \ 68 PLAT_ARM_TRUSTED_SRAM_SIZE - \ 69 ARM_L0_GPT_SIZE) 70 #define ARM_L0_GPT_SIZE UL(0x00002000) /* 8 KB */ 71 #else 72 #define ARM_L0_GPT_SIZE UL(0) 73 #endif 74 75 /* The remaining Trusted SRAM is used to load the BL images */ 76 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 77 ARM_SHARED_RAM_SIZE) 78 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 79 ARM_SHARED_RAM_SIZE - \ 80 ARM_L0_GPT_SIZE) 81 82 /* 83 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 84 * follows: 85 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 86 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 87 * - REALM DRAM: Reserved for Realm world if RME is enabled 88 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 89 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 90 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 91 * 92 * TODO: update this layout 93 * 94 * RME enabled(64MB) RME not enabled(16MB) 95 * -------------------- ------------------- 96 * | | | | 97 * | AP TZC (~28MB) | | AP TZC (~14MB) | 98 * -------------------- ------------------- 99 * | Event Log | | Event Log | 100 * | (4KB) | | (4KB) | 101 * -------------------- ------------------- 102 * | REALM (RMM) | | | 103 * | (32MB - 4KB) | | EL3 TZC (2MB) | 104 * -------------------- ------------------- 105 * | | | | 106 * | TF-A <-> RMM | | SCP TZC | 107 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 108 * -------------------- 109 * | | 110 * | EL3 TZC (3MB) | 111 * -------------------- 112 * | L1 GPT + SCP TZC | 113 * | (~1MB) | 114 * 0xFFFF_FFFF -------------------- 115 */ 116 #if ENABLE_FEAT_RME 117 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 118 /* 119 * Define a region within the TZC secured DRAM for use by EL3 runtime 120 * firmware. This region is meant to be NOLOAD and will not be zero 121 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 122 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 123 */ 124 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 125 /* 8 x 128KB L1 pages (L0GPTSZ = 1GB, PGS = 4KB) */ 126 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 127 128 #else /* !ENABLE_FEAT_RME */ 129 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 130 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 131 #define ARM_L1_GPT_SIZE UL(0) 132 #endif /* ENABLE_FEAT_RME */ 133 134 #if ENABLE_RMM 135 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 136 #define ARM_REALM_SIZE (UL(0x02000000) - \ 137 ARM_EL3_RMM_SHARED_SIZE) 138 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 139 #else /* !ENABLE_RMM */ 140 #define ARM_REALM_SIZE UL(0) 141 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 142 #endif /* ENABLE_RMM */ 143 144 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 145 ARM_DRAM1_SIZE - \ 146 (ARM_SCP_TZC_DRAM1_SIZE + \ 147 ARM_L1_GPT_SIZE)) 148 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 149 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 150 ARM_SCP_TZC_DRAM1_SIZE - 1U) 151 152 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 153 MEASURED_BOOT 154 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 155 156 #if ENABLE_RMM 157 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 158 ARM_EVENT_LOG_DRAM1_SIZE) 159 #else 160 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 161 ARM_EVENT_LOG_DRAM1_SIZE) 162 #endif /* ENABLE_RMM */ 163 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 164 ARM_EVENT_LOG_DRAM1_SIZE - \ 165 1U) 166 #else 167 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 168 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 169 170 #if ENABLE_FEAT_RME 171 #define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ 172 ARM_DRAM1_SIZE - \ 173 ARM_L1_GPT_SIZE) 174 #define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ 175 ARM_L1_GPT_SIZE - 1U) 176 177 #if ENABLE_RMM 178 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 179 ARM_REALM_SIZE) 180 181 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 182 183 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 184 ARM_DRAM1_SIZE - \ 185 (ARM_SCP_TZC_DRAM1_SIZE + \ 186 ARM_L1_GPT_SIZE + \ 187 ARM_EL3_RMM_SHARED_SIZE + \ 188 ARM_EL3_TZC_DRAM1_SIZE)) 189 190 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 191 ARM_EL3_RMM_SHARED_SIZE - 1U) 192 #endif /* ENABLE_RMM */ 193 #endif /* ENABLE_FEAT_RME */ 194 195 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 196 ARM_EL3_TZC_DRAM1_SIZE) 197 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 198 ARM_EL3_TZC_DRAM1_SIZE - 1U) 199 200 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 201 ARM_DRAM1_SIZE - \ 202 ARM_TZC_DRAM1_SIZE) 203 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 204 (ARM_SCP_TZC_DRAM1_SIZE + \ 205 ARM_EL3_TZC_DRAM1_SIZE + \ 206 ARM_EL3_RMM_SHARED_SIZE + \ 207 ARM_REALM_SIZE + \ 208 ARM_L1_GPT_SIZE + \ 209 ARM_EVENT_LOG_DRAM1_SIZE)) 210 211 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 212 ARM_AP_TZC_DRAM1_SIZE - 1U) 213 214 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 215 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 216 217 #ifdef SPD_opteed 218 /* 219 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 220 * load/authenticate the trusted os extra image. The first 512KB of 221 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 222 * for OPTEE is paged image which only include the paging part using 223 * virtual memory but without "init" data. OPTEE will copy the "init" data 224 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 225 * extra image behind the "init" data. 226 */ 227 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 228 ARM_AP_TZC_DRAM1_SIZE - \ 229 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 230 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 231 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 232 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 233 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 234 MT_MEMORY | MT_RW | MT_SECURE) 235 236 /* 237 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 238 * support is enabled). 239 */ 240 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 241 BL32_BASE, \ 242 BL32_LIMIT - BL32_BASE, \ 243 MT_MEMORY | MT_RW | MT_SECURE) 244 #endif /* SPD_opteed */ 245 246 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 247 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 248 ARM_TZC_DRAM1_SIZE) 249 250 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 251 ARM_NS_DRAM1_SIZE - 1U) 252 #ifdef PLAT_ARM_DRAM1_BASE 253 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 254 #else 255 #define ARM_DRAM1_BASE ULL(0x80000000) 256 #endif /* PLAT_ARM_DRAM1_BASE */ 257 258 #define ARM_DRAM1_SIZE ULL(0x80000000) 259 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 260 ARM_DRAM1_SIZE - 1U) 261 262 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 263 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 264 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 265 ARM_DRAM2_SIZE - 1U) 266 /* Number of DRAM banks */ 267 #define ARM_DRAM_NUM_BANKS 2UL 268 269 /* Number of PCIe memory regions */ 270 #define ARM_PCI_NUM_REGIONS 2UL 271 272 #define ARM_IRQ_SEC_PHY_TIMER 29 273 274 #define ARM_IRQ_SEC_SGI_0 8 275 #define ARM_IRQ_SEC_SGI_1 9 276 #define ARM_IRQ_SEC_SGI_2 10 277 #define ARM_IRQ_SEC_SGI_3 11 278 #define ARM_IRQ_SEC_SGI_4 12 279 #define ARM_IRQ_SEC_SGI_5 13 280 #define ARM_IRQ_SEC_SGI_6 14 281 #define ARM_IRQ_SEC_SGI_7 15 282 283 /* 284 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 285 * terminology. On a GICv2 system or mode, the lists will be merged and treated 286 * as Group 0 interrupts. 287 */ 288 #define ARM_G1S_IRQ_PROPS(grp) \ 289 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 290 GIC_INTR_CFG_LEVEL), \ 291 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 292 GIC_INTR_CFG_EDGE), \ 293 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 294 GIC_INTR_CFG_EDGE), \ 295 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 296 GIC_INTR_CFG_EDGE), \ 297 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 298 GIC_INTR_CFG_EDGE), \ 299 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 300 GIC_INTR_CFG_EDGE), \ 301 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 302 GIC_INTR_CFG_EDGE) 303 304 #define ARM_G0_IRQ_PROPS(grp) \ 305 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 306 GIC_INTR_CFG_EDGE), \ 307 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 308 GIC_INTR_CFG_EDGE) 309 310 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 311 ARM_SHARED_RAM_BASE, \ 312 ARM_SHARED_RAM_SIZE, \ 313 MT_DEVICE | MT_RW | EL3_PAS) 314 315 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 316 ARM_NS_DRAM1_BASE, \ 317 ARM_NS_DRAM1_SIZE, \ 318 MT_MEMORY | MT_RW | MT_NS) 319 320 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 321 ARM_DRAM2_BASE, \ 322 ARM_DRAM2_SIZE, \ 323 MT_MEMORY | MT_RW | MT_NS) 324 325 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 326 TSP_SEC_MEM_BASE, \ 327 TSP_SEC_MEM_SIZE, \ 328 MT_MEMORY | MT_RW | MT_SECURE) 329 330 #if ARM_BL31_IN_DRAM 331 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 332 BL31_BASE, \ 333 PLAT_ARM_MAX_BL31_SIZE, \ 334 MT_MEMORY | MT_RW | EL3_PAS) 335 #endif 336 337 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 338 ARM_EL3_TZC_DRAM1_BASE, \ 339 ARM_EL3_TZC_DRAM1_SIZE, \ 340 MT_MEMORY | MT_RW | EL3_PAS) 341 342 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 343 PLAT_ARM_TRUSTED_DRAM_BASE, \ 344 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 345 MT_MEMORY | MT_RW | MT_SECURE) 346 347 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 348 MEASURED_BOOT 349 #define ARM_MAP_EVENT_LOG_DRAM1 \ 350 MAP_REGION_FLAT( \ 351 ARM_EVENT_LOG_DRAM1_BASE, \ 352 ARM_EVENT_LOG_DRAM1_SIZE, \ 353 MT_MEMORY | MT_RW | MT_SECURE) 354 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 355 356 #if ENABLE_FEAT_RME 357 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 358 ARM_L1_GPT_BASE, \ 359 ARM_L1_GPT_SIZE, \ 360 MT_MEMORY | MT_RW | EL3_PAS) 361 #endif 362 363 #if ENABLE_RMM 364 /* 365 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 366 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 367 */ 368 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 369 PLAT_ARM_RMM_BASE, \ 370 (PLAT_ARM_RMM_SIZE + \ 371 ARM_EL3_RMM_SHARED_SIZE), \ 372 MT_MEMORY | MT_RW | MT_REALM) 373 374 375 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 376 MAP_REGION_FLAT( \ 377 ARM_EL3_RMM_SHARED_BASE, \ 378 ARM_EL3_RMM_SHARED_SIZE, \ 379 MT_MEMORY | MT_RW | MT_REALM) 380 #endif /* ENABLE_RMM */ 381 382 /* 383 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 384 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 385 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 386 * to be able to access the heap. 387 */ 388 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 389 BL1_RW_BASE, \ 390 BL1_RW_LIMIT - BL1_RW_BASE, \ 391 MT_MEMORY | MT_RW | EL3_PAS) 392 393 /* 394 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 395 * otherwise one region is defined containing both. 396 */ 397 #if SEPARATE_CODE_AND_RODATA 398 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 399 BL_CODE_BASE, \ 400 BL_CODE_END - BL_CODE_BASE, \ 401 MT_CODE | EL3_PAS), \ 402 MAP_REGION_FLAT( \ 403 BL_RO_DATA_BASE, \ 404 BL_RO_DATA_END \ 405 - BL_RO_DATA_BASE, \ 406 MT_RO_DATA | EL3_PAS) 407 #else 408 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 409 BL_CODE_BASE, \ 410 BL_CODE_END - BL_CODE_BASE, \ 411 MT_CODE | EL3_PAS) 412 #endif 413 #if USE_COHERENT_MEM 414 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 415 BL_COHERENT_RAM_BASE, \ 416 BL_COHERENT_RAM_END \ 417 - BL_COHERENT_RAM_BASE, \ 418 MT_DEVICE | MT_RW | EL3_PAS) 419 #endif 420 #if USE_ROMLIB 421 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 422 ROMLIB_RO_BASE, \ 423 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 424 MT_CODE | EL3_PAS) 425 426 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 427 ROMLIB_RW_BASE, \ 428 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 429 MT_MEMORY | MT_RW | EL3_PAS) 430 #endif 431 432 /* 433 * Map mem_protect flash region with read and write permissions 434 */ 435 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 436 V2M_FLASH_BLOCK_SIZE, \ 437 MT_DEVICE | MT_RW | MT_SECURE) 438 439 #if !TRANSFER_LIST 440 /* 441 * Map the region for device tree configuration with read and write permissions 442 */ 443 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 444 (ARM_FW_CONFIGS_LIMIT \ 445 - ARM_BL_RAM_BASE), \ 446 MT_MEMORY | MT_RW | EL3_PAS) 447 #endif 448 449 /* 450 * Map L0_GPT with read and write permissions 451 */ 452 #if ENABLE_FEAT_RME 453 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \ 454 ARM_L0_GPT_SIZE, \ 455 MT_MEMORY | MT_RW | MT_ROOT) 456 #endif 457 458 /* 459 * The max number of regions like RO(code), coherent and data required by 460 * different BL stages which need to be mapped in the MMU. 461 */ 462 #define ARM_BL_REGIONS 7 463 464 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 465 ARM_BL_REGIONS) 466 467 /* Memory mapped Generic timer interfaces */ 468 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 469 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 470 #else 471 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 472 #endif 473 474 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 475 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 476 #else 477 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 478 #endif 479 480 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 481 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 482 #else 483 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 484 #endif 485 486 #ifdef PLAT_ARM_SYS_CNT_BASE_S 487 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 488 #else 489 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 490 #endif 491 492 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 493 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 494 #else 495 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 496 #endif 497 498 #define ARM_CONSOLE_BAUDRATE 115200 499 500 /* Trusted Watchdog constants */ 501 #ifdef PLAT_ARM_SP805_TWDG_BASE 502 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 503 #else 504 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 505 #endif 506 #define ARM_SP805_TWDG_CLK_HZ 32768 507 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 508 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 509 #define ARM_TWDG_TIMEOUT_SEC 128 510 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 511 ARM_TWDG_TIMEOUT_SEC) 512 513 /****************************************************************************** 514 * Required platform porting definitions common to all ARM standard platforms 515 *****************************************************************************/ 516 517 /* 518 * This macro defines the deepest retention state possible. A higher state 519 * id will represent an invalid or a power down state. 520 */ 521 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 522 523 /* 524 * This macro defines the deepest power down states possible. Any state ID 525 * higher than this is invalid. 526 */ 527 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 528 529 /* 530 * Some data must be aligned on the biggest cache line size in the platform. 531 * This is known only to the platform as it might have a combination of 532 * integrated and external caches. 533 */ 534 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 535 536 /* Define memory configuration for trusted boot device tree files. */ 537 #ifdef PLAT_ARM_TB_FW_CONFIG_SIZE 538 #define ARM_TB_FW_CONFIG_MAX_SIZE PLAT_ARM_TB_FW_CONFIG_SIZE 539 #else 540 #define ARM_TB_FW_CONFIG_MAX_SIZE U(0x400) 541 #endif 542 543 #if !TRANSFER_LIST 544 /* 545 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 546 * and limit. Leave enough space of BL2 meminfo. 547 */ 548 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 549 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 550 + (PAGE_SIZE / 2U)) 551 #define ARM_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - \ 552 ARM_FW_CONFIG_BASE) 553 554 /* 555 * Boot parameters passed from BL2 to BL31/BL32 are stored here 556 */ 557 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 558 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 559 + (PAGE_SIZE / 2U)) 560 561 /* 562 * Define limit of firmware configuration memory: 563 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 564 */ 565 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 566 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 567 #endif 568 569 /******************************************************************************* 570 * BL1 specific defines. 571 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 572 * addresses. 573 ******************************************************************************/ 574 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 575 #ifdef PLAT_BL1_RO_LIMIT 576 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 577 #else 578 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 579 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 580 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 581 #endif 582 583 /* 584 * With ENABLE_RMM=1 put BL1 RW below L0 GPT, 585 * or at the top of Trusted SRAM otherwise. 586 */ 587 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 588 ARM_BL_RAM_SIZE - \ 589 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 590 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 591 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 592 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 593 594 #define ROMLIB_RO_BASE BL1_RO_LIMIT 595 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 596 597 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 598 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 599 600 /******************************************************************************* 601 * BL2 specific defines. 602 ******************************************************************************/ 603 #if RESET_TO_BL2 604 #if ENABLE_PIE 605 /* 606 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 607 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 608 */ 609 #define BL2_OFFSET (0x5000) 610 #else 611 /* Put BL2 towards the middle of the Trusted SRAM */ 612 #define BL2_OFFSET (0x2000) 613 #endif /* ENABLE_PIE */ 614 615 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 616 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 617 BL2_OFFSET) 618 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 619 620 #else 621 /* 622 * Put BL2 just below BL1. 623 */ 624 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 625 #define BL2_LIMIT BL1_RW_BASE 626 #endif 627 628 /******************************************************************************* 629 * BL31 specific defines. 630 ******************************************************************************/ 631 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 632 /* 633 * Put BL31 at the bottom of TZC secured DRAM 634 */ 635 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 636 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 637 PLAT_ARM_MAX_BL31_SIZE) 638 /* 639 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 640 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 641 */ 642 #if SEPARATE_NOBITS_REGION 643 #define BL31_NOBITS_BASE BL2_BASE 644 #define BL31_NOBITS_LIMIT BL2_LIMIT 645 #endif /* SEPARATE_NOBITS_REGION */ 646 #elif (RESET_TO_BL31) 647 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 648 # if !ENABLE_PIE 649 # error "BL31 must be a PIE if RESET_TO_BL31=1." 650 #endif 651 /* 652 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 653 * used for building BL31 and not used for loading BL31. 654 */ 655 # define BL31_BASE 0x0 656 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 657 #else 658 /* Put BL31 below BL2 in the Trusted SRAM.*/ 659 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 660 - PLAT_ARM_MAX_BL31_SIZE) 661 #define BL31_PROGBITS_LIMIT BL2_BASE 662 /* 663 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 664 * This is because in the RESET_TO_BL2 configuration, 665 * BL2 is always resident. 666 */ 667 #if RESET_TO_BL2 668 #define BL31_LIMIT BL2_BASE 669 #else 670 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 671 #endif 672 #endif 673 674 /****************************************************************************** 675 * RMM specific defines 676 *****************************************************************************/ 677 #if ENABLE_RMM 678 #define RMM_BASE (ARM_REALM_BASE) 679 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 680 #define RMM_PAYLOAD_LIMIT (RMM_BASE + PLAT_ARM_RMM_PAYLOAD_SIZE) 681 #define RMM_BANK_SIZE (PLAT_ARM_RMM_PAYLOAD_SIZE / 2U) 682 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 683 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 684 #endif 685 686 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 687 /******************************************************************************* 688 * BL32 specific defines for EL3 runtime in AArch32 mode 689 ******************************************************************************/ 690 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 691 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 692 # if !ENABLE_PIE 693 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 694 #endif 695 /* 696 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 697 * used for building BL32 and not used for loading BL32. 698 */ 699 # define BL32_BASE 0x0 700 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 701 # else 702 /* Put BL32 below BL2 in the Trusted SRAM.*/ 703 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 704 - PLAT_ARM_MAX_BL32_SIZE) 705 # define BL32_PROGBITS_LIMIT BL2_BASE 706 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 707 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 708 709 #else 710 /******************************************************************************* 711 * BL32 specific defines for EL3 runtime in AArch64 mode 712 ******************************************************************************/ 713 /* 714 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 715 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 716 * controller. 717 */ 718 # if SPM_MM || SPMC_AT_EL3 719 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 720 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 721 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 722 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 723 ARM_AP_TZC_DRAM1_SIZE) 724 # elif defined(SPD_spmd) 725 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 726 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 727 # define BL32_BASE PLAT_ARM_SPMC_BASE 728 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 729 PLAT_ARM_SPMC_SIZE) 730 # elif ARM_BL31_IN_DRAM 731 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 732 PLAT_ARM_MAX_BL31_SIZE) 733 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 734 PLAT_ARM_MAX_BL31_SIZE) 735 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 736 PLAT_ARM_MAX_BL31_SIZE) 737 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 738 ARM_AP_TZC_DRAM1_SIZE) 739 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 740 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 741 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 742 # define TSP_PROGBITS_LIMIT BL31_BASE 743 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 744 # define BL32_LIMIT BL31_BASE 745 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 746 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 747 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 748 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 749 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 750 + SZ_4M) 751 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 752 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 753 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 754 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 755 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 756 ARM_AP_TZC_DRAM1_SIZE) 757 # else 758 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 759 # endif 760 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 761 762 /* 763 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 764 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 765 * used as BL32. 766 */ 767 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 768 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 769 # undef BL32_BASE 770 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 771 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 772 773 #if RESET_TO_BL31 && defined(SPD_spmd) && defined(PLAT_ARM_SPMC_MANIFEST_BASE) 774 #define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE 775 #else 776 777 /* 778 * SPM expects SPM Core manifest base address in x0, which in !RESET_TO_BL31 779 * case loaded after base of non shared SRAM(after 4KB offset of SRAM). But in 780 * RESET_TO_BL31 case all non shared SRAM is allocated to BL31, so to avoid 781 * overwriting of manifest keep it in the last page. 782 */ 783 #define ARM_SPMC_MANIFEST_BASE (ARM_TRUSTED_SRAM_BASE + \ 784 PLAT_ARM_TRUSTED_SRAM_SIZE -\ 785 PAGE_SIZE) 786 #endif 787 788 /******************************************************************************* 789 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 790 ******************************************************************************/ 791 #define BL2U_BASE BL2_BASE 792 #define BL2U_LIMIT BL2_LIMIT 793 794 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 795 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 796 797 /* 798 * ID of the secure physical generic timer interrupt used by the TSP. 799 */ 800 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 801 802 803 /* 804 * One cache line needed for bakery locks on ARM platforms 805 */ 806 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 807 808 /* Priority levels for ARM platforms */ 809 #if ENABLE_FEAT_RAS && FFH_SUPPORT 810 #define PLAT_RAS_PRI 0x10 811 #endif 812 #define PLAT_SDEI_CRITICAL_PRI 0x60 813 #define PLAT_SDEI_NORMAL_PRI 0x70 814 815 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 816 #define PLAT_CORE_FAULT_IRQ 17 817 818 /* ARM platforms use 3 upper bits of secure interrupt priority */ 819 #define PLAT_PRI_BITS 3 820 821 /* SGI used for SDEI signalling */ 822 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 823 824 #if SDEI_IN_FCONF 825 /* ARM SDEI dynamic private event max count */ 826 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 827 828 /* ARM SDEI dynamic shared event max count */ 829 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 830 #else 831 /* ARM SDEI dynamic private event numbers */ 832 #define ARM_SDEI_DP_EVENT_0 1000 833 #define ARM_SDEI_DP_EVENT_1 1001 834 #define ARM_SDEI_DP_EVENT_2 1002 835 836 /* ARM SDEI dynamic shared event numbers */ 837 #define ARM_SDEI_DS_EVENT_0 2000 838 #define ARM_SDEI_DS_EVENT_1 2001 839 #define ARM_SDEI_DS_EVENT_2 2002 840 841 #define ARM_SDEI_PRIVATE_EVENTS \ 842 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 843 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 844 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 845 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 846 847 #define ARM_SDEI_SHARED_EVENTS \ 848 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 849 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 850 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 851 #endif /* SDEI_IN_FCONF */ 852 853 #endif /* ARM_DEF_H */ 854