1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_POWER_H 8 #define APUSYS_POWER_H 9 10 #include <platform_def.h> 11 12 #define CFG_APU_ARDCM_ENABLE (0) 13 #define CFG_CTL_RPC_BY_CE (1) 14 15 #define APUPLL0_DEFAULT_FREQ (800) 16 #define APUPLL1_DEFAULT_FREQ (960) 17 #define APUPLL2_DEFAULT_FREQ (1200) 18 #define APUPLL3_DEFAULT_FREQ (1230) 19 20 enum t_acx_id { 21 D_ACX0 = 0, 22 ACX0, 23 ACX1, 24 ACX2, 25 CLUSTER_NUM, 26 RCX, 27 }; 28 29 enum rcx_ao_range { 30 RCX_AO_BEGIN = 0, 31 PLL_ENTRY_BEGIN = 0, 32 PLL_ENTRY_END = 27, 33 ACC_ENTRY_BEGIN = 28, 34 ACC_ENTRY_END = 37, 35 RCX_AO_END = 37, 36 }; 37 38 #define SYS_VLP (0x000000) 39 #define SYS_SPM (0x000000) 40 #define APU_RCX (0x020000) 41 #define APU_RCX_DLA (0x040000) 42 #define APU_ARE (0x0a0000) 43 #define APU_ARE_REG (0x0b0000) 44 #define APU_VCORE (0x0e0000) 45 #define APU_MD32_MBOX (0x0e1000) 46 #define APU_RPC (0x0f0000) 47 #define APU_PCU (0x0f1000) 48 #define APU_AO_CTL (0x0f2000) 49 #define APU_ACC (0x0f3000) 50 #define APU_PLL (0x0f6000) 51 #define APU_RPCTOP_MDLA (0x0F7400) 52 #define APU_ACX0 (0x100000) 53 #define APU_ACX0_RPC_LITE (0x140000) 54 #define APU_ACX1 (0x200000) 55 #define APU_ACX1_RPC_LITE (0x240000) 56 #define APU_ACX2 (0x300000) 57 #define APU_ACX2_RPC_LITE (0x340000) 58 59 /* APU GRP offset define */ 60 #define APU_GRP_0_BASE (0x0000) 61 #define APU_GRP_1_BASE (0x0400) 62 #define APU_GRP_2_BASE (0x0800) 63 #define APU_GRP_3_BASE (0x0C00) 64 65 #define MDLA_PLL_BASE APU_GRP_0_BASE 66 #define MVPU_PLL_BASE APU_GRP_1_BASE 67 #define MNOC_PLL_BASE APU_GRP_2_BASE 68 #define UP_PLL_BASE APU_GRP_3_BASE 69 70 #define MDLA_ACC_BASE APU_GRP_0_BASE 71 #define MVPU_ACC_BASE APU_GRP_1_BASE 72 #define MNOC_ACC_BASE APU_GRP_2_BASE 73 #define UP_ACC_BASE APU_GRP_3_BASE 74 75 /* RPC / RPC_LITE control */ 76 #define APU_RPC_SW_TYPE0_OFF (0x200) 77 #define APU_RPC_SW_TYPE1_OFF (0x204) 78 #define APU_RPC_SW_TYPE2_OFF (0x208) 79 #define APU_RPC_SW_TYPE3_OFF (0x20C) 80 #define APU_RPC_SW_TYPE4_OFF (0x210) 81 #define SW_TYPE_MVPU_MDLA_RV BIT(0) 82 #define CE_ENABLE BIT(10) 83 #define BUCK_PROT_SEL BIT(20) 84 #define RPC_TYPE_INIT_VAL (0x18) 85 #define TOP_SEL_VAL (0xB2) 86 #define RPC_TOP_SEL_VAL (0xB800D50F) 87 88 #define APUSYS_AO_CTL (APUSYS_BASE + APU_AO_CTL) 89 #define APUSYS_RPC (APUSYS_BASE + APU_RPC) 90 #define APUSYS_ACC (APUSYS_BASE + APU_ACC) 91 #define APUSYS_PLL (APUSYS_BASE + APU_PLL) 92 #define APUSYS_PCU (APUSYS_BASE + APU_PCU) 93 94 /* ARE control */ 95 #define ARE_VCORE_EN BIT(20) 96 #define ARE_RCX_AO_EN BIT(21) 97 #define ARE_VCORE_OFF (20) 98 #define ARE_CONF_START (0x04) 99 #define ARE_CONF_END (0x6C) 100 #define ARE_REG_SIZE (4) 101 102 /* ACC offset */ 103 #define APU_ACC_CONFG_SET0 (0x000) 104 #define APU_ACC_CONFG_CLR0 (0x010) 105 #define APU_ACC_AUTO_CTRL_SET0 (0x084) 106 #define APU_ARDCM_CTRL0 (0x100) 107 #define APU_ARDCM_CTRL1 (0x104) 108 109 /* ACC control */ 110 #define APU_ARDCM_CTRL0_VAL_0 (0x00000016) 111 #define APU_ARDCM_CTRL0_VAL_1 (0x00000036) 112 #define APU_ARDCM_CTRL1_VAL_0 (0x00001006) 113 #define APU_ARDCM_CTRL1_VAL_1 (0x07F0F006) 114 #define CGEN_SOC BIT(2) 115 #define CLK_REQ_SW_EN BIT(8) 116 #define HW_CTRL_EN BIT(15) 117 118 /* APU PLL1C offset */ 119 #define RG_PLLGP_LVR_REFSEL (0x204) 120 #define PLL1C_PLL1_CON1 (0x20C) 121 #define PLL1CPLL_FHCTL_HP_EN (0x300) 122 #define PLL1CPLL_FHCTL_CLK_CON (0x308) 123 #define PLL1CPLL_FHCTL_RST_CON (0x30C) 124 #define PLL1CPLL_FHCTL0_CFG (0x314) 125 #define PLL1CPLL_FHCTL0_DDS (0x31C) 126 127 /* PLL control */ 128 #define RG_PLLGP_LVR_REFSEL_VAL (0x3) 129 #define FHCTL_CTRL (0x1) 130 #define FHCTL_NO_RESET (0x1) 131 #define FHCTL_CLKEN (0x1) 132 #define FHCTL_HOPPING_EN BIT(0) 133 #define FHCTL_SFSTR0_EN BIT(2) 134 #define RG_PLL_SDM_PCW_CHG_OFF (31) 135 #define RG_PLL_POSDIV_OFF (24) 136 #define FHCTL0_PLL_TGL_ORG (31) 137 138 /* RPC offset define */ 139 #define APU_RPC_TOP_SEL (0x0004) 140 #define APU_RPC_TOP_SEL_1 (0x0018) 141 #define APU_RPC_HW_CON (0x001C) 142 #define APU_RPC_STATUS_1 (0x0034) 143 #define APU_RPC_INTF_PWR_RDY (0x0044) 144 145 /* RPC control */ 146 #define SRAM_AOC_LHENB_SET BIT(4) 147 #define SRAM_AOC_ISO_SET BIT(6) 148 #define SRAM_AOC_ISO_CLR BIT(7) 149 #define PLL_AOC_ISO_EN_SET BIT(8) 150 #define PLL_AOC_ISO_EN_CLR BIT(9) 151 #define BUCK_ELS_EN_SET BIT(10) 152 #define BUCK_ELS_EN_CLR BIT(11) 153 #define BUCK_AO_RST_B_SET BIT(12) 154 #define BUCK_AO_RST_B_CLR BIT(13) 155 #define BUCK_PROT_REQ_SET BIT(14) 156 #define BUCK_PROT_REQ_CLR BIT(15) 157 158 /* mt6373_vbuck2 */ 159 #define MT6373_SLAVE_ID (0x5) 160 #define MT6373_RG_BUCK_VBUCK2_SET (0x241) 161 #define MT6373_RG_BUCK_VBUCK2_CLR (0x242) 162 #define MT6373_RG_BUCK_VBUCK2_EN_SHIFT (2) 163 #define MT6373_RG_BUCK_VBUCK2_VOSEL_ADDR (0x24e) 164 165 /* PCU initial data */ 166 #define APU_PCUTOP_CTRL_SET (0x0) 167 #define APU_PCU_BUCK_STEP_SEL (0x0030) 168 #define APU_PCU_BUCK_ON_DAT0_L (0x0080) 169 #define APU_PCU_BUCK_ON_DAT0_H (0x0084) 170 #define APU_PCU_BUCK_ON_DAT1_L (0x0088) 171 #define APU_PCU_BUCK_ON_DAT1_H (0x008C) 172 #define APU_PCU_BUCK_OFF_DAT0_L (0x00A0) 173 #define APU_PCU_BUCK_OFF_DAT0_H (0x00A4) 174 #define APU_PCU_BUCK_ON_SLE0 (0x00C0) 175 #define APU_PCU_BUCK_ON_SLE1 (0x00C4) 176 #define VAPU_BUCK_ON_SETTLE_TIME (0x00C8) 177 #define APU_PCU_PMIC_TAR_BUF1 (0x0190) 178 #define APU_PCU_PMIC_TAR_BUF2 (0x0194) 179 #define APU_PCU_PMIC_CMD (0x0184) 180 #define APU_PCU_PMIC_IRQ (0x0180) 181 182 /* PCU control */ 183 #define PMIC_CMD_IRQ BIT(0) 184 #define PMIC_IRQ_EN BIT(2) 185 #define AUTO_BUCK_EN BIT(3) 186 #define PMIC_PMIFID_OFF (3) 187 #define PMIC_SLVID_OFF (4) 188 #define PCU_CMD_OP_W (0x7) 189 #define PMIC_OFF_ADDR_OFF (16) 190 #define PMIC_CMD_EN (0x1) 191 #define BUCK_STEP_SEL_VAL (0x13) 192 #define PCU_BUCK_OFF_CMD (0x7) 193 194 /* sram_core: mt6363_vbuck4 */ 195 #define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR (0x250) 196 197 /* sub_pmic */ 198 #define BUCK_VAPU_PMIC_ID MT6373_SLAVE_ID 199 #define BUCK_VAPU_PMIC_REG_VOSEL_ADDR MT6373_RG_BUCK_VBUCK2_VOSEL_ADDR 200 #define BUCK_VAPU_PMIC_REG_EN_SET_ADDR MT6373_RG_BUCK_VBUCK2_SET 201 #define BUCK_VAPU_PMIC_REG_EN_CLR_ADDR MT6373_RG_BUCK_VBUCK2_CLR 202 #define BUCK_VAPU_PMIC_REG_EN_SHIFT MT6373_RG_BUCK_VBUCK2_EN_SHIFT 203 204 /* vlp offset define */ 205 #define APUSYS_AO_SRAM_CONFIG (0x70) 206 #define APUSYS_AO_SRAM_SET (0x74) 207 #define APUSYS_AO_SRAM_CLR (0x78) 208 209 #define APUSYS_AO_SRAM_EN (0x1) 210 211 #define ARE_ENTRIES(x, y) ((((y) - (x)) + 1) * 2) 212 #define ARE_ENTRY(x) (((x) * 2) + 36) 213 #define ARE_RCX_AO_CONFIG (0x0014) 214 #define ARE_RCX_AO_CONFIG_HIGH_OFF (16) 215 216 #define APU_ACE_HW_FLAG_DIS (APUSYS_CE_BASE + 0x05D4) 217 #define APU_ACE_DIS_FLAG_VAL (0xffff7ff8) 218 219 #define OUT_CLK_FREQ_MIN (1500) 220 #define DDS_SHIFT (14) 221 #define BASIC_CLK_FREQ (26) 222 223 int apusys_power_init(void); 224 225 #endif /* APUSYS_POWER_H */ 226