1 /* 2 * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SEC_CORE_DEFS_H 8 #define SEC_CORE_DEFS_H 9 10 #include "kodiak_def.h" 11 12 #define APSS_BANKED_APSS_CPU_IPM_REG_BASE (QTI_APSS_HM_BASE + 0x00000000) 13 #define APSS_BANKED_APC_SECURE_ADDR (APSS_BANKED_APSS_CPU_IPM_REG_BASE + 0x0) 14 #define APSS_BANKED_APC_SECURE_RMSK 0x1 15 16 #define APSS_WDT_TMR1_APSS_WDT_REG_BASE (QTI_APSS_HM_BASE + 0x00410000) 17 #define APSS_WDT_TMR1_WDOG_SECURE_ADDR (APSS_WDT_TMR1_APSS_WDT_REG_BASE + 0x0) 18 #define APSS_WDT_TMR1_WDOG_SECURE_RMSK 0x1 19 20 #define APSS_SHARED_APSS_SHARED_REG_BASE (QTI_APSS_HM_BASE + 0x00600000) 21 #define APSS_SHARED_KRYO_RVBARADDR_LO_ADDR (APSS_SHARED_APSS_SHARED_REG_BASE + 0x1c) 22 #define APSS_SHARED_KRYO_RVBARADDR_HI_ADDR (APSS_SHARED_APSS_SHARED_REG_BASE + 0x20) 23 #define APSS_SHARED_SHR_SECURE_ADDR (APSS_SHARED_APSS_SHARED_REG_BASE + 0x4) 24 25 #define APSS_ALIAS_0_APSS_CPU_IPM_REG_BASE (QTI_APSS_HM_BASE + 0x00800000) 26 #define APSS_ALIAS_0_APC_SECURE_ADDR (APSS_ALIAS_0_APSS_CPU_IPM_REG_BASE + 0x0) 27 #define APSS_ALIAS_0_APC_SECURE_RMSK 0x1 28 29 #define APSS_ALIASn_APC_SECURE_OFFSET_TO_NEXT 0x10000 30 #define APSS_ALIASn_APC_SECURE_MAX_INDEX 0x7 31 32 #define APSS_APSS_CL_IPM_REG_BASE (QTI_APSS_HM_BASE + 0x00880000) 33 #define APSS_CL_SECURE_ADDR (APSS_APSS_CL_IPM_REG_BASE + 0x0) 34 #define APSS_CL_SECURE_RMSK 0x1 35 36 #define GOLD_SAW4_1_1_STS_REG_BASE (QTI_APSS_HM_BASE + 0x00901c00) 37 #define GOLD_SAW4_SECURE_ADDR (GOLD_SAW4_1_1_STS_REG_BASE + 0x0) 38 #define GOLD_SAW4_SECURE_RMSK 0x7 39 40 #define SILVER_SAW4_1_1_STS_REG_BASE (QTI_APSS_HM_BASE + 0x00900c00) 41 #define SILVER_SAW4_SECURE_ADDR (SILVER_SAW4_1_1_STS_REG_BASE + 0x0) 42 #define SILVER_SAW4_SECURE_RMSK 0x7 43 44 #define GOLD_APSS_KRYO_CLK_CTL_REG_BASE (QTI_APSS_HM_BASE + 0x00a82000) 45 #define GOLD_PLL_SECURE_ADDR (GOLD_APSS_KRYO_CLK_CTL_REG_BASE + 0x40) 46 #define GOLD_PLL_SECURE_RMSK 0x3 47 48 #define SILVER_APSS_KRYO_CLK_CTL_REG_BASE (QTI_APSS_HM_BASE + 0x00a80000) 49 #define SILVER_PLL_SECURE_ADDR (SILVER_APSS_KRYO_CLK_CTL_REG_BASE + 0x40) 50 #define SILVER_PLL_SECURE_RMSK 0x3 51 52 #define L3_APSS_KRYO_CLK_CTL_REG_BASE (QTI_APSS_HM_BASE + 0x00a84000) 53 #define L3_PLL_SECURE_ADDR (L3_APSS_KRYO_CLK_CTL_REG_BASE + 0x40) 54 #define L3_PLL_SECURE_RMSK 0x3 55 56 #define APSS_APSS_MISC_CLK_REG_BASE (QTI_APSS_HM_BASE + 0x00aa0000) 57 #define APSS_MISC_CLK_SECURE_ADDR (APSS_APSS_MISC_CLK_REG_BASE + 0x4) 58 #define APSS_MISC_CLK_SECURE_RMSK 0x1 59 60 #define APSS_APM_WRAP_REG_BASE (QTI_APSS_HM_BASE + 0x00b00000) 61 #define APSS_PWR_APM_SECURE_ADDR (APSS_APM_WRAP_REG_BASE + 0x24) 62 #define APSS_PWR_APM_SECURE_RMSK 0x3 63 #define APSS_PWR_MAS_SECURE_ADDR (APSS_APM_WRAP_REG_BASE + 0x28) 64 #define APSS_PWR_MAS_SECURE_RMSK 0xf 65 66 #endif /* SEC_CORE_DEFS_H */ 67