1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * rk3528_codec.h - Rockchip RK3528 SoC Codec Driver 4 * 5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef __RK3528_CODEC_H__ 9 #define __RK3528_CODEC_H__ 10 11 #define ACODEC_DIG00 0x00 /* REG 0x00 */ 12 #define ACODEC_DIG01 0x04 /* REG 0x01 */ 13 #define ACODEC_DIG02 0x08 /* REG 0x02 */ 14 #define ACODEC_DIG03 0x0c /* REG 0x03 */ 15 #define ACODEC_DIG04 0x10 /* REG 0x04 */ 16 #define ACODEC_DIG05 0x14 /* REG 0x05 */ 17 #define ACODEC_DIG06 0x18 /* REG 0x06 */ 18 #define ACODEC_DIG07 0x1c /* REG 0x07 */ 19 #define ACODEC_DIG08 0x20 /* REG 0x08 */ 20 #define ACODEC_DIG09 0x24 /* REG 0x09 */ 21 #define ACODEC_DIG0A 0x28 /* REG 0x0a */ 22 #define ACODEC_DIG0B 0x2c /* REG 0x0b */ 23 #define ACODEC_DIG0D 0x34 /* REG 0x0d */ 24 #define ACODEC_DIG0E 0x38 /* REG 0x0e */ 25 #define ACODEC_DIG10 0x40 /* REG 0x10 */ 26 #define ACODEC_DIG11 0x44 /* REG 0x11 */ 27 28 #define ACODEC_ANA00 0x80 /* REG 0x20 */ 29 #define ACODEC_ANA01 0x84 /* REG 0x21 */ 30 #define ACODEC_ANA02 0x88 /* REG 0x22 */ 31 #define ACODEC_ANA08 0xa0 /* REG 0x28 */ 32 #define ACODEC_ANA09 0xa4 /* REG 0x29 */ 33 #define ACODEC_ANA0A 0xa8 /* REG 0x2a */ 34 #define ACODEC_ANA0B 0xac /* REG 0x2b */ 35 #define ACODEC_ANA0C 0xb0 /* REG 0x2c */ 36 #define ACODEC_ANA0D 0xb4 /* REG 0x2d */ 37 #define ACODEC_ANA0E 0xb8 /* REG 0x2e */ 38 #define ACODEC_ANA0F 0xbc /* REG 0x2f */ 39 40 #define ACODEC_REG_MAX ACODEC_ANA0F 41 42 /* ACODEC_DIG00 */ 43 #define ACODEC_DAC_RST_MASK (0x1 << 4) 44 #define ACODEC_DAC_RST_P (0x1 << 4) 45 #define ACODEC_DAC_RST_N (0x0 << 4) 46 #define ACODEC_REG_BIST_EN (0x1 << 1) 47 #define ACODEC_SYS_RST_MASK (0x1 << 0) 48 #define ACODEC_SYS_RST_P (0x1 << 0) 49 #define ACODEC_SYS_RST_N (0x0 << 0) 50 51 /* ACODEC_DIG01 */ 52 #define ACODEC_DAC_I2S_WL_SHIFT 4 53 #define ACODEC_DAC_I2S_WL_MASK (0x3 << ACODEC_DAC_I2S_WL_SHIFT) 54 #define ACODEC_DAC_I2S_32B (0x3 << ACODEC_DAC_I2S_WL_SHIFT) 55 #define ACODEC_DAC_I2S_24B (0x2 << ACODEC_DAC_I2S_WL_SHIFT) 56 #define ACODEC_DAC_I2S_20B (0x1 << ACODEC_DAC_I2S_WL_SHIFT) 57 #define ACODEC_DAC_I2S_16B (0x0 << ACODEC_DAC_I2S_WL_SHIFT) 58 #define ACODEC_DAC_I2S_FMT_SHIFT 2 59 #define ACODEC_DAC_I2S_FMT_MASK (0x3 << ACODEC_DAC_I2S_FMT_SHIFT) 60 #define ACODEC_DAC_I2S_I2S (0x2 << ACODEC_DAC_I2S_FMT_SHIFT) 61 #define ACODEC_DAC_I2S_LJM (0x1 << ACODEC_DAC_I2S_FMT_SHIFT) 62 63 /* ACODEC_DIG02 */ 64 #define ACODEC_DAC_I2S_LRP_MASK (0x1 << 7) 65 #define ACODEC_DAC_I2S_LRP_REVSL (0x1 << 7) 66 #define ACODEC_DAC_I2S_LRP_NORMAL (0x0 << 7) 67 #define ACODEC_DAC_I2S_LR_SWAP (0x1 << 6) 68 #define ACODEC_DAC_I2S_MST_FUNC_MASK (0x1 << 5) 69 #define ACODEC_DAC_I2S_MST_FUNC_MASTER (0x1 << 5) 70 #define ACODEC_DAC_I2S_MST_FUNC_SLAVE (0x0 << 5) 71 #define ACODEC_DAC_I2S_MST_IO_MASK (0x1 << 4) 72 #define ACODEC_DAC_I2S_MST_IO_MASTER (0x1 << 4) 73 #define ACODEC_DAC_I2S_MST_IO_SLAVE (0x0 << 4) 74 #define ACODEC_DAC_I2S_RST_MASK (0x1 << 0) 75 #define ACODEC_DAC_I2S_RST_P (0x1 << 0) 76 #define ACODEC_DAC_I2S_RST_N (0x0 << 0) 77 78 /* ACODEC_DIG03 */ 79 #define ACODEC_DAC_MUTE_EN (0x1 << 7) 80 #define ACODEC_DAC_MUTE_SR_SHIFT 4 81 #define ACODEC_DAC_MUTE_SR_MASK (0x7 << ACODEC_DAC_MUTE_SR_SHIFT) 82 #define ACODEC_DAC_MUTE_SR_96K (0x7 << ACODEC_DAC_MUTE_SR_SHIFT) 83 #define ACODEC_DAC_MUTE_SR_88K2 (0x6 << ACODEC_DAC_MUTE_SR_SHIFT) 84 #define ACODEC_DAC_MUTE_SR_48K (0x5 << ACODEC_DAC_MUTE_SR_SHIFT) 85 #define ACODEC_DAC_MUTE_SR_44K1 (0x4 << ACODEC_DAC_MUTE_SR_SHIFT) 86 #define ACODEC_DAC_MUTE_SR_32K (0x3 << ACODEC_DAC_MUTE_SR_SHIFT) 87 #define ACODEC_DAC_MUTE_SR_24K (0x2 << ACODEC_DAC_MUTE_SR_SHIFT) 88 #define ACODEC_DAC_MUTE_SR_16K (0x1 << ACODEC_DAC_MUTE_SR_SHIFT) 89 #define ACODEC_DAC_MUTE_SR_8K (0x0 << ACODEC_DAC_MUTE_SR_SHIFT) 90 #define ACODEC_DA_EN (0x1 << 3) 91 #define ACODEC_DITHER_EN (0x1 << 2) 92 #define ACODEC_DITHER_LEVEL (0x1 << 1) 93 #define ACODEC_DITHER_SIGN (0x1 << 0) 94 95 /* ACODEC_DIG04 */ 96 #define ACODEC_DAC_DEEMP_SEL_MASK 0x3 97 #define ACODEC_DAC_DEEMP_48K 0x3 98 #define ACODEC_DAC_DEEMP_44K1 0x2 99 #define ACODEC_DAC_DEEMP_32K 0x1 100 #define ACODEC_DAC_DEEMP_DIS 0x0 101 102 /* ACODEC_DIG05 */ 103 #define ACODEC_DAC_R_BIST_SEL_SHIFT 6 104 #define ACODEC_DAC_R_BIST_SEL_MASK (0x3 << ACODEC_DAC_R_BIST_SEL_SHIFT) 105 #define ACODEC_DAC_R_BIST_SEL_L (0x2 << ACODEC_DAC_R_BIST_SEL_SHIFT) 106 #define ACODEC_DAC_R_BIST_SEL_SINE (0x1 << ACODEC_DAC_R_BIST_SEL_SHIFT) 107 #define ACODEC_DAC_R_BIST_SEL_R (0x0 << ACODEC_DAC_R_BIST_SEL_SHIFT) 108 #define ACODEC_DAC_R_MUTE (0x1 << 4) 109 #define ACODEC_DAC_L_BIST_SEL_SHIFT 2 110 #define ACODEC_DAC_L_BIST_SEL_MASK (0x3 << ACODEC_DAC_L_BIST_SEL_SHIFT) 111 #define ACODEC_DAC_L_BIST_SEL_R (0x2 << ACODEC_DAC_L_BIST_SEL_SHIFT) 112 #define ACODEC_DAC_L_BIST_SEL_SINE (0x1 << ACODEC_DAC_L_BIST_SEL_SHIFT) 113 #define ACODEC_DAC_L_BIST_SEL_L (0x0 << ACODEC_DAC_L_BIST_SEL_SHIFT) 114 #define ACODEC_DAC_J_MUTE (0x1 << 0) 115 116 /* ACODEC_DIG06 */ 117 #define ACODEC_DAC_DIG_GAIN_SHIT 0 118 #define ACODEC_DAC_DIG_GAIN_MASK (0xff << ACODEC_DAC_DIG_GAIN_SHIT) 119 /* 0.5dB every step , 1: -121dB, 255: 6dB */ 120 #define ACODEC_DAC_DIG_GAIN(x) ((x) & ACODEC_DAC_DIG_GAIN_MASK) 121 #define ACODEC_DAC_DIG_0DB 0xe1 122 123 /* ACODEC_ANA00 */ 124 #define ACODEC_IBIAS_DAC_MASK (0x1 << 1) 125 #define ACODEC_IBIAS_DAC_EN (0x1 << 1) 126 #define ACODEC_IBIAS_DAC_DIS (0x0 << 1) 127 #define ACODEC_VREF_MASK (0x1 << 0) 128 #define ACODEC_VREF_EN (0x1 << 0) 129 #define ACODEC_VREF_DIS (0x0 << 0) 130 131 /* ACODEC_ANA01 */ 132 #define ACODEC_VREF_SEL_SHIFT 0 133 /* Bit 0 is I0, bit 1 is 2 * I0 ... bit 7 is 128 * I0 */ 134 #define ACODEC_VREF_SEL_MASK (0xff << ACODEC_VREF_SEL_SHIFT) 135 #define ACODEC_VREF_SEL(x) ((x) & ACODEC_VREF_SEL_MASK) 136 137 /* ACODEC_ANA02 */ 138 #define ACODEC_IBIAS_DAC_SEL_SHIFT 0 139 /* Ibias_DAC = I0 * (BIT[3]*8+BIT[2]*4+BIT[1]*2+BIT[0]+1) */ 140 #define ACODEC_IBIAS_DAC_SEL (0xf << ACODEC_IBIAS_DAC_SEL_SHIFT) 141 142 /* ACODEC_ANA08 */ 143 #define ACODEC_DAC_L_POP_CTRL_SHIFT 5 144 #define ACODEC_DAC_L_POP_CTRL_MASK (0x3 << ACODEC_DAC_L_POP_CTRL_SHIFT) 145 #define ACODEC_DAC_L_POP_CTRL_ON (0x1 << ACODEC_DAC_L_POP_CTRL_SHIFT) 146 #define ACODEC_DAC_L_POP_CTRL_OFF (0x0 << ACODEC_DAC_L_POP_CTRL_SHIFT) 147 #define ACODEC_DAC_L_INIT_MASK (0x1 << 4) 148 #define ACODEC_DAC_L_WORK (0x1 << 4) 149 #define ACODEC_DAC_L_INIT (0x0 << 4) 150 #define ACODEC_DAC_L_VREF_MASK (0x1 << 3) 151 #define ACODEC_DAC_L_VREF_EN (0x1 << 3) 152 #define ACODEC_DAC_L_VREF_DIS (0x0 << 3) 153 #define ACODEC_DAC_L_BUF_MASK (0x1 << 2) 154 #define ACODEC_DAC_L_BUF_EN (0x1 << 2) 155 #define ACODEC_DAC_L_BUF_DIS (0x0 << 2) 156 #define ACODEC_DAC_L_CLK_MASK (0x1 << 1) 157 #define ACODEC_DAC_L_CLK_EN (0x1 << 1) 158 #define ACODEC_DAC_L_CLK_DIS (0x0 << 1) 159 #define ACODEC_DAC_L_MASK (0x1 << 0) 160 #define ACODEC_DAC_L_EN (0x1 << 0) 161 #define ACODEC_DAC_L_DIS (0x0 << 0) 162 163 /* ACODEC_ANA09 */ 164 #define ACODEC_LINEOUT_L_MUTE_MASK (0x1 << 5) 165 #define ACODEC_LINEOUT_L_WORK (0x1 << 5) 166 #define ACODEC_LINEOUT_L_MUTE (0x0 << 5) 167 #define ACODEC_LINEOUT_L_INIT_MASK (0x1 << 4) 168 #define ACODEC_LINEOUT_L_INIT_WORK (0x1 << 4) 169 #define ACODEC_LINEOUT_L_INIT (0x0 << 4) 170 #define ACODEC_LINEOUT_L_MASK (0x1 << 0) 171 #define ACODEC_LINEOUT_L_EN (0x1 << 0) 172 #define ACODEC_LINEOUT_L_DIS (0x0 << 0) 173 174 /* ACODEC_ANA0A */ 175 #define ACODEC_LINEOUT_L_SEL_SHIFT 0 176 #define ACODEC_LINEOUT_L_SEL_MASK (0xf << ACODEC_LINEOUT_L_SEL_SHIFT) 177 178 /* ACODEC_ANA0B */ 179 #define ACODEC_LINEOUT_L_GAIN_SHIFT 0 180 /* 1.5dB every step. 0: -39dB, 0x1f: 0dB */ 181 #define ACODEC_LINEOUT_L_GAIN_MASK (0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT) 182 183 /* ACODEC_ANA0C */ 184 #define ACODEC_DAC_R_POP_CTRL_SHIFT 5 185 #define ACODEC_DAC_R_POP_CTRL_MASK (0x3 << ACODEC_DAC_R_POP_CTRL_SHIFT) 186 #define ACODEC_DAC_R_POP_CTRL_ON (0x1 << ACODEC_DAC_R_POP_CTRL_SHIFT) 187 #define ACODEC_DAC_R_POP_CTRL_OFF (0x0 << ACODEC_DAC_R_POP_CTRL_SHIFT) 188 #define ACODEC_DAC_R_INIT_MASK (0x1 << 4) 189 #define ACODEC_DAC_R_WORK (0x1 << 4) 190 #define ACODEC_DAC_R_INIT (0x0 << 4) 191 #define ACODEC_DAC_R_VREF_MASK (0x1 << 3) 192 #define ACODEC_DAC_R_VREF_EN (0x1 << 3) 193 #define ACODEC_DAC_R_VREF_DIS (0x0 << 3) 194 #define ACODEC_DAC_R_BUF_MASK (0x1 << 2) 195 #define ACODEC_DAC_R_BUF_EN (0x1 << 2) 196 #define ACODEC_DAC_R_BUF_DIS (0x0 << 2) 197 #define ACODEC_DAC_R_CLK_MASK (0x1 << 1) 198 #define ACODEC_DAC_R_CLK_EN (0x1 << 1) 199 #define ACODEC_DAC_R_CLK_DIS (0x0 << 1) 200 #define ACODEC_DAC_R_MASK (0x1 << 0) 201 #define ACODEC_DAC_R_EN (0x1 << 0) 202 #define ACODEC_DAC_R_DIS (0x0 << 0) 203 204 /* ACODEC_ANA0D */ 205 #define ACODEC_LINEOUT_R_MUTE_MASK (0x1 << 5) 206 #define ACODEC_LINEOUT_R_WORK (0x1 << 5) 207 #define ACODEC_LINEOUT_R_MUTE (0x0 << 5) 208 #define ACODEC_LINEOUT_R_INIT_MASK (0x1 << 4) 209 #define ACODEC_LINEOUT_R_INIT_WORK (0x1 << 4) 210 #define ACODEC_LINEOUT_R_INIT (0x0 << 4) 211 #define ACODEC_LINEOUT_R_MASK (0x1 << 0) 212 #define ACODEC_LINEOUT_R_EN (0x1 << 0) 213 #define ACODEC_LINEOUT_R_DIS (0x0 << 0) 214 215 /* ACODEC_ANA0E */ 216 #define ACODEC_LINEOUT_R_SEL_SHIFT 0 217 #define ACODEC_LINEOUT_R_SEL_MASK (0xf << ACODEC_LINEOUT_L_SEL_SHIFT) 218 219 /* ACODEC_ANA0F */ 220 #define ACODEC_LINEOUT_R_GAIN_SHIFT 0 221 /* 1.5dB every step. 0: -39dB, 0x1f: 0dB */ 222 #define ACODEC_LINEOUT_R_GAIN_MASK (0x1f << ACODEC_LINEOUT_L_GAIN_SHIFT) 223 224 #define ACODEC_DAC_LINEOUT_GAIN_MAX 0x1e 225 #define ACODEC_DAC_LINEOUT_GAIN_MIN 0 226 #define ACODEC_HIFI 0x0 227 #define ACODEC_DAC_LINEOUT_GAIN_0DB 0x1a 228 229 #endif /* __RK3528_CODEC_H__ */ 230