1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1126_H 8 #define _ASM_ARCH_CRU_RV1126_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 17 #define APLL_HZ (1008 * MHz) 18 #else 19 #define APLL_HZ (816 * MHz) 20 #endif 21 #define GPLL_HZ (1188 * MHz) 22 #define CPLL_HZ (500 * MHz) 23 #define HPLL_HZ (1400 * MHz) 24 #define PCLK_PDPMU_HZ (100 * MHz) 25 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 26 #define ACLK_PDBUS_HZ (396 * MHz) 27 #else 28 #define ACLK_PDBUS_HZ (500 * MHz) 29 #endif 30 #define HCLK_PDBUS_HZ (200 * MHz) 31 #define PCLK_PDBUS_HZ (100 * MHz) 32 #define ACLK_PDPHP_HZ (300 * MHz) 33 #define HCLK_PDPHP_HZ (200 * MHz) 34 #define HCLK_PDCORE_HZ (200 * MHz) 35 #define HCLK_PDAUDIO_HZ (150 * MHz) 36 #define CLK_OSC0_DIV_HZ (32768) 37 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 38 #define ACLK_PDVI_HZ (297 * MHz) 39 #define CLK_ISP_HZ (297 * MHz) 40 #define ACLK_PDISPP_HZ (297 * MHz) 41 #define CLK_ISPP_HZ (237 * MHz) 42 #define ACLK_VOP_HZ (300 * MHz) 43 #define DCLK_VOP_HZ (65 * MHz) 44 #endif 45 46 /* RV1126 pll id */ 47 enum rv1126_pll_id { 48 APLL, 49 DPLL, 50 CPLL, 51 HPLL, 52 GPLL, 53 PLL_COUNT, 54 }; 55 56 struct rv1126_clk_info { 57 unsigned long id; 58 char *name; 59 bool is_cru; 60 }; 61 62 /* Private data for the clock driver - used by rockchip_get_cru() */ 63 struct rv1126_pmuclk_priv { 64 struct rv1126_pmucru *pmucru; 65 ulong gpll_hz; 66 }; 67 68 struct rv1126_clk_priv { 69 struct rv1126_cru *cru; 70 struct rv1126_grf *grf; 71 ulong gpll_hz; 72 ulong cpll_hz; 73 ulong hpll_hz; 74 ulong armclk_hz; 75 ulong armclk_enter_hz; 76 ulong armclk_init_hz; 77 bool sync_kernel; 78 bool set_armclk_rate; 79 }; 80 81 struct rv1126_pll { 82 unsigned int con0; 83 unsigned int con1; 84 unsigned int con2; 85 unsigned int con3; 86 unsigned int con4; 87 unsigned int con5; 88 unsigned int con6; 89 unsigned int reserved0[1]; 90 }; 91 92 struct rv1126_pmucru { 93 unsigned int pmu_mode; 94 unsigned int reserved1[3]; 95 struct rv1126_pll pll; 96 unsigned int offsetcal_status; 97 unsigned int reserved2[51]; 98 unsigned int pmu_clksel_con[14]; 99 unsigned int reserved3[18]; 100 unsigned int pmu_clkgate_con[3]; 101 unsigned int reserved4[29]; 102 unsigned int pmu_softrst_con[2]; 103 unsigned int reserved5[14]; 104 unsigned int pmu_autocs_con[2]; 105 }; 106 107 check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); 108 109 struct rv1126_cru { 110 struct rv1126_pll pll[4]; 111 unsigned int offsetcal_status[4]; 112 unsigned int mode; 113 unsigned int reserved1[27]; 114 unsigned int clksel_con[78]; 115 unsigned int reserved2[18]; 116 unsigned int clkgate_con[25]; 117 unsigned int reserved3[7]; 118 unsigned int softrst_con[15]; 119 unsigned int reserved4[17]; 120 unsigned int ssgtbl[32]; 121 unsigned int glb_cnt_th; 122 unsigned int glb_rst_st; 123 unsigned int glb_srst_fst; 124 unsigned int glb_srst_snd; 125 unsigned int glb_rst_con; 126 unsigned int reserved5[11]; 127 unsigned int sdmmc_con[2]; 128 unsigned int sdio_con[2]; 129 unsigned int emmc_con[2]; 130 unsigned int reserved6[2]; 131 unsigned int gmac_con; 132 unsigned int misc[2]; 133 unsigned int reserved7[45]; 134 unsigned int autocs_con[26]; 135 }; 136 137 check_member(rv1126_cru, autocs_con[25], 0x584); 138 139 struct pll_rate_table { 140 unsigned long rate; 141 unsigned int fbdiv; 142 unsigned int postdiv1; 143 unsigned int refdiv; 144 unsigned int postdiv2; 145 unsigned int dsmpd; 146 unsigned int frac; 147 }; 148 149 struct cpu_rate_table { 150 unsigned long rate; 151 unsigned int aclk_div; 152 unsigned int pclk_div; 153 }; 154 155 #define RV1126_PMU_MODE 0x0 156 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 157 #define RV1126_PLL_CON(x) ((x) * 0x4) 158 #define RV1126_MODE_CON 0x90 159 160 enum { 161 /* CRU_PMU_CLK_SEL0_CON */ 162 RTC32K_SEL_SHIFT = 7, 163 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 164 RTC32K_SEL_PMUPVTM = 0, 165 RTC32K_SEL_OSC1_32K, 166 RTC32K_SEL_OSC0_DIV32K, 167 168 /* CRU_PMU_CLK_SEL1_CON */ 169 PCLK_PDPMU_DIV_SHIFT = 0, 170 PCLK_PDPMU_DIV_MASK = 0x1f, 171 172 /* CRU_PMU_CLK_SEL2_CON */ 173 CLK_I2C0_DIV_SHIFT = 0, 174 CLK_I2C0_DIV_MASK = 0x7f, 175 176 /* CRU_PMU_CLK_SEL3_CON */ 177 CLK_I2C2_DIV_SHIFT = 0, 178 CLK_I2C2_DIV_MASK = 0x7f, 179 180 /* CRU_PMU_CLK_SEL6_CON */ 181 CLK_PWM1_SEL_SHIFT = 15, 182 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 183 CLK_PWM1_SEL_XIN24M = 0, 184 CLK_PWM1_SEL_GPLL, 185 CLK_PWM1_DIV_SHIFT = 8, 186 CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, 187 CLK_PWM0_SEL_SHIFT = 7, 188 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 189 CLK_PWM0_SEL_XIN24M = 0, 190 CLK_PWM0_SEL_GPLL, 191 CLK_PWM0_DIV_SHIFT = 0, 192 CLK_PWM0_DIV_MASK = 0x7f, 193 194 /* CRU_PMU_CLK_SEL9_CON */ 195 CLK_SPI0_SEL_SHIFT = 7, 196 CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, 197 CLK_SPI0_SEL_GPLL = 0, 198 CLK_SPI0_SEL_XIN24M, 199 CLK_SPI0_DIV_SHIFT = 0, 200 CLK_SPI0_DIV_MASK = 0x7f, 201 202 /* CRU_PMU_CLK_SEL13_CON */ 203 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 204 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 205 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 206 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 207 208 /* CRU_CLK_SEL0_CON */ 209 CORE_HCLK_DIV_SHIFT = 8, 210 CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, 211 212 /* CRU_CLK_SEL1_CON */ 213 CORE_ACLK_DIV_SHIFT = 4, 214 CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, 215 CORE_DBG_DIV_SHIFT = 0, 216 CORE_DBG_DIV_MASK = 0x7, 217 218 /* CRU_CLK_SEL2_CON */ 219 HCLK_PDBUS_SEL_SHIFT = 15, 220 HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, 221 HCLK_PDBUS_SEL_GPLL = 0, 222 HCLK_PDBUS_SEL_CPLL, 223 HCLK_PDBUS_DIV_SHIFT = 8, 224 HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, 225 ACLK_PDBUS_SEL_SHIFT = 6, 226 ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, 227 ACLK_PDBUS_SEL_GPLL = 0, 228 ACLK_PDBUS_SEL_CPLL, 229 ACLK_PDBUS_SEL_DPLL, 230 ACLK_PDBUS_DIV_SHIFT = 0, 231 ACLK_PDBUS_DIV_MASK = 0x1f, 232 233 /* CRU_CLK_SEL3_CON */ 234 CLK_SCR1_SEL_SHIFT = 15, 235 CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, 236 CLK_SCR1_SEL_GPLL = 0, 237 CLK_SCR1_SEL_CPLL, 238 CLK_SCR1_DIV_SHIFT = 8, 239 CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, 240 PCLK_PDBUS_SEL_SHIFT = 7, 241 PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, 242 PCLK_PDBUS_SEL_GPLL = 0, 243 PCLK_PDBUS_SEL_CPLL, 244 PCLK_PDBUS_DIV_SHIFT = 0, 245 PCLK_PDBUS_DIV_MASK = 0x1f, 246 247 /* CRU_CLK_SEL4_CON */ 248 ACLK_CRYPTO_SEL_SHIFT = 7, 249 ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, 250 ACLK_CRYPTO_SEL_GPLL = 0, 251 ACLK_CRYPTO_SEL_CPLL, 252 ACLK_CRYPTO_DIV_SHIFT = 0, 253 ACLK_CRYPTO_DIV_MASK = 0x1f, 254 255 /* CRU_CLK_SEL5_CON */ 256 CLK_I2C3_DIV_SHIFT = 8, 257 CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, 258 CLK_I2C1_DIV_SHIFT = 0, 259 CLK_I2C1_DIV_MASK = 0x7f, 260 261 /* CRU_CLK_SEL6_CON */ 262 CLK_I2C5_DIV_SHIFT = 8, 263 CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, 264 CLK_I2C4_DIV_SHIFT = 0, 265 CLK_I2C4_DIV_MASK = 0x7f, 266 267 /* CRU_CLK_SEL7_CON */ 268 CLK_CRYPTO_PKA_SEL_SHIFT = 15, 269 CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, 270 CLK_CRYPTO_PKA_SEL_GPLL = 0, 271 CLK_CRYPTO_PKA_SEL_CPLL, 272 CLK_CRYPTO_PKA_DIV_SHIFT = 8, 273 CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, 274 CLK_CRYPTO_CORE_SEL_SHIFT = 7, 275 CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, 276 CLK_CRYPTO_CORE_SEL_GPLL = 0, 277 CLK_CRYPTO_CORE_SEL_CPLL, 278 CLK_CRYPTO_CORE_DIV_SHIFT = 0, 279 CLK_CRYPTO_CORE_DIV_MASK = 0x1f, 280 281 /* CRU_CLK_SEL8_CON */ 282 CLK_SPI1_SEL_SHIFT = 8, 283 CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, 284 CLK_SPI1_SEL_GPLL = 0, 285 CLK_SPI1_SEL_XIN24M, 286 CLK_SPI1_DIV_SHIFT = 0, 287 CLK_SPI1_DIV_MASK = 0x7f, 288 289 /* CRU_CLK_SEL9_CON */ 290 CLK_PWM2_SEL_SHIFT = 15, 291 CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 292 CLK_PWM2_SEL_XIN24M = 0, 293 CLK_PWM2_SEL_GPLL, 294 CLK_PWM2_DIV_SHIFT = 8, 295 CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, 296 297 /* CRU_CLK_SEL20_CON */ 298 CLK_SARADC_DIV_SHIFT = 0, 299 CLK_SARADC_DIV_MASK = 0x7ff, 300 301 /* CRU_CLK_SEL25_CON */ 302 DCLK_DECOM_SEL_SHIFT = 15, 303 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 304 DCLK_DECOM_SEL_GPLL = 0, 305 DCLK_DECOM_SEL_CPLL, 306 DCLK_DECOM_DIV_SHIFT = 8, 307 DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT, 308 309 /* CRU_CLK_SEL26_CON */ 310 HCLK_PDAUDIO_DIV_SHIFT = 0, 311 HCLK_PDAUDIO_DIV_MASK = 0x1f, 312 313 /* CRU_CLK_SEL45_CON */ 314 ACLK_PDVO_SEL_SHIFT = 7, 315 ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, 316 ACLK_PDVO_SEL_GPLL = 0, 317 ACLK_PDVO_SEL_CPLL, 318 ACLK_PDVO_DIV_SHIFT = 0, 319 ACLK_PDVO_DIV_MASK = 0x1f, 320 321 /* CRU_CLK_SEL47_CON */ 322 DCLK_VOP_SEL_SHIFT = 8, 323 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 324 DCLK_VOP_SEL_GPLL = 0, 325 DCLK_VOP_SEL_CPLL, 326 DCLK_VOP_DIV_SHIFT = 0, 327 DCLK_VOP_DIV_MASK = 0xff, 328 329 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 330 /* CRU_CLK_SEL49_CON */ 331 ACLK_PDVI_SEL_SHIFT = 6, 332 ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, 333 ACLK_PDVI_SEL_CPLL = 0, 334 ACLK_PDVI_SEL_GPLL, 335 ACLK_PDVI_SEL_HPLL, 336 ACLK_PDVI_DIV_SHIFT = 0, 337 ACLK_PDVI_DIV_MASK = 0x1f, 338 339 /* CRU_CLK_SEL50_CON */ 340 CLK_ISP_SEL_SHIFT = 6, 341 CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT, 342 CLK_ISP_SEL_GPLL = 0, 343 CLK_ISP_SEL_CPLL, 344 CLK_ISP_SEL_HPLL, 345 CLK_ISP_DIV_SHIFT = 0, 346 CLK_ISP_DIV_MASK = 0x1f, 347 #endif 348 349 /* CRU_CLK_SEL53_CON */ 350 HCLK_PDPHP_DIV_SHIFT = 8, 351 HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, 352 ACLK_PDPHP_SEL_SHIFT = 7, 353 ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, 354 ACLK_PDPHP_SEL_GPLL = 0, 355 ACLK_PDPHP_SEL_CPLL, 356 ACLK_PDPHP_DIV_SHIFT = 0, 357 ACLK_PDPHP_DIV_MASK = 0x1f, 358 359 /* CRU_CLK_SEL57_CON */ 360 EMMC_SEL_SHIFT = 14, 361 EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, 362 EMMC_SEL_GPLL = 0, 363 EMMC_SEL_CPLL, 364 EMMC_SEL_XIN24M, 365 EMMC_DIV_SHIFT = 0, 366 EMMC_DIV_MASK = 0xff, 367 368 /* CRU_CLK_SEL58_CON */ 369 SCLK_SFC_SEL_SHIFT = 15, 370 SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, 371 SCLK_SFC_SEL_CPLL = 0, 372 SCLK_SFC_SEL_GPLL, 373 SCLK_SFC_DIV_SHIFT = 0, 374 SCLK_SFC_DIV_MASK = 0xff, 375 376 /* CRU_CLK_SEL59_CON */ 377 CLK_NANDC_SEL_SHIFT = 15, 378 CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, 379 CLK_NANDC_SEL_GPLL = 0, 380 CLK_NANDC_SEL_CPLL, 381 CLK_NANDC_DIV_SHIFT = 0, 382 CLK_NANDC_DIV_MASK = 0xff, 383 384 /* CRU_CLK_SEL61_CON */ 385 CLK_GMAC_OUT_SEL_SHIFT = 15, 386 CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT, 387 CLK_GMAC_OUT_SEL_CPLL = 0, 388 CLK_GMAC_OUT_SEL_GPLL, 389 CLK_GMAC_OUT_DIV_SHIFT = 8, 390 CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT, 391 392 /* CRU_CLK_SEL63_CON */ 393 PCLK_GMAC_DIV_SHIFT = 8, 394 PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT, 395 CLK_GMAC_SRC_SEL_SHIFT = 7, 396 CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT, 397 CLK_GMAC_SRC_SEL_CPLL = 0, 398 CLK_GMAC_SRC_SEL_GPLL, 399 CLK_GMAC_SRC_DIV_SHIFT = 0, 400 CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, 401 402 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 403 /* CRU_CLK_SEL68_CON */ 404 ACLK_PDISPP_SEL_SHIFT = 6, 405 ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, 406 ACLK_PDISPP_SEL_CPLL = 0, 407 ACLK_PDISPP_SEL_GPLL, 408 ACLK_PDISPP_SEL_HPLL, 409 ACLK_PDISPP_DIV_SHIFT = 0, 410 ACLK_PDISPP_DIV_MASK = 0x1f, 411 412 /* CRU_CLK_SEL69_CON */ 413 CLK_ISPP_SEL_SHIFT = 6, 414 CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT, 415 CLK_ISPP_SEL_CPLL = 0, 416 CLK_ISPP_SEL_GPLL, 417 CLK_ISPP_SEL_HPLL, 418 CLK_ISPP_DIV_SHIFT = 0, 419 CLK_ISPP_DIV_MASK = 0x1f, 420 421 /* CRU_CLK_SEL73_CON */ 422 MIPICSI_OUT_SEL_SHIFT = 10, 423 MIPICSI_OUT_SEL_MASK = 0x3 << MIPICSI_OUT_SEL_SHIFT, 424 MIPICSI_OUT_SEL_XIN24M = 0, 425 MIPICSI_OUT_SEL_DIV, 426 MIPICSI_OUT_SEL_FRACDIV, 427 MIPICSI_OUT_DIV_SHIFT = 0, 428 MIPICSI_OUT_DIV_MASK = 0x1f, 429 #endif 430 431 /* CRU_GMAC_CON */ 432 GMAC_SRC_M1_SEL_SHIFT = 5, 433 GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, 434 GMAC_SRC_M1_SEL_INT = 0, 435 GMAC_SRC_M1_SEL_EXT, 436 GMAC_MODE_SEL_SHIFT = 4, 437 GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT, 438 GMAC_RGMII_MODE = 0, 439 GMAC_RMII_MODE, 440 RGMII_CLK_SEL_SHIFT = 2, 441 RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT, 442 RGMII_CLK_DIV0 = 0, 443 RGMII_CLK_DIV1, 444 RGMII_CLK_DIV50, 445 RGMII_CLK_DIV5, 446 RMII_CLK_SEL_SHIFT = 1, 447 RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, 448 RMII_CLK_DIV20 = 0, 449 RMII_CLK_DIV2, 450 GMAC_SRC_M0_SEL_SHIFT = 0, 451 GMAC_SRC_M0_SEL_MASK = 0x1, 452 GMAC_SRC_M0_SEL_INT = 0, 453 GMAC_SRC_M0_SEL_EXT, 454 455 /* GRF_IOFUNC_CON1 */ 456 GMAC_SRC_SEL_SHIFT = 12, 457 GMAC_SRC_SEL_MASK = 1 << GMAC_SRC_SEL_SHIFT, 458 GMAC_SRC_SEL_M0 = 0, 459 GMAC_SRC_SEL_M1, 460 }; 461 #endif 462