1 /* 2 * Copyright (c) 2019-2022 Rockchip Eletronics Co., Ltd. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef __CALIBDBV2_ABLC_HEADER_V32_H__ 17 #define __CALIBDBV2_ABLC_HEADER_V32_H__ 18 19 #include "rk_aiq_comm.h" 20 21 RKAIQ_BEGIN_DECLARE 22 23 #define ABLCV32_MAX_ISO_LEVEL (13) 24 #define ABLCV32_MAX_CHANNEL_NUM 4 25 26 /*****************************************************************************/ 27 /** 28 * @brief ISP3.2 ABLC Config Params 29 */ 30 /*****************************************************************************/ 31 32 typedef struct Blc_data_V32_s { 33 // M4_ARRAY_DESC("ISO", "f32", M4_SIZE(1,13), M4_RANGE(0,10000000), "50",M4_DIGIT(4), M4_DYNAMIC(0)) 34 float ISO[ABLCV32_MAX_ISO_LEVEL]; 35 // M4_ARRAY_DESC("R_Channel", "f32", M4_SIZE(1,13), M4_RANGE(0,4095), "0",M4_DIGIT(4), M4_DYNAMIC(0)) 36 float R_Channel[ABLCV32_MAX_ISO_LEVEL]; 37 // M4_ARRAY_DESC("Gr_Channel", "f32", M4_SIZE(1,13), M4_RANGE(0,4095), "0",M4_DIGIT(4), M4_DYNAMIC(0)) 38 float Gr_Channel[ABLCV32_MAX_ISO_LEVEL]; 39 // M4_ARRAY_DESC("Gb_Channel", "f32", M4_SIZE(1,13), M4_RANGE(0,4095), "0",M4_DIGIT(4), M4_DYNAMIC(0)) 40 float Gb_Channel[ABLCV32_MAX_ISO_LEVEL]; 41 // M4_ARRAY_DESC("B_Channel", "f32", M4_SIZE(1,13), M4_RANGE(0,4095), "0",M4_DIGIT(4), M4_DYNAMIC(0)) 42 float B_Channel[ABLCV32_MAX_ISO_LEVEL]; 43 } Blc_data_V32_t; 44 45 typedef struct AblcV32ParaV2_s { 46 // M4_BOOL_DESC("enable", "1") 47 bool enable; 48 // M4_ARRAY_TABLE_DESC("BLC_Data", "array_table_ui", "none") 49 Blc_data_V32_t BLC_Data; 50 } AblcV32ParaV2_t; 51 52 typedef struct Blc_ob_dataV32_s { 53 // M4_ARRAY_DESC("ISO", "f32", M4_SIZE(1,13), M4_RANGE(0,10000000), "50",M4_DIGIT(4), M4_DYNAMIC(0)) 54 float ISO[ABLCV32_MAX_ISO_LEVEL]; 55 // M4_ARRAY_DESC("isp_ob_Offset", "f32", M4_SIZE(1,13), M4_RANGE(0,511), "0",M4_DIGIT(4), M4_DYNAMIC(0)) 56 float isp_ob_Offset[ABLCV32_MAX_ISO_LEVEL]; 57 // M4_ARRAY_DESC("isp_ob_preDgain", "f32", M4_SIZE(1,13), M4_RANGE(0,256), "1",M4_DIGIT(2), M4_DYNAMIC(0)) 58 float isp_ob_preDgain[ABLCV32_MAX_ISO_LEVEL]; 59 } Blc_ob_dataV32_t; 60 61 typedef struct AblcV32OBPara_s { 62 // M4_BOOL_DESC("enable", "1") 63 bool enable; 64 // M4_ARRAY_TABLE_DESC("BLC_OB_Data", "array_table_ui", "none") 65 Blc_ob_dataV32_t BLC_OB_Data; 66 } AblcV32OBPara_t; 67 68 typedef struct CalibDbV2_Blc_V32_s { 69 // M4_STRUCT_DESC("Blc0TuningPara", "normal_ui_style") 70 AblcV32ParaV2_t Blc0TuningPara; 71 // M4_STRUCT_DESC("Blc1TuningPara", "normal_ui_style") 72 AblcV32ParaV2_t Blc1TuningPara; 73 // M4_STRUCT_DESC("BlcObPara", "normal_ui_style") 74 AblcV32OBPara_t BlcObPara; 75 } CalibDbV2_Blc_V32_t; 76 77 RKAIQ_END_DECLARE 78 79 #endif 80