//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
// All software, firmware and related documentation herein ("MStar Software") are
// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
// law, including, but not limited to, copyright law and international treaties.
// Any use, modification, reproduction, retransmission, or republication of all
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// By accessing, browsing and/or using MStar Software, you acknowledge that you
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// 1. MStar shall retain any and all right, ownership and interest to MStar
//    Software and any modification/derivatives thereof.
//    No right, ownership, or interest to MStar Software and any
//    modification/derivatives thereof is transferred to you under Terms.
//
// 2. You understand that MStar Software might include, incorporate or be
//    supplied together with third party`s software and the use of MStar
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// 4. MStar Software is provided on an "AS IS" basis without warranties of any
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//        including without limitation, you and your customers, any assistance
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// 7. These terms shall be governed by and construed in accordance with the laws
//    of Taiwan, R.O.C., excluding its conflict of law rules.
//    Any and all dispute arising out hereof or related hereto shall be finally
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//    be English.
//    The arbitration award shall be final and binding to both parties.
//
//******************************************************************************
//<MStar Software>
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// ("MStar Confidential Information") by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _DRV_DTC_H_
#define _DRV_DTC_H_

#define UTOPIA 0
#define UTOPIA2L 1

#ifdef UTOPIA_TYPE
    #if (UTOPIA_TYPE == UTOPIA2L)
        #if defined (__aarch64__)
        #define DTC_MS_U32_d "d"
        #define DTC_MS_U32_i "i"
        #define DTC_MS_U32_x "x"
        #define DTC_MS_U32_X "X"
        #define DTC_MS_U32_u "u"

        #define DTC_MS_U64_d "ld"
        #define DTC_MS_U64_i "li"
        #define DTC_MS_U64_x "lx"
        #define DTC_MS_U64_X "lX"
        #define DTC_MS_U64_u "lu"

        #define DTC_MS_S32_d "d"
        #define DTC_MS_S32_i "i"
        #define DTC_MS_S32_x "x"
        #define DTC_MS_S32_X "X"
        #define DTC_MS_S32_u "u"

        #define DTC_MS_S64_d "ld"
        #define DTC_MS_S64_i "li"
        #define DTC_MS_S64_x "lx"
        #define DTC_MS_S64_X "lX"
        #define DTC_MS_S64_u "lu"

        #define DTC_MS_PHY_d DTC_MS_U64_d
        #define DTC_MS_PHY_i DTC_MS_U64_i
        #define DTC_MS_PHY_x DTC_MS_U64_x
        #define DTC_MS_PHY_X DTC_MS_U64_X
        #define DTC_MS_PHY_u DTC_MS_U64_u

        #define DTC_MS_VIRT_d "zd"
        #define DTC_MS_VIRT_i "zi"
        #define DTC_MS_VIRT_x "zx"
        #define DTC_MS_VIRT_X "zX"
        #define DTC_MS_VIRT_u "zu"

        #define DTC_MS_PHYADDR_d "zd"
        #define DTC_MS_PHYADDR_i "zi"
        #define DTC_MS_PHYADDR_x "zx"
        #define DTC_MS_PHYADDR_X "zX"
        #define DTC_MS_PHYADDR_u "zu"
        #else
        #define DTC_MS_U32_d "d"
        #define DTC_MS_U32_i "i"
        #define DTC_MS_U32_x "x"
        #define DTC_MS_U32_X "X"
        #define DTC_MS_U32_u "u"

        #define DTC_MS_U64_d "lld"
        #define DTC_MS_U64_i "lli"
        #define DTC_MS_U64_x "llx"
        #define DTC_MS_U64_X "llX"
        #define DTC_MS_U64_u "llu"

        #define DTC_MS_S32_d "d"
        #define DTC_MS_S32_i "i"
        #define DTC_MS_S32_x "x"
        #define DTC_MS_S32_X "X"
        #define DTC_MS_S32_u "u"

        #define DTC_MS_S64_d "lld"
        #define DTC_MS_S64_i "lli"
        #define DTC_MS_S64_x "llx"
        #define DTC_MS_S64_X "llX"
        #define DTC_MS_S64_u "llu"

        #define DTC_MS_PHY_d DTC_MS_U64_d
        #define DTC_MS_PHY_i DTC_MS_U64_i
        #define DTC_MS_PHY_x DTC_MS_U64_x
        #define DTC_MS_PHY_X DTC_MS_U64_X
        #define DTC_MS_PHY_u DTC_MS_U64_u

        #define DTC_MS_VIRT_d "zd"
        #define DTC_MS_VIRT_i "zi"
        #define DTC_MS_VIRT_x "zx"
        #define DTC_MS_VIRT_X "zX"
        #define DTC_MS_VIRT_u "zu"

        #define DTC_MS_PHYADDR_d "zd"
        #define DTC_MS_PHYADDR_i "zi"
        #define DTC_MS_PHYADDR_x "zx"
        #define DTC_MS_PHYADDR_X "zX"
        #define DTC_MS_PHYADDR_u "zu"
        #endif
    #else
        #define DTC_MS_U32_d "ld"
        #define DTC_MS_U32_i "li"
        #define DTC_MS_U32_x "lx"
        #define DTC_MS_U32_X "lX"
        #define DTC_MS_U32_u "lu"

        #define DTC_MS_U64_d "lld"
        #define DTC_MS_U64_i "lli"
        #define DTC_MS_U64_x "llx"
        #define DTC_MS_U64_X "llX"
        #define DTC_MS_U64_u "llu"

        #define DTC_MS_S32_d "ld"
        #define DTC_MS_S32_i "li"
        #define DTC_MS_S32_x "lx"
        #define DTC_MS_S32_X "lX"
        #define DTC_MS_S32_u "lu"

        #define DTC_MS_S64_d "lld"
        #define DTC_MS_S64_i "lli"
        #define DTC_MS_S64_x "llx"
        #define DTC_MS_S64_X "llX"
        #define DTC_MS_S64_u "llu"

        #define DTC_MS_PHY_d DTC_MS_U32_d
        #define DTC_MS_PHY_i DTC_MS_U32_i
        #define DTC_MS_PHY_x DTC_MS_U32_x
        #define DTC_MS_PHY_X DTC_MS_U32_X
        #define DTC_MS_PHY_u DTC_MS_U32_u

        #define DTC_MS_VIRT_d DTC_MS_U32_d
        #define DTC_MS_VIRT_i DTC_MS_U32_i
        #define DTC_MS_VIRT_x DTC_MS_U32_x
        #define DTC_MS_VIRT_X DTC_MS_U32_X
        #define DTC_MS_VIRT_u DTC_MS_U32_u

        #define DTC_MS_PHYADDR_d DTC_MS_PHY_d
        #define DTC_MS_PHYADDR_i DTC_MS_PHY_i
        #define DTC_MS_PHYADDR_x DTC_MS_PHY_x
        #define DTC_MS_PHYADDR_X DTC_MS_PHY_X
        #define DTC_MS_PHYADDR_u DTC_MS_PHY_u
    #endif
#else
#define DTC_MS_U32_d "ld"
#define DTC_MS_U32_i "li"
#define DTC_MS_U32_x "lx"
#define DTC_MS_U32_X "lX"
#define DTC_MS_U32_u "lu"

#define DTC_MS_U64_d "lld"
#define DTC_MS_U64_i "lli"
#define DTC_MS_U64_x "llx"
#define DTC_MS_U64_X "llX"
#define DTC_MS_U64_u "llu"

#define DTC_MS_S32_d "ld"
#define DTC_MS_S32_i "li"
#define DTC_MS_S32_x "lx"
#define DTC_MS_S32_X "lX"
#define DTC_MS_S32_u "lu"

#define DTC_MS_S64_d "lld"
#define DTC_MS_S64_i "lli"
#define DTC_MS_S64_x "llx"
#define DTC_MS_S64_X "llX"
#define DTC_MS_S64_u "llu"

#define DTC_MS_PHYADDR_d "ld"
#define DTC_MS_PHYADDR_i "li"
#define DTC_MS_PHYADDR_x "lx"
#define DTC_MS_PHYADDR_X "lX"
#define DTC_MS_PHYADDR_u "lu"
#endif

#endif