//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
// All software, firmware and related documentation herein ("MStar Software") are
// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
// law, including, but not limited to, copyright law and international treaties.
// Any use, modification, reproduction, retransmission, or republication of all 
// or part of MStar Software is expressly prohibited, unless prior written 
// permission has been granted by MStar. 
//
// By accessing, browsing and/or using MStar Software, you acknowledge that you
// have read, understood, and agree, to be bound by below terms ("Terms") and to
// comply with all applicable laws and regulations:
//
// 1. MStar shall retain any and all right, ownership and interest to MStar
//    Software and any modification/derivatives thereof.
//    No right, ownership, or interest to MStar Software and any
//    modification/derivatives thereof is transferred to you under Terms.
//
// 2. You understand that MStar Software might include, incorporate or be
//    supplied together with third party`s software and the use of MStar
//    Software may require additional licenses from third parties.  
//    Therefore, you hereby agree it is your sole responsibility to separately
//    obtain any and all third party right and license necessary for your use of
//    such third party`s software. 
//
// 3. MStar Software and any modification/derivatives thereof shall be deemed as
//    MStar`s confidential information and you agree to keep MStar`s 
//    confidential information in strictest confidence and not disclose to any
//    third party.  
//
// 4. MStar Software is provided on an "AS IS" basis without warranties of any
//    kind. Any warranties are hereby expressly disclaimed by MStar, including
//    without limitation, any warranties of merchantability, non-infringement of
//    intellectual property rights, fitness for a particular purpose, error free
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//    claim against MStar for any loss, damage, cost or expense that you may
//    incur related to your use of MStar Software.
//    In no event shall MStar be liable for any direct, indirect, incidental or
//    consequential damages, including without limitation, lost of profit or
//    revenues, lost or damage of data, and unauthorized system use.
//    You agree that this Section 4 shall still apply without being affected
//    even if MStar Software has been modified by MStar in accordance with your
//    request or instruction for your use, except otherwise agreed by both
//    parties in writing.
//
// 5. If requested, MStar may from time to time provide technical supports or
//    services in relation with MStar Software to you for your use of
//    MStar Software in conjunction with your or your customer`s product
//    ("Services").
//    You understand and agree that, except otherwise agreed by both parties in
//    writing, Services are provided on an "AS IS" basis and the warranty
//    disclaimer set forth in Section 4 above shall apply.  
//
// 6. Nothing contained herein shall be construed as by implication, estoppels
//    or otherwise:
//    (a) conferring any license or right to use MStar name, trademark, service
//        mark, symbol or any other identification;
//    (b) obligating MStar or any of its affiliates to furnish any person,
//        including without limitation, you and your customers, any assistance
//        of any kind whatsoever, or any information; or 
//    (c) conferring any license or right under any intellectual property right.
//
// 7. These terms shall be governed by and construed in accordance with the laws
//    of Taiwan, R.O.C., excluding its conflict of law rules.
//    Any and all dispute arising out hereof or related hereto shall be finally
//    settled by arbitration referred to the Chinese Arbitration Association,
//    Taipei in accordance with the ROC Arbitration Law and the Arbitration
//    Rules of the Association by three (3) arbitrators appointed in accordance
//    with the said Rules.
//    The place of arbitration shall be in Taipei, Taiwan and the language shall
//    be English.  
//    The arbitration award shall be final and binding to both parties.
//
//******************************************************************************
//<MStar Software>
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// ("MStar Confidential Information") by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////

#ifndef _HWREG_HDMI_H_
#define _HWREG_HDMI_H_


//=============================================================
// DVI DTOP

#define REG_DVI_DTOP_00_L        (REG_DVI_DTOP_BASE + 0x00)
#define REG_DVI_DTOP_00_H        (REG_DVI_DTOP_BASE + 0x01)
#define REG_DVI_DTOP_01_L        (REG_DVI_DTOP_BASE + 0x02)
#define REG_DVI_DTOP_01_H        (REG_DVI_DTOP_BASE + 0x03)
#define REG_DVI_DTOP_02_L        (REG_DVI_DTOP_BASE + 0x04)
#define REG_DVI_DTOP_02_H        (REG_DVI_DTOP_BASE + 0x05)
#define REG_DVI_DTOP_03_L        (REG_DVI_DTOP_BASE + 0x06)
#define REG_DVI_DTOP_03_H        (REG_DVI_DTOP_BASE + 0x07)
#define REG_DVI_DTOP_04_L        (REG_DVI_DTOP_BASE + 0x08)
#define REG_DVI_DTOP_04_H        (REG_DVI_DTOP_BASE + 0x09)
#define REG_DVI_DTOP_05_L        (REG_DVI_DTOP_BASE + 0x0A)
#define REG_DVI_DTOP_05_H        (REG_DVI_DTOP_BASE + 0x0B)
#define REG_DVI_DTOP_06_L        (REG_DVI_DTOP_BASE + 0x0C)
#define REG_DVI_DTOP_06_H        (REG_DVI_DTOP_BASE + 0x0D)
#define REG_DVI_DTOP_07_L        (REG_DVI_DTOP_BASE + 0x0E)
#define REG_DVI_DTOP_07_H        (REG_DVI_DTOP_BASE + 0x0F)
#define REG_DVI_DTOP_08_L        (REG_DVI_DTOP_BASE + 0x10)
#define REG_DVI_DTOP_08_H        (REG_DVI_DTOP_BASE + 0x11)
#define REG_DVI_DTOP_09_L        (REG_DVI_DTOP_BASE + 0x12)
#define REG_DVI_DTOP_09_H        (REG_DVI_DTOP_BASE + 0x13)
#define REG_DVI_DTOP_0A_L        (REG_DVI_DTOP_BASE + 0x14)
#define REG_DVI_DTOP_0A_H        (REG_DVI_DTOP_BASE + 0x15)
#define REG_DVI_DTOP_0B_L        (REG_DVI_DTOP_BASE + 0x16)
#define REG_DVI_DTOP_0B_H        (REG_DVI_DTOP_BASE + 0x17)
#define REG_DVI_DTOP_0C_L        (REG_DVI_DTOP_BASE + 0x18)
#define REG_DVI_DTOP_0C_H        (REG_DVI_DTOP_BASE + 0x19)
#define REG_DVI_DTOP_0D_L        (REG_DVI_DTOP_BASE + 0x1A)
#define REG_DVI_DTOP_0D_H        (REG_DVI_DTOP_BASE + 0x1B)
#define REG_DVI_DTOP_0E_L        (REG_DVI_DTOP_BASE + 0x1C)
#define REG_DVI_DTOP_0E_H        (REG_DVI_DTOP_BASE + 0x1D)
#define REG_DVI_DTOP_0F_L        (REG_DVI_DTOP_BASE + 0x1E)
#define REG_DVI_DTOP_0F_H        (REG_DVI_DTOP_BASE + 0x1F)
#define REG_DVI_DTOP_10_L        (REG_DVI_DTOP_BASE + 0x20)
#define REG_DVI_DTOP_10_H        (REG_DVI_DTOP_BASE + 0x21)
#define REG_DVI_DTOP_11_L        (REG_DVI_DTOP_BASE + 0x22)
#define REG_DVI_DTOP_11_H        (REG_DVI_DTOP_BASE + 0x23)
#define REG_DVI_DTOP_12_L        (REG_DVI_DTOP_BASE + 0x24)
#define REG_DVI_DTOP_12_H        (REG_DVI_DTOP_BASE + 0x25)
#define REG_DVI_DTOP_13_L        (REG_DVI_DTOP_BASE + 0x26)
#define REG_DVI_DTOP_13_H        (REG_DVI_DTOP_BASE + 0x27)
#define REG_DVI_DTOP_14_L        (REG_DVI_DTOP_BASE + 0x28)
#define REG_DVI_DTOP_14_H        (REG_DVI_DTOP_BASE + 0x29)
#define REG_DVI_DTOP_15_L        (REG_DVI_DTOP_BASE + 0x2A)
#define REG_DVI_DTOP_15_H        (REG_DVI_DTOP_BASE + 0x2B)
#define REG_DVI_DTOP_16_L        (REG_DVI_DTOP_BASE + 0x2C)
#define REG_DVI_DTOP_16_H        (REG_DVI_DTOP_BASE + 0x2D)
#define REG_DVI_DTOP_17_L        (REG_DVI_DTOP_BASE + 0x2E)
#define REG_DVI_DTOP_17_H        (REG_DVI_DTOP_BASE + 0x2F)
#define REG_DVI_DTOP_18_L        (REG_DVI_DTOP_BASE + 0x30)
#define REG_DVI_DTOP_18_H        (REG_DVI_DTOP_BASE + 0x31)
#define REG_DVI_DTOP_19_L        (REG_DVI_DTOP_BASE + 0x32)
#define REG_DVI_DTOP_19_H        (REG_DVI_DTOP_BASE + 0x33)
#define REG_DVI_DTOP_1A_L        (REG_DVI_DTOP_BASE + 0x34)
#define REG_DVI_DTOP_1A_H        (REG_DVI_DTOP_BASE + 0x35)
#define REG_DVI_DTOP_1B_L        (REG_DVI_DTOP_BASE + 0x36)
#define REG_DVI_DTOP_1B_H        (REG_DVI_DTOP_BASE + 0x37)
#define REG_DVI_DTOP_1C_L        (REG_DVI_DTOP_BASE + 0x38)
#define REG_DVI_DTOP_1C_H        (REG_DVI_DTOP_BASE + 0x39)
#define REG_DVI_DTOP_1D_L        (REG_DVI_DTOP_BASE + 0x3A)
#define REG_DVI_DTOP_1D_H        (REG_DVI_DTOP_BASE + 0x3B)
#define REG_DVI_DTOP_1E_L        (REG_DVI_DTOP_BASE + 0x3C)
#define REG_DVI_DTOP_1E_H        (REG_DVI_DTOP_BASE + 0x3D)
#define REG_DVI_DTOP_1F_L        (REG_DVI_DTOP_BASE + 0x3E)
#define REG_DVI_DTOP_1F_H        (REG_DVI_DTOP_BASE + 0x3F)
#define REG_DVI_DTOP_20_L        (REG_DVI_DTOP_BASE + 0x40)
#define REG_DVI_DTOP_20_H        (REG_DVI_DTOP_BASE + 0x41)
#define REG_DVI_DTOP_21_L        (REG_DVI_DTOP_BASE + 0x42)
#define REG_DVI_DTOP_21_H        (REG_DVI_DTOP_BASE + 0x43)
#define REG_DVI_DTOP_22_L        (REG_DVI_DTOP_BASE + 0x44)
#define REG_DVI_DTOP_22_H        (REG_DVI_DTOP_BASE + 0x45)
#define REG_DVI_DTOP_23_L        (REG_DVI_DTOP_BASE + 0x46)
#define REG_DVI_DTOP_23_H        (REG_DVI_DTOP_BASE + 0x47)
#define REG_DVI_DTOP_24_L        (REG_DVI_DTOP_BASE + 0x48)
#define REG_DVI_DTOP_24_H        (REG_DVI_DTOP_BASE + 0x49)
#define REG_DVI_DTOP_25_L        (REG_DVI_DTOP_BASE + 0x4A)
#define REG_DVI_DTOP_25_H        (REG_DVI_DTOP_BASE + 0x4B)
#define REG_DVI_DTOP_26_L        (REG_DVI_DTOP_BASE + 0x4C)
#define REG_DVI_DTOP_26_H        (REG_DVI_DTOP_BASE + 0x4D)
#define REG_DVI_DTOP_27_L        (REG_DVI_DTOP_BASE + 0x4E)
#define REG_DVI_DTOP_27_H        (REG_DVI_DTOP_BASE + 0x4F)
#define REG_DVI_DTOP_28_L        (REG_DVI_DTOP_BASE + 0x50)
#define REG_DVI_DTOP_28_H        (REG_DVI_DTOP_BASE + 0x51)
#define REG_DVI_DTOP_29_L        (REG_DVI_DTOP_BASE + 0x52)
#define REG_DVI_DTOP_29_H        (REG_DVI_DTOP_BASE + 0x53)
#define REG_DVI_DTOP_2A_L        (REG_DVI_DTOP_BASE + 0x54)
#define REG_DVI_DTOP_2A_H        (REG_DVI_DTOP_BASE + 0x55)
#define REG_DVI_DTOP_2B_L        (REG_DVI_DTOP_BASE + 0x56)
#define REG_DVI_DTOP_2B_H        (REG_DVI_DTOP_BASE + 0x57)
#define REG_DVI_DTOP_2C_L        (REG_DVI_DTOP_BASE + 0x58)
#define REG_DVI_DTOP_2C_H        (REG_DVI_DTOP_BASE + 0x59)
#define REG_DVI_DTOP_2D_L        (REG_DVI_DTOP_BASE + 0x5A)
#define REG_DVI_DTOP_2D_H        (REG_DVI_DTOP_BASE + 0x5B)
#define REG_DVI_DTOP_2E_L        (REG_DVI_DTOP_BASE + 0x5C)
#define REG_DVI_DTOP_2E_H        (REG_DVI_DTOP_BASE + 0x5D)
#define REG_DVI_DTOP_2F_L        (REG_DVI_DTOP_BASE + 0x5E)
#define REG_DVI_DTOP_2F_H        (REG_DVI_DTOP_BASE + 0x5F)
#define REG_DVI_DTOP_30_L        (REG_DVI_DTOP_BASE + 0x60)
#define REG_DVI_DTOP_30_H        (REG_DVI_DTOP_BASE + 0x61)
#define REG_DVI_DTOP_31_L        (REG_DVI_DTOP_BASE + 0x62)
#define REG_DVI_DTOP_31_H        (REG_DVI_DTOP_BASE + 0x63)
#define REG_DVI_DTOP_32_L        (REG_DVI_DTOP_BASE + 0x64)
#define REG_DVI_DTOP_32_H        (REG_DVI_DTOP_BASE + 0x65)
#define REG_DVI_DTOP_33_L        (REG_DVI_DTOP_BASE + 0x66)
#define REG_DVI_DTOP_33_H        (REG_DVI_DTOP_BASE + 0x67)
#define REG_DVI_DTOP_34_L        (REG_DVI_DTOP_BASE + 0x68)
#define REG_DVI_DTOP_34_H        (REG_DVI_DTOP_BASE + 0x69)
#define REG_DVI_DTOP_35_L        (REG_DVI_DTOP_BASE + 0x6A)
#define REG_DVI_DTOP_35_H        (REG_DVI_DTOP_BASE + 0x6B)
#define REG_DVI_DTOP_36_L        (REG_DVI_DTOP_BASE + 0x6C)
#define REG_DVI_DTOP_36_H        (REG_DVI_DTOP_BASE + 0x6D)
#define REG_DVI_DTOP_37_L        (REG_DVI_DTOP_BASE + 0x6E)
#define REG_DVI_DTOP_37_H        (REG_DVI_DTOP_BASE + 0x6F)
#define REG_DVI_DTOP_38_L        (REG_DVI_DTOP_BASE + 0x70)
#define REG_DVI_DTOP_38_H        (REG_DVI_DTOP_BASE + 0x71)
#define REG_DVI_DTOP_39_L        (REG_DVI_DTOP_BASE + 0x72)
#define REG_DVI_DTOP_39_H        (REG_DVI_DTOP_BASE + 0x73)
#define REG_DVI_DTOP_3A_L        (REG_DVI_DTOP_BASE + 0x74)
#define REG_DVI_DTOP_3A_H        (REG_DVI_DTOP_BASE + 0x75)
#define REG_DVI_DTOP_3B_L        (REG_DVI_DTOP_BASE + 0x76)
#define REG_DVI_DTOP_3B_H        (REG_DVI_DTOP_BASE + 0x77)
#define REG_DVI_DTOP_3C_L        (REG_DVI_DTOP_BASE + 0x78)
#define REG_DVI_DTOP_3C_H        (REG_DVI_DTOP_BASE + 0x79)
#define REG_DVI_DTOP_3D_L        (REG_DVI_DTOP_BASE + 0x7A)
#define REG_DVI_DTOP_3D_H        (REG_DVI_DTOP_BASE + 0x7B)
#define REG_DVI_DTOP_3E_L        (REG_DVI_DTOP_BASE + 0x7C)
#define REG_DVI_DTOP_3E_H        (REG_DVI_DTOP_BASE + 0x7D)
#define REG_DVI_DTOP_3F_L        (REG_DVI_DTOP_BASE + 0x7E)
#define REG_DVI_DTOP_3F_H        (REG_DVI_DTOP_BASE + 0x7F)

// DVI DTOP1
#define REG_DVI_DTOP1_00_L        (REG_DVI_DTOP1_BASE + 0x00)
#define REG_DVI_DTOP1_00_H        (REG_DVI_DTOP1_BASE + 0x01)
#define REG_DVI_DTOP1_01_L        (REG_DVI_DTOP1_BASE + 0x02)
#define REG_DVI_DTOP1_01_H        (REG_DVI_DTOP1_BASE + 0x03)
#define REG_DVI_DTOP1_02_L        (REG_DVI_DTOP1_BASE + 0x04)
#define REG_DVI_DTOP1_02_H        (REG_DVI_DTOP1_BASE + 0x05)
#define REG_DVI_DTOP1_03_L        (REG_DVI_DTOP1_BASE + 0x06)
#define REG_DVI_DTOP1_03_H        (REG_DVI_DTOP1_BASE + 0x07)
#define REG_DVI_DTOP1_05_L        (REG_DVI_DTOP1_BASE + 0x0A)
#define REG_DVI_DTOP1_05_H        (REG_DVI_DTOP1_BASE + 0x0B)
#define REG_DVI_DTOP1_0B_L        (REG_DVI_DTOP1_BASE + 0x16)
#define REG_DVI_DTOP1_0B_H        (REG_DVI_DTOP1_BASE + 0x17)
#define REG_DVI_DTOP1_0E_L        (REG_DVI_DTOP1_BASE + 0x1C)
#define REG_DVI_DTOP1_0E_H        (REG_DVI_DTOP1_BASE + 0x1D)
#define REG_DVI_DTOP1_16_L        (REG_DVI_DTOP1_BASE + 0x2C)
#define REG_DVI_DTOP1_16_H        (REG_DVI_DTOP1_BASE + 0x2D)
#define REG_DVI_DTOP1_17_L        (REG_DVI_DTOP1_BASE + 0x2E)
#define REG_DVI_DTOP1_17_H        (REG_DVI_DTOP1_BASE + 0x2F)
#define REG_DVI_DTOP1_19_L        (REG_DVI_DTOP1_BASE + 0x32)
#define REG_DVI_DTOP1_19_H        (REG_DVI_DTOP1_BASE + 0x33)
#define REG_DVI_DTOP1_1E_L        (REG_DVI_DTOP1_BASE + 0x3C)
#define REG_DVI_DTOP1_1E_H        (REG_DVI_DTOP1_BASE + 0x3D)
#define REG_DVI_DTOP1_21_L        (REG_DVI_DTOP1_BASE + 0x42)
#define REG_DVI_DTOP1_21_H        (REG_DVI_DTOP1_BASE + 0x43)
#define REG_DVI_DTOP1_23_L        (REG_DVI_DTOP1_BASE + 0x46)
#define REG_DVI_DTOP1_24_L        (REG_DVI_DTOP1_BASE + 0x48)
#define REG_DVI_DTOP1_24_H        (REG_DVI_DTOP1_BASE + 0x49)
#define REG_DVI_DTOP1_25_L        (REG_DVI_DTOP1_BASE + 0x4A)
#define REG_DVI_DTOP1_25_H        (REG_DVI_DTOP1_BASE + 0x4B)
#define REG_DVI_DTOP1_29_L        (REG_DVI_DTOP1_BASE + 0x52)
#define REG_DVI_DTOP1_29_H        (REG_DVI_DTOP1_BASE + 0x53)
#define REG_DVI_DTOP1_2A_L        (REG_DVI_DTOP1_BASE + 0x54)
#define REG_DVI_DTOP1_2A_H        (REG_DVI_DTOP1_BASE + 0x55)
#define REG_DVI_DTOP1_2F_L        (REG_DVI_DTOP1_BASE + 0x5E)
#define REG_DVI_DTOP1_2F_H        (REG_DVI_DTOP1_BASE + 0x5F)
#define REG_DVI_DTOP1_30_L        (REG_DVI_DTOP1_BASE + 0x60)
#define REG_DVI_DTOP1_30_H        (REG_DVI_DTOP1_BASE + 0x61)
#define REG_DVI_DTOP1_31_L        (REG_DVI_DTOP1_BASE + 0x62)
#define REG_DVI_DTOP1_31_H        (REG_DVI_DTOP1_BASE + 0x63)

// DVI DTOP2
#define REG_DVI_DTOP2_00_L        (REG_DVI_DTOP2_BASE + 0x00)
#define REG_DVI_DTOP2_00_H        (REG_DVI_DTOP2_BASE + 0x01)
#define REG_DVI_DTOP2_01_L        (REG_DVI_DTOP2_BASE + 0x02)
#define REG_DVI_DTOP2_01_H        (REG_DVI_DTOP2_BASE + 0x03)
#define REG_DVI_DTOP2_02_L        (REG_DVI_DTOP2_BASE + 0x04)
#define REG_DVI_DTOP2_02_H        (REG_DVI_DTOP2_BASE + 0x05)
#define REG_DVI_DTOP2_03_L        (REG_DVI_DTOP2_BASE + 0x06)
#define REG_DVI_DTOP2_03_H        (REG_DVI_DTOP2_BASE + 0x07)
#define REG_DVI_DTOP2_05_L        (REG_DVI_DTOP2_BASE + 0x0A)
#define REG_DVI_DTOP2_05_H        (REG_DVI_DTOP2_BASE + 0x0B)
#define REG_DVI_DTOP2_0B_L        (REG_DVI_DTOP2_BASE + 0x16)
#define REG_DVI_DTOP2_0B_H        (REG_DVI_DTOP2_BASE + 0x17)
#define REG_DVI_DTOP2_0E_L        (REG_DVI_DTOP2_BASE + 0x1C)
#define REG_DVI_DTOP2_0E_H        (REG_DVI_DTOP2_BASE + 0x1D)
#define REG_DVI_DTOP2_16_L        (REG_DVI_DTOP2_BASE + 0x2C)
#define REG_DVI_DTOP2_16_H        (REG_DVI_DTOP2_BASE + 0x2D)
#define REG_DVI_DTOP2_17_L        (REG_DVI_DTOP2_BASE + 0x2E)
#define REG_DVI_DTOP2_17_H        (REG_DVI_DTOP2_BASE + 0x2F)
#define REG_DVI_DTOP2_19_L        (REG_DVI_DTOP2_BASE + 0x32)
#define REG_DVI_DTOP2_19_H        (REG_DVI_DTOP2_BASE + 0x33)
#define REG_DVI_DTOP2_20_L        (REG_DVI_DTOP2_BASE + 0x40)
#define REG_DVI_DTOP2_20_H        (REG_DVI_DTOP2_BASE + 0x41)
#define REG_DVI_DTOP2_1E_L        (REG_DVI_DTOP2_BASE + 0x3C)
#define REG_DVI_DTOP2_1E_H        (REG_DVI_DTOP2_BASE + 0x3D)
#define REG_DVI_DTOP2_1F_L        (REG_DVI_DTOP2_BASE + 0x3E)
#define REG_DVI_DTOP2_1F_H        (REG_DVI_DTOP2_BASE + 0x3F)
#define REG_DVI_DTOP2_20_L        (REG_DVI_DTOP2_BASE + 0x40)
#define REG_DVI_DTOP2_20_H        (REG_DVI_DTOP2_BASE + 0x41)
#define REG_DVI_DTOP2_21_L        (REG_DVI_DTOP2_BASE + 0x42)
#define REG_DVI_DTOP2_21_H        (REG_DVI_DTOP2_BASE + 0x43)
#define REG_DVI_DTOP2_23_L        (REG_DVI_DTOP2_BASE + 0x46)
#define REG_DVI_DTOP2_24_L        (REG_DVI_DTOP2_BASE + 0x48)
#define REG_DVI_DTOP2_24_H        (REG_DVI_DTOP2_BASE + 0x49)
#define REG_DVI_DTOP2_25_L        (REG_DVI_DTOP2_BASE + 0x4A)
#define REG_DVI_DTOP2_25_H        (REG_DVI_DTOP2_BASE + 0x4B)
#define REG_DVI_DTOP2_27_L        (REG_DVI_DTOP2_BASE + 0x4E)
#define REG_DVI_DTOP2_27_H        (REG_DVI_DTOP2_BASE + 0x4F)
#define REG_DVI_DTOP2_28_L        (REG_DVI_DTOP2_BASE + 0x50)
#define REG_DVI_DTOP2_28_H        (REG_DVI_DTOP2_BASE + 0x51)
#define REG_DVI_DTOP2_29_L        (REG_DVI_DTOP2_BASE + 0x52)
#define REG_DVI_DTOP2_29_H        (REG_DVI_DTOP2_BASE + 0x53)
#define REG_DVI_DTOP2_2A_L        (REG_DVI_DTOP2_BASE + 0x54)
#define REG_DVI_DTOP2_2A_H        (REG_DVI_DTOP2_BASE + 0x55)
#define REG_DVI_DTOP2_2E_L        (REG_DVI_DTOP2_BASE + 0x5C)
#define REG_DVI_DTOP2_2E_H        (REG_DVI_DTOP2_BASE + 0x5D)
#define REG_DVI_DTOP2_2F_L        (REG_DVI_DTOP2_BASE + 0x5E)
#define REG_DVI_DTOP2_2F_H        (REG_DVI_DTOP2_BASE + 0x5F)
#define REG_DVI_DTOP2_30_L        (REG_DVI_DTOP2_BASE + 0x60)
#define REG_DVI_DTOP2_30_H        (REG_DVI_DTOP2_BASE + 0x61)
#define REG_DVI_DTOP2_31_L        (REG_DVI_DTOP2_BASE + 0x62)
#define REG_DVI_DTOP2_31_H        (REG_DVI_DTOP2_BASE + 0x63)
#define REG_DVI_DTOP2_37_L        (REG_DVI_DTOP2_BASE + 0x6E)
#define REG_DVI_DTOP2_3A_L        (REG_DVI_DTOP2_BASE + 0x74)
#define REG_DVI_DTOP2_3A_H        (REG_DVI_DTOP2_BASE + 0x75)
#define REG_DVI_DTOP2_3B_L        (REG_DVI_DTOP2_BASE + 0x76)
#define REG_DVI_DTOP2_3B_H        (REG_DVI_DTOP2_BASE + 0x77)
#define REG_DVI_DTOP2_3C_L        (REG_DVI_DTOP2_BASE + 0x78)
#define REG_DVI_DTOP2_3C_H        (REG_DVI_DTOP2_BASE + 0x79)
#define REG_DVI_DTOP2_3D_L        (REG_DVI_DTOP2_BASE + 0x7A)
#define REG_DVI_DTOP2_3D_H        (REG_DVI_DTOP2_BASE + 0x7B)
#define REG_DVI_DTOP2_3E_L        (REG_DVI_DTOP2_BASE + 0x7C)
#define REG_DVI_DTOP2_3E_H        (REG_DVI_DTOP2_BASE + 0x7D)
#define REG_DVI_DTOP2_3F_L        (REG_DVI_DTOP2_BASE + 0x7E)
#define REG_DVI_DTOP2_3F_H        (REG_DVI_DTOP2_BASE + 0x7F)

// DVI DTOP3
#define REG_DVI_DTOP3_00_L        (REG_DVI_DTOP3_BASE + 0x00)
#define REG_DVI_DTOP3_00_H        (REG_DVI_DTOP3_BASE + 0x01)
#define REG_DVI_DTOP3_01_L        (REG_DVI_DTOP3_BASE + 0x02)
#define REG_DVI_DTOP3_01_H        (REG_DVI_DTOP3_BASE + 0x03)
#define REG_DVI_DTOP3_02_L        (REG_DVI_DTOP3_BASE + 0x04)
#define REG_DVI_DTOP3_02_H        (REG_DVI_DTOP3_BASE + 0x05)
#define REG_DVI_DTOP3_03_L        (REG_DVI_DTOP3_BASE + 0x06)
#define REG_DVI_DTOP3_03_H        (REG_DVI_DTOP3_BASE + 0x07)
#define REG_DVI_DTOP3_04_L        (REG_DVI_DTOP3_BASE + 0x08)
#define REG_DVI_DTOP3_04_H        (REG_DVI_DTOP3_BASE + 0x09)
#define REG_DVI_DTOP3_05_L        (REG_DVI_DTOP3_BASE + 0x0A)
#define REG_DVI_DTOP3_05_H        (REG_DVI_DTOP3_BASE + 0x0B)
#define REG_DVI_DTOP3_0B_L        (REG_DVI_DTOP3_BASE + 0x16)
#define REG_DVI_DTOP3_0B_H        (REG_DVI_DTOP3_BASE + 0x17)
#define REG_DVI_DTOP3_0C_L        (REG_DVI_DTOP3_BASE + 0x18)
#define REG_DVI_DTOP3_0C_H        (REG_DVI_DTOP3_BASE + 0x19)
#define REG_DVI_DTOP3_0E_L        (REG_DVI_DTOP3_BASE + 0x1C)
#define REG_DVI_DTOP3_0E_H        (REG_DVI_DTOP3_BASE + 0x1D)
#define REG_DVI_DTOP3_16_L        (REG_DVI_DTOP3_BASE + 0x2C)
#define REG_DVI_DTOP3_16_H        (REG_DVI_DTOP3_BASE + 0x2D)
#define REG_DVI_DTOP3_17_L        (REG_DVI_DTOP3_BASE + 0x2E)
#define REG_DVI_DTOP3_17_H        (REG_DVI_DTOP3_BASE + 0x2F)
#define REG_DVI_DTOP3_19_L        (REG_DVI_DTOP3_BASE + 0x32)
#define REG_DVI_DTOP3_19_H        (REG_DVI_DTOP3_BASE + 0x33)
#define REG_DVI_DTOP3_1E_L        (REG_DVI_DTOP3_BASE + 0x3C)
#define REG_DVI_DTOP3_1E_H        (REG_DVI_DTOP3_BASE + 0x3D)
#define REG_DVI_DTOP3_1F_L        (REG_DVI_DTOP3_BASE + 0x3E)
#define REG_DVI_DTOP3_1F_H        (REG_DVI_DTOP3_BASE + 0x3F)
#define REG_DVI_DTOP3_20_L        (REG_DVI_DTOP3_BASE + 0x40)
#define REG_DVI_DTOP3_21_L        (REG_DVI_DTOP3_BASE + 0x42)
#define REG_DVI_DTOP3_21_H        (REG_DVI_DTOP3_BASE + 0x43)
#define REG_DVI_DTOP3_23_L        (REG_DVI_DTOP3_BASE + 0x46)
#define REG_DVI_DTOP3_23_H        (REG_DVI_DTOP3_BASE + 0x47)
#define REG_DVI_DTOP3_24_L        (REG_DVI_DTOP3_BASE + 0x48)
#define REG_DVI_DTOP3_24_H        (REG_DVI_DTOP3_BASE + 0x49)
#define REG_DVI_DTOP3_25_L        (REG_DVI_DTOP3_BASE + 0x4A)
#define REG_DVI_DTOP3_25_H        (REG_DVI_DTOP3_BASE + 0x4B)
#define REG_DVI_DTOP3_27_L        (REG_DVI_DTOP3_BASE + 0x4E)
#define REG_DVI_DTOP3_27_H        (REG_DVI_DTOP3_BASE + 0x4F)
#define REG_DVI_DTOP3_28_L        (REG_DVI_DTOP3_BASE + 0x50)
#define REG_DVI_DTOP3_28_H        (REG_DVI_DTOP3_BASE + 0x51)
#define REG_DVI_DTOP3_29_L        (REG_DVI_DTOP3_BASE + 0x52)
#define REG_DVI_DTOP3_29_H        (REG_DVI_DTOP3_BASE + 0x53)
#define REG_DVI_DTOP3_2A_L        (REG_DVI_DTOP3_BASE + 0x54)
#define REG_DVI_DTOP3_2A_H        (REG_DVI_DTOP3_BASE + 0x55)
#define REG_DVI_DTOP3_2E_L        (REG_DVI_DTOP3_BASE + 0x5C)
#define REG_DVI_DTOP3_2E_H        (REG_DVI_DTOP3_BASE + 0x5D)
#define REG_DVI_DTOP3_2F_L        (REG_DVI_DTOP3_BASE + 0x5E)
#define REG_DVI_DTOP3_2F_H        (REG_DVI_DTOP3_BASE + 0x5F)
#define REG_DVI_DTOP3_30_L        (REG_DVI_DTOP3_BASE + 0x60)
#define REG_DVI_DTOP3_30_H        (REG_DVI_DTOP3_BASE + 0x61)
#define REG_DVI_DTOP3_31_L        (REG_DVI_DTOP3_BASE + 0x62)
#define REG_DVI_DTOP3_31_H        (REG_DVI_DTOP3_BASE + 0x63)
#define REG_DVI_DTOP3_37_L        (REG_DVI_DTOP3_BASE + 0x6E)
#define REG_DVI_DTOP3_37_H        (REG_DVI_DTOP3_BASE + 0x6F)
#define REG_DVI_DTOP3_3A_L        (REG_DVI_DTOP3_BASE + 0x74)
#define REG_DVI_DTOP3_3B_L        (REG_DVI_DTOP3_BASE + 0x76)
#define REG_DVI_DTOP3_3C_L        (REG_DVI_DTOP3_BASE + 0x78)
#define REG_DVI_DTOP3_3D_L        (REG_DVI_DTOP3_BASE + 0x7A)
#define REG_DVI_DTOP3_3E_L        (REG_DVI_DTOP3_BASE + 0x7C)
#define REG_DVI_DTOP3_3E_H        (REG_DVI_DTOP3_BASE + 0x7D)
#define REG_DVI_DTOP3_3F_L        (REG_DVI_DTOP3_BASE + 0x7E)


//=============================================================
// DVI EQ

#define REG_DVI_EQ_00_L        (REG_DVI_EQ_BASE + 0x00)
#define REG_DVI_EQ_00_H        (REG_DVI_EQ_BASE + 0x01)
#define REG_DVI_EQ_01_L        (REG_DVI_EQ_BASE + 0x02)
#define REG_DVI_EQ_01_H        (REG_DVI_EQ_BASE + 0x03)
#define REG_DVI_EQ_02_L        (REG_DVI_EQ_BASE + 0x04)
#define REG_DVI_EQ_02_H        (REG_DVI_EQ_BASE + 0x05)
#define REG_DVI_EQ_03_L        (REG_DVI_EQ_BASE + 0x06)
#define REG_DVI_EQ_03_H        (REG_DVI_EQ_BASE + 0x07)
#define REG_DVI_EQ_04_L        (REG_DVI_EQ_BASE + 0x08)
#define REG_DVI_EQ_04_H        (REG_DVI_EQ_BASE + 0x09)
#define REG_DVI_EQ_05_L        (REG_DVI_EQ_BASE + 0x0A)
#define REG_DVI_EQ_05_H        (REG_DVI_EQ_BASE + 0x0B)
#define REG_DVI_EQ_06_L        (REG_DVI_EQ_BASE + 0x0C)
#define REG_DVI_EQ_06_H        (REG_DVI_EQ_BASE + 0x0D)
#define REG_DVI_EQ_07_L        (REG_DVI_EQ_BASE + 0x0E)
#define REG_DVI_EQ_07_H        (REG_DVI_EQ_BASE + 0x0F)
#define REG_DVI_EQ_08_L        (REG_DVI_EQ_BASE + 0x10)
#define REG_DVI_EQ_08_H        (REG_DVI_EQ_BASE + 0x11)
#define REG_DVI_EQ_09_L        (REG_DVI_EQ_BASE + 0x12)
#define REG_DVI_EQ_09_H        (REG_DVI_EQ_BASE + 0x13)
#define REG_DVI_EQ_0A_L        (REG_DVI_EQ_BASE + 0x14)
#define REG_DVI_EQ_0A_H        (REG_DVI_EQ_BASE + 0x15)
#define REG_DVI_EQ_0B_L        (REG_DVI_EQ_BASE + 0x16)
#define REG_DVI_EQ_0B_H        (REG_DVI_EQ_BASE + 0x17)
#define REG_DVI_EQ_0C_L        (REG_DVI_EQ_BASE + 0x18)
#define REG_DVI_EQ_0C_H        (REG_DVI_EQ_BASE + 0x19)
#define REG_DVI_EQ_0D_L        (REG_DVI_EQ_BASE + 0x1A)
#define REG_DVI_EQ_0D_H        (REG_DVI_EQ_BASE + 0x1B)
#define REG_DVI_EQ_0E_L        (REG_DVI_EQ_BASE + 0x1C)
#define REG_DVI_EQ_0E_H        (REG_DVI_EQ_BASE + 0x1D)
#define REG_DVI_EQ_0F_L        (REG_DVI_EQ_BASE + 0x1E)
#define REG_DVI_EQ_0F_H        (REG_DVI_EQ_BASE + 0x1F)
#define REG_DVI_EQ_10_L        (REG_DVI_EQ_BASE + 0x20)
#define REG_DVI_EQ_10_H        (REG_DVI_EQ_BASE + 0x21)
#define REG_DVI_EQ_11_L        (REG_DVI_EQ_BASE + 0x22)
#define REG_DVI_EQ_11_H        (REG_DVI_EQ_BASE + 0x23)
#define REG_DVI_EQ_12_L        (REG_DVI_EQ_BASE + 0x24)
#define REG_DVI_EQ_12_H        (REG_DVI_EQ_BASE + 0x25)
#define REG_DVI_EQ_13_L        (REG_DVI_EQ_BASE + 0x26)
#define REG_DVI_EQ_13_H        (REG_DVI_EQ_BASE + 0x27)
#define REG_DVI_EQ_14_L        (REG_DVI_EQ_BASE + 0x28)
#define REG_DVI_EQ_14_H        (REG_DVI_EQ_BASE + 0x29)
#define REG_DVI_EQ_15_L        (REG_DVI_EQ_BASE + 0x2A)
#define REG_DVI_EQ_15_H        (REG_DVI_EQ_BASE + 0x2B)
#define REG_DVI_EQ_16_L        (REG_DVI_EQ_BASE + 0x2C)
#define REG_DVI_EQ_16_H        (REG_DVI_EQ_BASE + 0x2D)
#define REG_DVI_EQ_17_L        (REG_DVI_EQ_BASE + 0x2E)
#define REG_DVI_EQ_17_H        (REG_DVI_EQ_BASE + 0x2F)
#define REG_DVI_EQ_18_L        (REG_DVI_EQ_BASE + 0x30)
#define REG_DVI_EQ_18_H        (REG_DVI_EQ_BASE + 0x31)
#define REG_DVI_EQ_19_L        (REG_DVI_EQ_BASE + 0x32)
#define REG_DVI_EQ_19_H        (REG_DVI_EQ_BASE + 0x33)
#define REG_DVI_EQ_1A_L        (REG_DVI_EQ_BASE + 0x34)
#define REG_DVI_EQ_1A_H        (REG_DVI_EQ_BASE + 0x35)
#define REG_DVI_EQ_1B_L        (REG_DVI_EQ_BASE + 0x36)
#define REG_DVI_EQ_1B_H        (REG_DVI_EQ_BASE + 0x37)
#define REG_DVI_EQ_1C_L        (REG_DVI_EQ_BASE + 0x38)
#define REG_DVI_EQ_1C_H        (REG_DVI_EQ_BASE + 0x39)
#define REG_DVI_EQ_1D_L        (REG_DVI_EQ_BASE + 0x3A)
#define REG_DVI_EQ_1D_H        (REG_DVI_EQ_BASE + 0x3B)
#define REG_DVI_EQ_1E_L        (REG_DVI_EQ_BASE + 0x3C)
#define REG_DVI_EQ_1E_H        (REG_DVI_EQ_BASE + 0x3D)
#define REG_DVI_EQ_1F_L        (REG_DVI_EQ_BASE + 0x3E)

// DVI EQ1
#define REG_DVI_EQ1_00_L        (REG_DVI_EQ1_BASE + 0x00)
#define REG_DVI_EQ1_00_H        (REG_DVI_EQ1_BASE + 0x01)
#define REG_DVI_EQ1_01_L        (REG_DVI_EQ1_BASE + 0x02)
#define REG_DVI_EQ1_01_H        (REG_DVI_EQ1_BASE + 0x03)
#define REG_DVI_EQ1_02_L        (REG_DVI_EQ1_BASE + 0x04)
#define REG_DVI_EQ1_02_H        (REG_DVI_EQ1_BASE + 0x05)
#define REG_DVI_EQ1_04_L        (REG_DVI_EQ1_BASE + 0x08)
#define REG_DVI_EQ1_04_H        (REG_DVI_EQ1_BASE + 0x09)
#define REG_DVI_EQ1_10_L        (REG_DVI_EQ1_BASE + 0x20)
#define REG_DVI_EQ1_10_H        (REG_DVI_EQ1_BASE + 0x21)
#define REG_DVI_EQ1_11_L        (REG_DVI_EQ1_BASE + 0x22)
#define REG_DVI_EQ1_11_H        (REG_DVI_EQ1_BASE + 0x23)
#define REG_DVI_EQ1_12_L        (REG_DVI_EQ1_BASE + 0x24)
#define REG_DVI_EQ1_12_H        (REG_DVI_EQ1_BASE + 0x25)
#define REG_DVI_EQ1_17_L        (REG_DVI_EQ1_BASE + 0x2E)
#define REG_DVI_EQ1_17_H        (REG_DVI_EQ1_BASE + 0x2F)

// DVI EQ2
#define REG_DVI_EQ2_00_L        (REG_DVI_EQ2_BASE + 0x00)
#define REG_DVI_EQ2_00_H        (REG_DVI_EQ2_BASE + 0x01)
#define REG_DVI_EQ2_01_L        (REG_DVI_EQ2_BASE + 0x02)
#define REG_DVI_EQ2_01_H        (REG_DVI_EQ2_BASE + 0x03)
#define REG_DVI_EQ2_02_L        (REG_DVI_EQ2_BASE + 0x04)
#define REG_DVI_EQ2_02_H        (REG_DVI_EQ2_BASE + 0x05)
#define REG_DVI_EQ2_04_L        (REG_DVI_EQ2_BASE + 0x08)
#define REG_DVI_EQ2_04_H        (REG_DVI_EQ2_BASE + 0x09)
#define REG_DVI_EQ2_10_L        (REG_DVI_EQ2_BASE + 0x20)
#define REG_DVI_EQ2_10_H        (REG_DVI_EQ2_BASE + 0x21)
#define REG_DVI_EQ2_11_L        (REG_DVI_EQ2_BASE + 0x22)
#define REG_DVI_EQ2_11_H        (REG_DVI_EQ2_BASE + 0x23)
#define REG_DVI_EQ2_12_L        (REG_DVI_EQ2_BASE + 0x24)
#define REG_DVI_EQ2_12_H        (REG_DVI_EQ2_BASE + 0x25)
#define REG_DVI_EQ2_17_L        (REG_DVI_EQ2_BASE + 0x2E)
#define REG_DVI_EQ2_17_H        (REG_DVI_EQ2_BASE + 0x2F)

// DVI EQ3
#define REG_DVI_EQ3_00_L        (REG_DVI_EQ3_BASE + 0x00)
#define REG_DVI_EQ3_00_H        (REG_DVI_EQ3_BASE + 0x01)
#define REG_DVI_EQ3_01_L        (REG_DVI_EQ3_BASE + 0x02)
#define REG_DVI_EQ3_01_H        (REG_DVI_EQ3_BASE + 0x03)
#define REG_DVI_EQ3_02_L        (REG_DVI_EQ3_BASE + 0x04)
#define REG_DVI_EQ3_02_H        (REG_DVI_EQ3_BASE + 0x05)
#define REG_DVI_EQ3_04_L        (REG_DVI_EQ3_BASE + 0x08)
#define REG_DVI_EQ3_04_H        (REG_DVI_EQ3_BASE + 0x09)
#define REG_DVI_EQ3_10_L        (REG_DVI_EQ3_BASE + 0x20)
#define REG_DVI_EQ3_10_H        (REG_DVI_EQ3_BASE + 0x21)
#define REG_DVI_EQ3_11_L        (REG_DVI_EQ3_BASE + 0x22)
#define REG_DVI_EQ3_11_H        (REG_DVI_EQ3_BASE + 0x23)
#define REG_DVI_EQ3_12_L        (REG_DVI_EQ3_BASE + 0x24)
#define REG_DVI_EQ3_12_H        (REG_DVI_EQ3_BASE + 0x25)
#define REG_DVI_EQ3_17_L        (REG_DVI_EQ3_BASE + 0x2E)
#define REG_DVI_EQ3_17_H        (REG_DVI_EQ3_BASE + 0x2F)

//=============================================================
// DVI ATOP

#define REG_DVI_ATOP_00_L        (REG_DVI_ATOP_BASE + 0x00)
#define REG_DVI_ATOP_00_H        (REG_DVI_ATOP_BASE + 0x01)
#define REG_DVI_ATOP_01_L        (REG_DVI_ATOP_BASE + 0x02)
#define REG_DVI_ATOP_01_H        (REG_DVI_ATOP_BASE + 0x03)
#define REG_DVI_ATOP_02_L        (REG_DVI_ATOP_BASE + 0x04)
#define REG_DVI_ATOP_02_H        (REG_DVI_ATOP_BASE + 0x05)
#define REG_DVI_ATOP_03_L        (REG_DVI_ATOP_BASE + 0x06)
#define REG_DVI_ATOP_03_H        (REG_DVI_ATOP_BASE + 0x07)
#define REG_DVI_ATOP_04_L        (REG_DVI_ATOP_BASE + 0x08)
#define REG_DVI_ATOP_04_H        (REG_DVI_ATOP_BASE + 0x09)
#define REG_DVI_ATOP_05_L        (REG_DVI_ATOP_BASE + 0x0A)
#define REG_DVI_ATOP_05_H        (REG_DVI_ATOP_BASE + 0x0B)
#define REG_DVI_ATOP_06_L        (REG_DVI_ATOP_BASE + 0x0C)
#define REG_DVI_ATOP_06_H        (REG_DVI_ATOP_BASE + 0x0D)
#define REG_DVI_ATOP_07_L        (REG_DVI_ATOP_BASE + 0x0E)
#define REG_DVI_ATOP_07_H        (REG_DVI_ATOP_BASE + 0x0F)
#define REG_DVI_ATOP_08_L        (REG_DVI_ATOP_BASE + 0x10)
#define REG_DVI_ATOP_08_H        (REG_DVI_ATOP_BASE + 0x11)
#define REG_DVI_ATOP_09_L        (REG_DVI_ATOP_BASE + 0x12)
#define REG_DVI_ATOP_09_H        (REG_DVI_ATOP_BASE + 0x13)
#define REG_DVI_ATOP_0A_L        (REG_DVI_ATOP_BASE + 0x14)
#define REG_DVI_ATOP_0A_H        (REG_DVI_ATOP_BASE + 0x15)
#define REG_DVI_ATOP_0B_L        (REG_DVI_ATOP_BASE + 0x16)
#define REG_DVI_ATOP_0B_H        (REG_DVI_ATOP_BASE + 0x17)
#define REG_DVI_ATOP_0C_L        (REG_DVI_ATOP_BASE + 0x18)
#define REG_DVI_ATOP_0C_H        (REG_DVI_ATOP_BASE + 0x19)
#define REG_DVI_ATOP_0D_L        (REG_DVI_ATOP_BASE + 0x1A)
#define REG_DVI_ATOP_0D_H        (REG_DVI_ATOP_BASE + 0x1B)
#define REG_DVI_ATOP_0E_L        (REG_DVI_ATOP_BASE + 0x1C)
#define REG_DVI_ATOP_0E_H        (REG_DVI_ATOP_BASE + 0x1D)
#define REG_DVI_ATOP_0F_L        (REG_DVI_ATOP_BASE + 0x1E)
#define REG_DVI_ATOP_0F_H        (REG_DVI_ATOP_BASE + 0x1F)
#define REG_DVI_ATOP_10_L        (REG_DVI_ATOP_BASE + 0x20)
#define REG_DVI_ATOP_10_H        (REG_DVI_ATOP_BASE + 0x21)
#define REG_DVI_ATOP_11_L        (REG_DVI_ATOP_BASE + 0x22)
#define REG_DVI_ATOP_11_H        (REG_DVI_ATOP_BASE + 0x23)
#define REG_DVI_ATOP_12_L        (REG_DVI_ATOP_BASE + 0x24)
#define REG_DVI_ATOP_12_H        (REG_DVI_ATOP_BASE + 0x25)
#define REG_DVI_ATOP_13_L        (REG_DVI_ATOP_BASE + 0x26)
#define REG_DVI_ATOP_13_H        (REG_DVI_ATOP_BASE + 0x27)
#define REG_DVI_ATOP_14_L        (REG_DVI_ATOP_BASE + 0x28)
#define REG_DVI_ATOP_14_H        (REG_DVI_ATOP_BASE + 0x29)
#define REG_DVI_ATOP_15_L        (REG_DVI_ATOP_BASE + 0x2A)
#define REG_DVI_ATOP_15_H        (REG_DVI_ATOP_BASE + 0x2B)
#define REG_DVI_ATOP_16_L        (REG_DVI_ATOP_BASE + 0x2C)
#define REG_DVI_ATOP_16_H        (REG_DVI_ATOP_BASE + 0x2D)
#define REG_DVI_ATOP_17_L        (REG_DVI_ATOP_BASE + 0x2E)
#define REG_DVI_ATOP_17_H        (REG_DVI_ATOP_BASE + 0x2F)
#define REG_DVI_ATOP_18_L        (REG_DVI_ATOP_BASE + 0x30)
#define REG_DVI_ATOP_18_H        (REG_DVI_ATOP_BASE + 0x31)
#define REG_DVI_ATOP_19_L        (REG_DVI_ATOP_BASE + 0x32)
#define REG_DVI_ATOP_19_H        (REG_DVI_ATOP_BASE + 0x33)
#define REG_DVI_ATOP_1A_L        (REG_DVI_ATOP_BASE + 0x34)
#define REG_DVI_ATOP_1A_H        (REG_DVI_ATOP_BASE + 0x35)
#define REG_DVI_ATOP_1B_L        (REG_DVI_ATOP_BASE + 0x36)
#define REG_DVI_ATOP_1B_H        (REG_DVI_ATOP_BASE + 0x37)
#define REG_DVI_ATOP_1C_L        (REG_DVI_ATOP_BASE + 0x38)
#define REG_DVI_ATOP_1C_H        (REG_DVI_ATOP_BASE + 0x39)
#define REG_DVI_ATOP_1D_L        (REG_DVI_ATOP_BASE + 0x3A)
#define REG_DVI_ATOP_1D_H        (REG_DVI_ATOP_BASE + 0x3B)
#define REG_DVI_ATOP_1E_L        (REG_DVI_ATOP_BASE + 0x3C)
#define REG_DVI_ATOP_1E_H        (REG_DVI_ATOP_BASE + 0x3D)
#define REG_DVI_ATOP_1F_L        (REG_DVI_ATOP_BASE + 0x3E)
#define REG_DVI_ATOP_1F_H        (REG_DVI_ATOP_BASE + 0x3F)
#define REG_DVI_ATOP_20_L        (REG_DVI_ATOP_BASE + 0x40)
#define REG_DVI_ATOP_20_H        (REG_DVI_ATOP_BASE + 0x41)
#define REG_DVI_ATOP_21_L        (REG_DVI_ATOP_BASE + 0x42)
#define REG_DVI_ATOP_21_H        (REG_DVI_ATOP_BASE + 0x43)
#define REG_DVI_ATOP_22_L        (REG_DVI_ATOP_BASE + 0x44)
#define REG_DVI_ATOP_22_H        (REG_DVI_ATOP_BASE + 0x45)
#define REG_DVI_ATOP_23_L        (REG_DVI_ATOP_BASE + 0x46)
#define REG_DVI_ATOP_23_H        (REG_DVI_ATOP_BASE + 0x47)
#define REG_DVI_ATOP_24_L        (REG_DVI_ATOP_BASE + 0x48)
#define REG_DVI_ATOP_24_H        (REG_DVI_ATOP_BASE + 0x49)
#define REG_DVI_ATOP_25_L        (REG_DVI_ATOP_BASE + 0x4A)
#define REG_DVI_ATOP_25_H        (REG_DVI_ATOP_BASE + 0x4B)
#define REG_DVI_ATOP_26_L        (REG_DVI_ATOP_BASE + 0x4C)
#define REG_DVI_ATOP_26_H        (REG_DVI_ATOP_BASE + 0x4D)
#define REG_DVI_ATOP_27_L        (REG_DVI_ATOP_BASE + 0x4E)
#define REG_DVI_ATOP_27_H        (REG_DVI_ATOP_BASE + 0x4F)
#define REG_DVI_ATOP_28_L        (REG_DVI_ATOP_BASE + 0x50)
#define REG_DVI_ATOP_28_H        (REG_DVI_ATOP_BASE + 0x51)
#define REG_DVI_ATOP_29_L        (REG_DVI_ATOP_BASE + 0x52)
#define REG_DVI_ATOP_29_H        (REG_DVI_ATOP_BASE + 0x53)
#define REG_DVI_ATOP_2A_L        (REG_DVI_ATOP_BASE + 0x54)
#define REG_DVI_ATOP_2A_H        (REG_DVI_ATOP_BASE + 0x55)
#define REG_DVI_ATOP_2B_L        (REG_DVI_ATOP_BASE + 0x56)
#define REG_DVI_ATOP_2B_H        (REG_DVI_ATOP_BASE + 0x57)
#define REG_DVI_ATOP_2C_L        (REG_DVI_ATOP_BASE + 0x58)
#define REG_DVI_ATOP_2C_H        (REG_DVI_ATOP_BASE + 0x59)
#define REG_DVI_ATOP_2D_L        (REG_DVI_ATOP_BASE + 0x5A)
#define REG_DVI_ATOP_2D_H        (REG_DVI_ATOP_BASE + 0x5B)
#define REG_DVI_ATOP_2E_L        (REG_DVI_ATOP_BASE + 0x5C)
#define REG_DVI_ATOP_2E_H        (REG_DVI_ATOP_BASE + 0x5D)
#define REG_DVI_ATOP_2F_L        (REG_DVI_ATOP_BASE + 0x5E)
#define REG_DVI_ATOP_2F_H        (REG_DVI_ATOP_BASE + 0x5F)
#define REG_DVI_ATOP_30_L        (REG_DVI_ATOP_BASE + 0x60)
#define REG_DVI_ATOP_30_H        (REG_DVI_ATOP_BASE + 0x61)
#define REG_DVI_ATOP_31_L        (REG_DVI_ATOP_BASE + 0x62)
#define REG_DVI_ATOP_31_H        (REG_DVI_ATOP_BASE + 0x63)
#define REG_DVI_ATOP_32_L        (REG_DVI_ATOP_BASE + 0x64)
#define REG_DVI_ATOP_32_H        (REG_DVI_ATOP_BASE + 0x65)
#define REG_DVI_ATOP_33_L        (REG_DVI_ATOP_BASE + 0x66)
#define REG_DVI_ATOP_33_H        (REG_DVI_ATOP_BASE + 0x67)
#define REG_DVI_ATOP_34_L        (REG_DVI_ATOP_BASE + 0x68)
#define REG_DVI_ATOP_34_H        (REG_DVI_ATOP_BASE + 0x69)
#define REG_DVI_ATOP_35_L        (REG_DVI_ATOP_BASE + 0x6A)
#define REG_DVI_ATOP_35_H        (REG_DVI_ATOP_BASE + 0x6B)
#define REG_DVI_ATOP_36_L        (REG_DVI_ATOP_BASE + 0x6C)
#define REG_DVI_ATOP_36_H        (REG_DVI_ATOP_BASE + 0x6D)
#define REG_DVI_ATOP_37_L        (REG_DVI_ATOP_BASE + 0x6E)
#define REG_DVI_ATOP_37_H        (REG_DVI_ATOP_BASE + 0x6F)
#define REG_DVI_ATOP_38_L        (REG_DVI_ATOP_BASE + 0x70)
#define REG_DVI_ATOP_38_H        (REG_DVI_ATOP_BASE + 0x71)
#define REG_DVI_ATOP_39_L        (REG_DVI_ATOP_BASE + 0x72)
#define REG_DVI_ATOP_39_H        (REG_DVI_ATOP_BASE + 0x73)
#define REG_DVI_ATOP_3A_L        (REG_DVI_ATOP_BASE + 0x74)
#define REG_DVI_ATOP_3A_H        (REG_DVI_ATOP_BASE + 0x75)
#define REG_DVI_ATOP_3B_L        (REG_DVI_ATOP_BASE + 0x76)
#define REG_DVI_ATOP_3B_H        (REG_DVI_ATOP_BASE + 0x77)
#define REG_DVI_ATOP_3C_L        (REG_DVI_ATOP_BASE + 0x78)
#define REG_DVI_ATOP_3C_H        (REG_DVI_ATOP_BASE + 0x79)
#define REG_DVI_ATOP_3D_L        (REG_DVI_ATOP_BASE + 0x7A)
#define REG_DVI_ATOP_3D_H        (REG_DVI_ATOP_BASE + 0x7B)
#define REG_DVI_ATOP_3E_L        (REG_DVI_ATOP_BASE + 0x7C)
#define REG_DVI_ATOP_3E_H        (REG_DVI_ATOP_BASE + 0x7D)
#define REG_DVI_ATOP_3F_L        (REG_DVI_ATOP_BASE + 0x7E)
#define REG_DVI_ATOP_3F_H        (REG_DVI_ATOP_BASE + 0x7F)
#define REG_DVI_ATOP_40_L        (REG_DVI_ATOP_BASE + 0x80)
#define REG_DVI_ATOP_40_H        (REG_DVI_ATOP_BASE + 0x81)
#define REG_DVI_ATOP_41_L        (REG_DVI_ATOP_BASE + 0x82)
#define REG_DVI_ATOP_41_H        (REG_DVI_ATOP_BASE + 0x83)
#define REG_DVI_ATOP_42_L        (REG_DVI_ATOP_BASE + 0x84)
#define REG_DVI_ATOP_42_H        (REG_DVI_ATOP_BASE + 0x85)
#define REG_DVI_ATOP_43_L        (REG_DVI_ATOP_BASE + 0x86)
#define REG_DVI_ATOP_43_H        (REG_DVI_ATOP_BASE + 0x87)
#define REG_DVI_ATOP_44_L        (REG_DVI_ATOP_BASE + 0x88)
#define REG_DVI_ATOP_44_H        (REG_DVI_ATOP_BASE + 0x89)
#define REG_DVI_ATOP_45_L        (REG_DVI_ATOP_BASE + 0x8A)
#define REG_DVI_ATOP_45_H        (REG_DVI_ATOP_BASE + 0x8B)
#define REG_DVI_ATOP_46_L        (REG_DVI_ATOP_BASE + 0x8C)
#define REG_DVI_ATOP_46_H        (REG_DVI_ATOP_BASE + 0x8D)
#define REG_DVI_ATOP_47_L        (REG_DVI_ATOP_BASE + 0x8E)
#define REG_DVI_ATOP_47_H        (REG_DVI_ATOP_BASE + 0x8F)
#define REG_DVI_ATOP_48_L        (REG_DVI_ATOP_BASE + 0x90)
#define REG_DVI_ATOP_48_H        (REG_DVI_ATOP_BASE + 0x91)
#define REG_DVI_ATOP_49_L        (REG_DVI_ATOP_BASE + 0x92)
#define REG_DVI_ATOP_49_H        (REG_DVI_ATOP_BASE + 0x93)
#define REG_DVI_ATOP_4A_L        (REG_DVI_ATOP_BASE + 0x94)
#define REG_DVI_ATOP_4A_H        (REG_DVI_ATOP_BASE + 0x95)
#define REG_DVI_ATOP_4B_L        (REG_DVI_ATOP_BASE + 0x96)
#define REG_DVI_ATOP_4B_H        (REG_DVI_ATOP_BASE + 0x97)
#define REG_DVI_ATOP_4C_L        (REG_DVI_ATOP_BASE + 0x98)
#define REG_DVI_ATOP_4C_H        (REG_DVI_ATOP_BASE + 0x99)
#define REG_DVI_ATOP_4D_L        (REG_DVI_ATOP_BASE + 0x9A)
#define REG_DVI_ATOP_4D_H        (REG_DVI_ATOP_BASE + 0x9B)
#define REG_DVI_ATOP_4E_L        (REG_DVI_ATOP_BASE + 0x9C)
#define REG_DVI_ATOP_4E_H        (REG_DVI_ATOP_BASE + 0x9D)
#define REG_DVI_ATOP_4F_L        (REG_DVI_ATOP_BASE + 0x9E)
#define REG_DVI_ATOP_4F_H        (REG_DVI_ATOP_BASE + 0x9F)
#define REG_DVI_ATOP_50_L        (REG_DVI_ATOP_BASE + 0xA0)
#define REG_DVI_ATOP_50_H        (REG_DVI_ATOP_BASE + 0xA1)
#define REG_DVI_ATOP_51_L        (REG_DVI_ATOP_BASE + 0xA2)
#define REG_DVI_ATOP_51_H        (REG_DVI_ATOP_BASE + 0xA3)
#define REG_DVI_ATOP_52_L        (REG_DVI_ATOP_BASE + 0xA4)
#define REG_DVI_ATOP_52_H        (REG_DVI_ATOP_BASE + 0xA5)
#define REG_DVI_ATOP_53_L        (REG_DVI_ATOP_BASE + 0xA6)
#define REG_DVI_ATOP_53_H        (REG_DVI_ATOP_BASE + 0xA7)
#define REG_DVI_ATOP_54_L        (REG_DVI_ATOP_BASE + 0xA8)
#define REG_DVI_ATOP_54_H        (REG_DVI_ATOP_BASE + 0xA9)
#define REG_DVI_ATOP_55_L        (REG_DVI_ATOP_BASE + 0xAA)
#define REG_DVI_ATOP_55_H        (REG_DVI_ATOP_BASE + 0xAB)
#define REG_DVI_ATOP_56_L        (REG_DVI_ATOP_BASE + 0xAC)
#define REG_DVI_ATOP_56_H        (REG_DVI_ATOP_BASE + 0xAD)
#define REG_DVI_ATOP_57_L        (REG_DVI_ATOP_BASE + 0xAE)
#define REG_DVI_ATOP_57_H        (REG_DVI_ATOP_BASE + 0xAF)
#define REG_DVI_ATOP_58_L        (REG_DVI_ATOP_BASE + 0xB0)
#define REG_DVI_ATOP_58_H        (REG_DVI_ATOP_BASE + 0xB1)
#define REG_DVI_ATOP_59_L        (REG_DVI_ATOP_BASE + 0xB2)
#define REG_DVI_ATOP_59_H        (REG_DVI_ATOP_BASE + 0xB3)
#define REG_DVI_ATOP_5A_L        (REG_DVI_ATOP_BASE + 0xB4)
#define REG_DVI_ATOP_5A_H        (REG_DVI_ATOP_BASE + 0xB5)
#define REG_DVI_ATOP_5B_L        (REG_DVI_ATOP_BASE + 0xB6)
#define REG_DVI_ATOP_5B_H        (REG_DVI_ATOP_BASE + 0xB7)
#define REG_DVI_ATOP_5C_L        (REG_DVI_ATOP_BASE + 0xB8)
#define REG_DVI_ATOP_5C_H        (REG_DVI_ATOP_BASE + 0xB9)
#define REG_DVI_ATOP_5D_L        (REG_DVI_ATOP_BASE + 0xBA)
#define REG_DVI_ATOP_5D_H        (REG_DVI_ATOP_BASE + 0xBB)
#define REG_DVI_ATOP_5E_L        (REG_DVI_ATOP_BASE + 0xBC)
#define REG_DVI_ATOP_5E_H        (REG_DVI_ATOP_BASE + 0xBD)
#define REG_DVI_ATOP_5F_L        (REG_DVI_ATOP_BASE + 0xBE)
#define REG_DVI_ATOP_5F_H        (REG_DVI_ATOP_BASE + 0xBF)
#define REG_DVI_ATOP_60_L        (REG_DVI_ATOP_BASE + 0xC0)
#define REG_DVI_ATOP_60_H        (REG_DVI_ATOP_BASE + 0xC1)
#define REG_DVI_ATOP_61_L        (REG_DVI_ATOP_BASE + 0xC2)
#define REG_DVI_ATOP_61_H        (REG_DVI_ATOP_BASE + 0xC3)
#define REG_DVI_ATOP_62_L        (REG_DVI_ATOP_BASE + 0xC4)
#define REG_DVI_ATOP_62_H        (REG_DVI_ATOP_BASE + 0xC5)
#define REG_DVI_ATOP_63_L        (REG_DVI_ATOP_BASE + 0xC6)
#define REG_DVI_ATOP_63_H        (REG_DVI_ATOP_BASE + 0xC7)
#define REG_DVI_ATOP_64_L        (REG_DVI_ATOP_BASE + 0xC8)
#define REG_DVI_ATOP_64_H        (REG_DVI_ATOP_BASE + 0xC9)
#define REG_DVI_ATOP_65_L        (REG_DVI_ATOP_BASE + 0xCA)
#define REG_DVI_ATOP_65_H        (REG_DVI_ATOP_BASE + 0xCB)
#define REG_DVI_ATOP_66_L        (REG_DVI_ATOP_BASE + 0xCC)
#define REG_DVI_ATOP_66_H        (REG_DVI_ATOP_BASE + 0xCD)
#define REG_DVI_ATOP_67_L        (REG_DVI_ATOP_BASE + 0xCE)
#define REG_DVI_ATOP_67_H        (REG_DVI_ATOP_BASE + 0xCF)
#define REG_DVI_ATOP_68_L        (REG_DVI_ATOP_BASE + 0xD0)
#define REG_DVI_ATOP_68_H        (REG_DVI_ATOP_BASE + 0xD1)
#define REG_DVI_ATOP_69_L        (REG_DVI_ATOP_BASE + 0xD2)
#define REG_DVI_ATOP_69_H        (REG_DVI_ATOP_BASE + 0xD3)
#define REG_DVI_ATOP_6A_L        (REG_DVI_ATOP_BASE + 0xD4)
#define REG_DVI_ATOP_6A_H        (REG_DVI_ATOP_BASE + 0xD5)
#define REG_DVI_ATOP_6B_L        (REG_DVI_ATOP_BASE + 0xD6)
#define REG_DVI_ATOP_6B_H        (REG_DVI_ATOP_BASE + 0xD7)
#define REG_DVI_ATOP_6C_L        (REG_DVI_ATOP_BASE + 0xD8)
#define REG_DVI_ATOP_6C_H        (REG_DVI_ATOP_BASE + 0xD9)
#define REG_DVI_ATOP_6D_L        (REG_DVI_ATOP_BASE + 0xDA)
#define REG_DVI_ATOP_6D_H        (REG_DVI_ATOP_BASE + 0xDB)
#define REG_DVI_ATOP_6E_L        (REG_DVI_ATOP_BASE + 0xDC)
#define REG_DVI_ATOP_6E_H        (REG_DVI_ATOP_BASE + 0xDD)
#define REG_DVI_ATOP_6F_L        (REG_DVI_ATOP_BASE + 0xDE)
#define REG_DVI_ATOP_6F_H        (REG_DVI_ATOP_BASE + 0xDF)
#define REG_DVI_ATOP_70_L        (REG_DVI_ATOP_BASE + 0xE0)
#define REG_DVI_ATOP_70_H        (REG_DVI_ATOP_BASE + 0xE1)
#define REG_DVI_ATOP_71_L        (REG_DVI_ATOP_BASE + 0xE2)
#define REG_DVI_ATOP_71_H        (REG_DVI_ATOP_BASE + 0xE3)
#define REG_DVI_ATOP_72_L        (REG_DVI_ATOP_BASE + 0xE4)
#define REG_DVI_ATOP_72_H        (REG_DVI_ATOP_BASE + 0xE5)
#define REG_DVI_ATOP_73_L        (REG_DVI_ATOP_BASE + 0xE6)
#define REG_DVI_ATOP_73_H        (REG_DVI_ATOP_BASE + 0xE7)
#define REG_DVI_ATOP_74_L        (REG_DVI_ATOP_BASE + 0xE8)
#define REG_DVI_ATOP_74_H        (REG_DVI_ATOP_BASE + 0xE9)
#define REG_DVI_ATOP_75_L        (REG_DVI_ATOP_BASE + 0xEA)
#define REG_DVI_ATOP_75_H        (REG_DVI_ATOP_BASE + 0xEB)
#define REG_DVI_ATOP_76_L        (REG_DVI_ATOP_BASE + 0xEC)
#define REG_DVI_ATOP_76_H        (REG_DVI_ATOP_BASE + 0xED)
#define REG_DVI_ATOP_77_L        (REG_DVI_ATOP_BASE + 0xEE)
#define REG_DVI_ATOP_77_H        (REG_DVI_ATOP_BASE + 0xEF)
#define REG_DVI_ATOP_78_L        (REG_DVI_ATOP_BASE + 0xF0)
#define REG_DVI_ATOP_78_H        (REG_DVI_ATOP_BASE + 0xF1)
#define REG_DVI_ATOP_79_L        (REG_DVI_ATOP_BASE + 0xF2)
#define REG_DVI_ATOP_79_H        (REG_DVI_ATOP_BASE + 0xF3)
#define REG_DVI_ATOP_7A_L        (REG_DVI_ATOP_BASE + 0xF4)
#define REG_DVI_ATOP_7A_H        (REG_DVI_ATOP_BASE + 0xF5)
#define REG_DVI_ATOP_7B_L        (REG_DVI_ATOP_BASE + 0xF6)
#define REG_DVI_ATOP_7B_H        (REG_DVI_ATOP_BASE + 0xF7)
#define REG_DVI_ATOP_7C_L        (REG_DVI_ATOP_BASE + 0xF8)
#define REG_DVI_ATOP_7C_H        (REG_DVI_ATOP_BASE + 0xF9)
#define REG_DVI_ATOP_7D_L        (REG_DVI_ATOP_BASE + 0xFA)
#define REG_DVI_ATOP_7D_H        (REG_DVI_ATOP_BASE + 0xFB)
#define REG_DVI_ATOP_7E_L        (REG_DVI_ATOP_BASE + 0xFC)
#define REG_DVI_ATOP_7E_H        (REG_DVI_ATOP_BASE + 0xFD)
#define REG_DVI_ATOP_7F_L        (REG_DVI_ATOP_BASE + 0xFE)
#define REG_DVI_ATOP_7F_H        (REG_DVI_ATOP_BASE + 0xFF)

// DVI ATOP1
#define REG_DVI_ATOP1_00_L        (REG_DVI_ATOP1_BASE + 0x00)
#define REG_DVI_ATOP1_00_H        (REG_DVI_ATOP1_BASE + 0x01)
#define REG_DVI_ATOP1_06_L        (REG_DVI_ATOP1_BASE + 0x0C)
#define REG_DVI_ATOP1_06_H        (REG_DVI_ATOP1_BASE + 0x0D)
#define REG_DVI_ATOP1_07_L        (REG_DVI_ATOP1_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
#define REG_DVI_ATOP1_32_L        (REG_DVI_ATOP1_BASE + 0x64)
#define REG_DVI_ATOP1_32_H        (REG_DVI_ATOP1_BASE + 0x65)
#define REG_DVI_ATOP1_5E_L        (REG_DVI_ATOP1_BASE + 0xBC)
#define REG_DVI_ATOP1_5E_H        (REG_DVI_ATOP1_BASE + 0xBD)
#define REG_DVI_ATOP1_60_L        (REG_DVI_ATOP1_BASE + 0xC0)
#define REG_DVI_ATOP1_60_H        (REG_DVI_ATOP1_BASE + 0xC1)
#define REG_DVI_ATOP1_61_L        (REG_DVI_ATOP1_BASE + 0xC2)
#define REG_DVI_ATOP1_61_H        (REG_DVI_ATOP1_BASE + 0xC3)
#define REG_DVI_ATOP1_62_L        (REG_DVI_ATOP1_BASE + 0xC4)
#define REG_DVI_ATOP1_63_L        (REG_DVI_ATOP1_BASE + 0xC6)
#define REG_DVI_ATOP1_63_H        (REG_DVI_ATOP1_BASE + 0xC7)
#define REG_DVI_ATOP1_64_L        (REG_DVI_ATOP1_BASE + 0xC8)

#define REG_DVI_ATOP1_65_L        (REG_DVI_ATOP1_BASE + 0xCA)
#define REG_DVI_ATOP1_67_L        (REG_DVI_ATOP1_BASE + 0xCE)
#define REG_DVI_ATOP1_68_L        (REG_DVI_ATOP1_BASE + 0xD0)
#define REG_DVI_ATOP1_68_H        (REG_DVI_ATOP1_BASE + 0xD1)

#define REG_DVI_ATOP1_70_L        (REG_DVI_ATOP1_BASE + 0xE0)
#define REG_DVI_ATOP1_70_H        (REG_DVI_ATOP1_BASE + 0xE1)
#define REG_DVI_ATOP1_71_L        (REG_DVI_ATOP1_BASE + 0xE2)
#define REG_DVI_ATOP1_71_H        (REG_DVI_ATOP1_BASE + 0xE3)
#define REG_DVI_ATOP1_74_L        (REG_DVI_ATOP1_BASE + 0xE8)

// DVI ATOP2
#define REG_DVI_ATOP2_00_L        (REG_DVI_ATOP2_BASE + 0x00)
#define REG_DVI_ATOP2_00_H        (REG_DVI_ATOP2_BASE + 0x01)
#define REG_DVI_ATOP2_06_L        (REG_DVI_ATOP2_BASE + 0x0C)
#define REG_DVI_ATOP2_06_H        (REG_DVI_ATOP2_BASE + 0x0D)
#define REG_DVI_ATOP2_07_L        (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
#define REG_DVI_ATOP2_32_L        (REG_DVI_ATOP2_BASE + 0x64)
#define REG_DVI_ATOP2_32_H        (REG_DVI_ATOP2_BASE + 0x65)
#define REG_DVI_ATOP2_5E_L        (REG_DVI_ATOP2_BASE + 0xBC)
#define REG_DVI_ATOP2_5E_H        (REG_DVI_ATOP2_BASE + 0xBD)
#define REG_DVI_ATOP2_60_L        (REG_DVI_ATOP2_BASE + 0xC0)
#define REG_DVI_ATOP2_60_H        (REG_DVI_ATOP2_BASE + 0xC1)
#define REG_DVI_ATOP2_61_L        (REG_DVI_ATOP2_BASE + 0xC2)
#define REG_DVI_ATOP2_61_H        (REG_DVI_ATOP2_BASE + 0xC3)
#define REG_DVI_ATOP2_62_L        (REG_DVI_ATOP2_BASE + 0xC4)
#define REG_DVI_ATOP2_62_H        (REG_DVI_ATOP2_BASE + 0xC5)
#define REG_DVI_ATOP2_63_L        (REG_DVI_ATOP2_BASE + 0xC6)
#define REG_DVI_ATOP2_63_H        (REG_DVI_ATOP2_BASE + 0xC7)

#define REG_DVI_ATOP2_64_L        (REG_DVI_ATOP2_BASE + 0xC8)
#define REG_DVI_ATOP2_64_H        (REG_DVI_ATOP2_BASE + 0xC9)
#define REG_DVI_ATOP2_65_L        (REG_DVI_ATOP2_BASE + 0xCA)
#define REG_DVI_ATOP2_66_L        (REG_DVI_ATOP2_BASE + 0xCC)
#define REG_DVI_ATOP2_66_H        (REG_DVI_ATOP2_BASE + 0xCD)
#define REG_DVI_ATOP2_67_L        (REG_DVI_ATOP2_BASE + 0xCE)
#define REG_DVI_ATOP2_68_L        (REG_DVI_ATOP2_BASE + 0xD0)
#define REG_DVI_ATOP2_68_H        (REG_DVI_ATOP2_BASE + 0xD1)

#define REG_DVI_ATOP2_69_L        (REG_DVI_ATOP2_BASE + 0xD2)
#define REG_DVI_ATOP2_69_H        (REG_DVI_ATOP2_BASE + 0xD3)
#define REG_DVI_ATOP2_6D_L        (REG_DVI_ATOP2_BASE + 0xDA)
#define REG_DVI_ATOP2_6D_H        (REG_DVI_ATOP2_BASE + 0xDB)
#define REG_DVI_ATOP2_70_L        (REG_DVI_ATOP2_BASE + 0xE0)
#define REG_DVI_ATOP2_70_H        (REG_DVI_ATOP2_BASE + 0xE1)
#define REG_DVI_ATOP2_71_L        (REG_DVI_ATOP2_BASE + 0xE2)
#define REG_DVI_ATOP2_71_H        (REG_DVI_ATOP2_BASE + 0xE3)
#define REG_DVI_ATOP2_74_L        (REG_DVI_ATOP2_BASE + 0xE8)

// DVI ATOP3
#define REG_DVI_ATOP3_00_L        (REG_DVI_ATOP3_BASE + 0x00)
#define REG_DVI_ATOP3_00_H        (REG_DVI_ATOP3_BASE + 0x01)
#define REG_DVI_ATOP3_06_L        (REG_DVI_ATOP3_BASE + 0x0C)
#define REG_DVI_ATOP3_06_H        (REG_DVI_ATOP3_BASE + 0x0D)
#define REG_DVI_ATOP3_07_L        (REG_DVI_ATOP3_BASE + 0x0E)
#define REG_DVI_ATOP3_07_H        (REG_DVI_ATOP3_BASE + 0x0F)
#define REG_DVI_ATOP3_0A_L        (REG_DVI_ATOP3_BASE + 0x14)
#define REG_DVI_ATOP3_0A_H        (REG_DVI_ATOP3_BASE + 0x15)
#define REG_DVI_ATOP3_0B_L        (REG_DVI_ATOP3_BASE + 0x16)
#define REG_DVI_ATOP3_0B_H        (REG_DVI_ATOP3_BASE + 0x17)
#define REG_DVI_ATOP3_0C_L        (REG_DVI_ATOP3_BASE + 0x18)
#define REG_DVI_ATOP3_0C_H        (REG_DVI_ATOP3_BASE + 0x19)
#define REG_DVI_ATOP3_5E_L        (REG_DVI_ATOP3_BASE + 0xBC)
#define REG_DVI_ATOP3_5E_H        (REG_DVI_ATOP3_BASE + 0xBD)
#define REG_DVI_ATOP3_60_L        (REG_DVI_ATOP3_BASE + 0xC0)
#define REG_DVI_ATOP3_60_H        (REG_DVI_ATOP3_BASE + 0xC1)
#define REG_DVI_ATOP3_61_L        (REG_DVI_ATOP3_BASE + 0xC2)
#define REG_DVI_ATOP3_61_H        (REG_DVI_ATOP3_BASE + 0xC3)
#define REG_DVI_ATOP3_62_L        (REG_DVI_ATOP3_BASE + 0xC4)
#define REG_DVI_ATOP3_62_H        (REG_DVI_ATOP3_BASE + 0xC5)
#define REG_DVI_ATOP3_63_L        (REG_DVI_ATOP3_BASE + 0xC6)
#define REG_DVI_ATOP3_63_H        (REG_DVI_ATOP3_BASE + 0xC7)
#define REG_DVI_ATOP3_64_L        (REG_DVI_ATOP3_BASE + 0xC8)
#define REG_DVI_ATOP3_64_H        (REG_DVI_ATOP3_BASE + 0xC9)
#define REG_DVI_ATOP3_65_L        (REG_DVI_ATOP3_BASE + 0xCA)
#define REG_DVI_ATOP3_65_H        (REG_DVI_ATOP3_BASE + 0xCB)
#define REG_DVI_ATOP3_67_L        (REG_DVI_ATOP3_BASE + 0xCE)
#define REG_DVI_ATOP3_67_H        (REG_DVI_ATOP3_BASE + 0xCF)
#define REG_DVI_ATOP3_68_L        (REG_DVI_ATOP3_BASE + 0xD0)
#define REG_DVI_ATOP3_68_H        (REG_DVI_ATOP3_BASE + 0xD1)

#define REG_DVI_ATOP3_70_L        (REG_DVI_ATOP3_BASE + 0xE0)
#define REG_DVI_ATOP3_70_H        (REG_DVI_ATOP3_BASE + 0xE1)
#define REG_DVI_ATOP3_71_L        (REG_DVI_ATOP3_BASE + 0xE2)
#define REG_DVI_ATOP3_71_H        (REG_DVI_ATOP3_BASE + 0xE3)
#define REG_DVI_ATOP3_74_L        (REG_DVI_ATOP3_BASE + 0xE8)
#define REG_DVI_ATOP3_74_H        (REG_DVI_ATOP3_BASE + 0xE9)

//=============================================================
// DVI Power Saving
#define REG_DVI_PS_00_L         (REG_DVI_PS_BASE + 0x00)
#define REG_DVI_PS_00_H         (REG_DVI_PS_BASE + 0x01)
#define REG_DVI_PS_01_L         (REG_DVI_PS_BASE + 0x02)
#define REG_DVI_PS_01_H         (REG_DVI_PS_BASE + 0x03)
#define REG_DVI_PS_02_L         (REG_DVI_PS_BASE + 0x04)
#define REG_DVI_PS_02_H         (REG_DVI_PS_BASE + 0x05)
#define REG_DVI_PS_03_L         (REG_DVI_PS_BASE + 0x06)
#define REG_DVI_PS_03_H         (REG_DVI_PS_BASE + 0x07)
#define REG_DVI_PS_04_L         (REG_DVI_PS_BASE + 0x08)	//
#define REG_DVI_PS_04_H         (REG_DVI_PS_BASE + 0x09)	//add DVI VDE period change tolerance
#define REG_DVI_PS_06_L         (REG_DVI_PS_BASE + 0x0C)
#define REG_DVI_PS_06_H         (REG_DVI_PS_BASE + 0x0D)
#define REG_DVI_PS_0A_L         (REG_DVI_PS_BASE + 0x14)
#define REG_DVI_PS_0A_H         (REG_DVI_PS_BASE + 0x15)
#define REG_DVI_PS_0B_L         (REG_DVI_PS_BASE + 0x16)
#define REG_DVI_PS_0B_H         (REG_DVI_PS_BASE + 0x17)
#define REG_DVI_PS_12_L         (REG_DVI_PS_BASE + 0x24)
#define REG_DVI_PS_12_H         (REG_DVI_PS_BASE + 0x25)


// DVI PS1
#define REG_DVI_PS1_00_L         (REG_DVI_PS1_BASE + 0x00)
#define REG_DVI_PS1_00_H         (REG_DVI_PS1_BASE + 0x01)
#define REG_DVI_PS1_01_L         (REG_DVI_PS1_BASE + 0x02)
#define REG_DVI_PS1_01_H         (REG_DVI_PS1_BASE + 0x03)
#define REG_DVI_PS1_0B_L         (REG_DVI_PS1_BASE + 0x16)
#define REG_DVI_PS1_0B_H         (REG_DVI_PS1_BASE + 0x17)
// DVI PS2
#define REG_DVI_PS2_00_L         (REG_DVI_PS2_BASE + 0x00)
#define REG_DVI_PS2_00_H         (REG_DVI_PS2_BASE + 0x01)
#define REG_DVI_PS2_01_L         (REG_DVI_PS2_BASE + 0x02)
#define REG_DVI_PS2_01_H         (REG_DVI_PS2_BASE + 0x03)
#define REG_DVI_PS2_0B_L         (REG_DVI_PS2_BASE + 0x16)
#define REG_DVI_PS2_0B_H         (REG_DVI_PS2_BASE + 0x17)
// DVI PS3
#define REG_DVI_PS3_00_L         (REG_DVI_PS3_BASE + 0x00)
#define REG_DVI_PS3_00_H         (REG_DVI_PS3_BASE + 0x01)
#define REG_DVI_PS3_01_L         (REG_DVI_PS3_BASE + 0x02)
#define REG_DVI_PS3_01_H         (REG_DVI_PS3_BASE + 0x03)
#define REG_DVI_PS3_0B_L         (REG_DVI_PS3_BASE + 0x16)
#define REG_DVI_PS3_0B_H         (REG_DVI_PS3_BASE + 0x17)
//=============================================================
//HDMI
//#define REG_HDMI_BASE       0x2700

#define REG_HDMI_00_L       (REG_HDMI_BASE + 0x00)
#define REG_HDMI_00_H       (REG_HDMI_BASE + 0x01)
#define REG_HDMI_01_L       (REG_HDMI_BASE + 0x02)
#define REG_HDMI_01_H       (REG_HDMI_BASE + 0x03)
#define REG_HDMI_02_L       (REG_HDMI_BASE + 0x04)
#define REG_HDMI_02_H       (REG_HDMI_BASE + 0x05)
#define REG_HDMI_03_L       (REG_HDMI_BASE + 0x06)
#define REG_HDMI_03_H       (REG_HDMI_BASE + 0x07)
#define REG_HDMI_04_L       (REG_HDMI_BASE + 0x08)
#define REG_HDMI_04_H       (REG_HDMI_BASE + 0x09)
#define REG_HDMI_05_L       (REG_HDMI_BASE + 0x0A)
#define REG_HDMI_05_H       (REG_HDMI_BASE + 0x0B)
#define REG_HDMI_06_L       (REG_HDMI_BASE + 0x0C)
#define REG_HDMI_06_H       (REG_HDMI_BASE + 0x0D)
#define REG_HDMI_07_L       (REG_HDMI_BASE + 0x0E)
#define REG_HDMI_07_H       (REG_HDMI_BASE + 0x0F)
#define REG_HDMI_08_L       (REG_HDMI_BASE + 0x10)
#define REG_HDMI_08_H       (REG_HDMI_BASE + 0x11)
#define REG_HDMI_09_L       (REG_HDMI_BASE + 0x12)
#define REG_HDMI_09_H       (REG_HDMI_BASE + 0x13)
#define REG_HDMI_0A_L       (REG_HDMI_BASE + 0x14)
#define REG_HDMI_0A_H       (REG_HDMI_BASE + 0x15)
#define REG_HDMI_0B_L       (REG_HDMI_BASE + 0x16)
#define REG_HDMI_0B_H       (REG_HDMI_BASE + 0x17)
#define REG_HDMI_0C_L       (REG_HDMI_BASE + 0x18)
#define REG_HDMI_0C_H       (REG_HDMI_BASE + 0x19)
#define REG_HDMI_0D_L       (REG_HDMI_BASE + 0x1A)
#define REG_HDMI_0D_H       (REG_HDMI_BASE + 0x1B)
#define REG_HDMI_0E_L       (REG_HDMI_BASE + 0x1C)
#define REG_HDMI_0E_H       (REG_HDMI_BASE + 0x1D)
#define REG_HDMI_0F_L       (REG_HDMI_BASE + 0x1E)
#define REG_HDMI_0F_H       (REG_HDMI_BASE + 0x1F)
#define REG_HDMI_10_L       (REG_HDMI_BASE + 0x20)
#define REG_HDMI_10_H       (REG_HDMI_BASE + 0x21)
#define REG_HDMI_11_L       (REG_HDMI_BASE + 0x22)
#define REG_HDMI_11_H       (REG_HDMI_BASE + 0x23)
#define REG_HDMI_12_L       (REG_HDMI_BASE + 0x24)
#define REG_HDMI_12_H       (REG_HDMI_BASE + 0x25)
#define REG_HDMI_13_L       (REG_HDMI_BASE + 0x26)
#define REG_HDMI_13_H       (REG_HDMI_BASE + 0x27)
#define REG_HDMI_14_L       (REG_HDMI_BASE + 0x28)
#define REG_HDMI_14_H       (REG_HDMI_BASE + 0x29)
#define REG_HDMI_15_L       (REG_HDMI_BASE + 0x2A)
#define REG_HDMI_15_H       (REG_HDMI_BASE + 0x2B)
#define REG_HDMI_16_L       (REG_HDMI_BASE + 0x2C)
#define REG_HDMI_16_H       (REG_HDMI_BASE + 0x2D)
#define REG_HDMI_17_L       (REG_HDMI_BASE + 0x2E)
#define REG_HDMI_17_H       (REG_HDMI_BASE + 0x2F)
#define REG_HDMI_18_L       (REG_HDMI_BASE + 0x30)
#define REG_HDMI_18_H       (REG_HDMI_BASE + 0x31)
#define REG_HDMI_19_L       (REG_HDMI_BASE + 0x32)
#define REG_HDMI_19_H       (REG_HDMI_BASE + 0x33)
#define REG_HDMI_1A_L       (REG_HDMI_BASE + 0x34)
#define REG_HDMI_1A_H       (REG_HDMI_BASE + 0x35)
#define REG_HDMI_1B_L       (REG_HDMI_BASE + 0x36)
#define REG_HDMI_1B_H       (REG_HDMI_BASE + 0x37)
#define REG_HDMI_1C_L       (REG_HDMI_BASE + 0x38)
#define REG_HDMI_1C_H       (REG_HDMI_BASE + 0x39)
#define REG_HDMI_1D_L       (REG_HDMI_BASE + 0x3A)
#define REG_HDMI_1D_H       (REG_HDMI_BASE + 0x3B)
#define REG_HDMI_1E_L       (REG_HDMI_BASE + 0x3C)
#define REG_HDMI_1E_H       (REG_HDMI_BASE + 0x3D)
#define REG_HDMI_1F_L       (REG_HDMI_BASE + 0x3E)
#define REG_HDMI_1F_H       (REG_HDMI_BASE + 0x3F)
#define REG_HDMI_20_L       (REG_HDMI_BASE + 0x40)
#define REG_HDMI_20_H       (REG_HDMI_BASE + 0x41)
#define REG_HDMI_21_L       (REG_HDMI_BASE + 0x42)
#define REG_HDMI_21_H       (REG_HDMI_BASE + 0x43)
#define REG_HDMI_22_L       (REG_HDMI_BASE + 0x44)
#define REG_HDMI_22_H       (REG_HDMI_BASE + 0x45)
#define REG_HDMI_23_L       (REG_HDMI_BASE + 0x46)
#define REG_HDMI_23_H       (REG_HDMI_BASE + 0x47)
#define REG_HDMI_24_L       (REG_HDMI_BASE + 0x48)
#define REG_HDMI_24_H       (REG_HDMI_BASE + 0x49)
#define REG_HDMI_25_L       (REG_HDMI_BASE + 0x4A)
#define REG_HDMI_25_H       (REG_HDMI_BASE + 0x4B)
#define REG_HDMI_26_L       (REG_HDMI_BASE + 0x4C)
#define REG_HDMI_26_H       (REG_HDMI_BASE + 0x4D)
#define REG_HDMI_27_L       (REG_HDMI_BASE + 0x4E)
#define REG_HDMI_27_H       (REG_HDMI_BASE + 0x4F)
#define REG_HDMI_28_L       (REG_HDMI_BASE + 0x50)
#define REG_HDMI_28_H       (REG_HDMI_BASE + 0x51)
#define REG_HDMI_29_L       (REG_HDMI_BASE + 0x52)
#define REG_HDMI_29_H       (REG_HDMI_BASE + 0x53)
#define REG_HDMI_2A_L       (REG_HDMI_BASE + 0x54)
#define REG_HDMI_2A_H       (REG_HDMI_BASE + 0x55)
#define REG_HDMI_2B_L       (REG_HDMI_BASE + 0x56)
#define REG_HDMI_2B_H       (REG_HDMI_BASE + 0x57)
#define REG_HDMI_2C_L       (REG_HDMI_BASE + 0x58)
#define REG_HDMI_2C_H       (REG_HDMI_BASE + 0x59)
#define REG_HDMI_2D_L       (REG_HDMI_BASE + 0x5A)
#define REG_HDMI_2D_H       (REG_HDMI_BASE + 0x5B)
#define REG_HDMI_2E_L       (REG_HDMI_BASE + 0x5C)
#define REG_HDMI_2E_H       (REG_HDMI_BASE + 0x5D)
#define REG_HDMI_2F_L       (REG_HDMI_BASE + 0x5E)
#define REG_HDMI_2F_H       (REG_HDMI_BASE + 0x5F)
#define REG_HDMI_30_L       (REG_HDMI_BASE + 0x60)
#define REG_HDMI_30_H       (REG_HDMI_BASE + 0x61)
#define REG_HDMI_31_L       (REG_HDMI_BASE + 0x62)
#define REG_HDMI_31_H       (REG_HDMI_BASE + 0x63)
#define REG_HDMI_32_L       (REG_HDMI_BASE + 0x64)
#define REG_HDMI_32_H       (REG_HDMI_BASE + 0x65)
#define REG_HDMI_33_L       (REG_HDMI_BASE + 0x66)
#define REG_HDMI_33_H       (REG_HDMI_BASE + 0x67)
#define REG_HDMI_34_L       (REG_HDMI_BASE + 0x68)
#define REG_HDMI_34_H       (REG_HDMI_BASE + 0x69)
#define REG_HDMI_35_L       (REG_HDMI_BASE + 0x6A)
#define REG_HDMI_35_H       (REG_HDMI_BASE + 0x6B)
#define REG_HDMI_36_L       (REG_HDMI_BASE + 0x6C)
#define REG_HDMI_36_H       (REG_HDMI_BASE + 0x6D)
#define REG_HDMI_37_L       (REG_HDMI_BASE + 0x6E)
#define REG_HDMI_37_H       (REG_HDMI_BASE + 0x6F)
#define REG_HDMI_38_L       (REG_HDMI_BASE + 0x70)
#define REG_HDMI_38_H       (REG_HDMI_BASE + 0x71)
#define REG_HDMI_39_L       (REG_HDMI_BASE + 0x72)
#define REG_HDMI_39_H       (REG_HDMI_BASE + 0x73)
#define REG_HDMI_3A_L       (REG_HDMI_BASE + 0x74)
#define REG_HDMI_3A_H       (REG_HDMI_BASE + 0x75)
#define REG_HDMI_3B_L       (REG_HDMI_BASE + 0x76)
#define REG_HDMI_3B_H       (REG_HDMI_BASE + 0x77)
#define REG_HDMI_3C_L       (REG_HDMI_BASE + 0x78)
#define REG_HDMI_3C_H       (REG_HDMI_BASE + 0x79)
#define REG_HDMI_3D_L       (REG_HDMI_BASE + 0x7A)
#define REG_HDMI_3D_H       (REG_HDMI_BASE + 0x7B)
#define REG_HDMI_3E_L       (REG_HDMI_BASE + 0x7C)
#define REG_HDMI_3E_H       (REG_HDMI_BASE + 0x7D)
#define REG_HDMI_3F_L       (REG_HDMI_BASE + 0x7E)
#define REG_HDMI_3F_H       (REG_HDMI_BASE + 0x7F)
#define REG_HDMI_40_L       (REG_HDMI_BASE + 0x80)
#define REG_HDMI_40_H       (REG_HDMI_BASE + 0x81)
#define REG_HDMI_41_L       (REG_HDMI_BASE + 0x82)
#define REG_HDMI_41_H       (REG_HDMI_BASE + 0x83)
#define REG_HDMI_42_L       (REG_HDMI_BASE + 0x84)
#define REG_HDMI_42_H       (REG_HDMI_BASE + 0x85)
#define REG_HDMI_43_L       (REG_HDMI_BASE + 0x86)
#define REG_HDMI_43_H       (REG_HDMI_BASE + 0x87)
#define REG_HDMI_44_L       (REG_HDMI_BASE + 0x88)
#define REG_HDMI_44_H       (REG_HDMI_BASE + 0x89)
#define REG_HDMI_45_L       (REG_HDMI_BASE + 0x8A)
#define REG_HDMI_45_H       (REG_HDMI_BASE + 0x8B)
#define REG_HDMI_46_L       (REG_HDMI_BASE + 0x8C)
#define REG_HDMI_46_H       (REG_HDMI_BASE + 0x8D)
#define REG_HDMI_47_L       (REG_HDMI_BASE + 0x8E)
#define REG_HDMI_47_H       (REG_HDMI_BASE + 0x8F)
#define REG_HDMI_48_L       (REG_HDMI_BASE + 0x90)
#define REG_HDMI_48_H       (REG_HDMI_BASE + 0x91)
#define REG_HDMI_49_L       (REG_HDMI_BASE + 0x92)
#define REG_HDMI_49_H       (REG_HDMI_BASE + 0x93)
#define REG_HDMI_4A_L       (REG_HDMI_BASE + 0x94)
#define REG_HDMI_4A_H       (REG_HDMI_BASE + 0x95)
#define REG_HDMI_4B_L       (REG_HDMI_BASE + 0x96)
#define REG_HDMI_4B_H       (REG_HDMI_BASE + 0x97)
#define REG_HDMI_4C_L       (REG_HDMI_BASE + 0x98)
#define REG_HDMI_4C_H       (REG_HDMI_BASE + 0x99)
#define REG_HDMI_4D_L       (REG_HDMI_BASE + 0x9A)
#define REG_HDMI_4D_H       (REG_HDMI_BASE + 0x9B)
#define REG_HDMI_4E_L       (REG_HDMI_BASE + 0x9C)
#define REG_HDMI_4E_H       (REG_HDMI_BASE + 0x9D)
#define REG_HDMI_4F_L       (REG_HDMI_BASE + 0x9E)
#define REG_HDMI_4F_H       (REG_HDMI_BASE + 0x9F)
#define REG_HDMI_50_L       (REG_HDMI_BASE + 0xA0)
#define REG_HDMI_50_H       (REG_HDMI_BASE + 0xA1)
#define REG_HDMI_51_L       (REG_HDMI_BASE + 0xA2)
#define REG_HDMI_51_H       (REG_HDMI_BASE + 0xA3)
#define REG_HDMI_52_L       (REG_HDMI_BASE + 0xA4)
#define REG_HDMI_52_H       (REG_HDMI_BASE + 0xA5)
#define REG_HDMI_53_L       (REG_HDMI_BASE + 0xA6)
#define REG_HDMI_53_H       (REG_HDMI_BASE + 0xA7)
#define REG_HDMI_54_L       (REG_HDMI_BASE + 0xA8)
#define REG_HDMI_54_H       (REG_HDMI_BASE + 0xA9)
#define REG_HDMI_55_L       (REG_HDMI_BASE + 0xAA)
#define REG_HDMI_55_H       (REG_HDMI_BASE + 0xAB)
#define REG_HDMI_56_L       (REG_HDMI_BASE + 0xAC)
#define REG_HDMI_56_H       (REG_HDMI_BASE + 0xAD)
#define REG_HDMI_57_L       (REG_HDMI_BASE + 0xAE)
#define REG_HDMI_57_H       (REG_HDMI_BASE + 0xAF)
#define REG_HDMI_58_L       (REG_HDMI_BASE + 0xB0)
#define REG_HDMI_58_H       (REG_HDMI_BASE + 0xB1)
#define REG_HDMI_59_L       (REG_HDMI_BASE + 0xB2)
#define REG_HDMI_59_H       (REG_HDMI_BASE + 0xB3)
#define REG_HDMI_5A_L       (REG_HDMI_BASE + 0xB4)
#define REG_HDMI_5A_H       (REG_HDMI_BASE + 0xB5)
#define REG_HDMI_5B_L       (REG_HDMI_BASE + 0xB6)
#define REG_HDMI_5B_H       (REG_HDMI_BASE + 0xB7)
#define REG_HDMI_5C_L       (REG_HDMI_BASE + 0xB8)
#define REG_HDMI_5C_H       (REG_HDMI_BASE + 0xB9)
#define REG_HDMI_5D_L       (REG_HDMI_BASE + 0xBA)
#define REG_HDMI_5D_H       (REG_HDMI_BASE + 0xBB)
#define REG_HDMI_5E_L       (REG_HDMI_BASE + 0xBC)
#define REG_HDMI_5E_H       (REG_HDMI_BASE + 0xBD)
#define REG_HDMI_5F_L       (REG_HDMI_BASE + 0xBE)
#define REG_HDMI_5F_H       (REG_HDMI_BASE + 0xBF)
#define REG_HDMI_60_L       (REG_HDMI_BASE + 0xC0)
#define REG_HDMI_60_H       (REG_HDMI_BASE + 0xC1)
#define REG_HDMI_61_L       (REG_HDMI_BASE + 0xC2)
#define REG_HDMI_61_H       (REG_HDMI_BASE + 0xC3)
#define REG_HDMI_62_L       (REG_HDMI_BASE + 0xC4)
#define REG_HDMI_62_H       (REG_HDMI_BASE + 0xC5)
#define REG_HDMI_63_L       (REG_HDMI_BASE + 0xC6)
#define REG_HDMI_63_H       (REG_HDMI_BASE + 0xC7)
#define REG_HDMI_64_L       (REG_HDMI_BASE + 0xC8)
#define REG_HDMI_64_H       (REG_HDMI_BASE + 0xC9)
#define REG_HDMI_65_L       (REG_HDMI_BASE + 0xCA)
#define REG_HDMI_65_H       (REG_HDMI_BASE + 0xCB)
#define REG_HDMI_66_L       (REG_HDMI_BASE + 0xCC)
#define REG_HDMI_66_H       (REG_HDMI_BASE + 0xCD)
#define REG_HDMI_67_L       (REG_HDMI_BASE + 0xCE)
#define REG_HDMI_67_H       (REG_HDMI_BASE + 0xCF)
#define REG_HDMI_68_L       (REG_HDMI_BASE + 0xD0)
#define REG_HDMI_68_H       (REG_HDMI_BASE + 0xD1)
#define REG_HDMI_69_L       (REG_HDMI_BASE + 0xD2)
#define REG_HDMI_69_H       (REG_HDMI_BASE + 0xD3)
#define REG_HDMI_6A_L       (REG_HDMI_BASE + 0xD4)
#define REG_HDMI_6A_H       (REG_HDMI_BASE + 0xD5)
#define REG_HDMI_6B_L       (REG_HDMI_BASE + 0xD6)
#define REG_HDMI_6B_H       (REG_HDMI_BASE + 0xD7)
#define REG_HDMI_6C_L       (REG_HDMI_BASE + 0xD8)
#define REG_HDMI_6C_H       (REG_HDMI_BASE + 0xD9)
#define REG_HDMI_6D_L       (REG_HDMI_BASE + 0xDA)
#define REG_HDMI_6D_H       (REG_HDMI_BASE + 0xDB)
#define REG_HDMI_6E_L       (REG_HDMI_BASE + 0xDC)
#define REG_HDMI_6E_H       (REG_HDMI_BASE + 0xDD)
#define REG_HDMI_6F_L       (REG_HDMI_BASE + 0xDE)
#define REG_HDMI_6F_H       (REG_HDMI_BASE + 0xDF)
#define REG_HDMI_70_L       (REG_HDMI_BASE + 0xE0)
#define REG_HDMI_70_H       (REG_HDMI_BASE + 0xE1)
#define REG_HDMI_71_L       (REG_HDMI_BASE + 0xE2)
#define REG_HDMI_71_H       (REG_HDMI_BASE + 0xE3)
#define REG_HDMI_72_L       (REG_HDMI_BASE + 0xE4)
#define REG_HDMI_72_H       (REG_HDMI_BASE + 0xE5)
#define REG_HDMI_73_L       (REG_HDMI_BASE + 0xE6)
#define REG_HDMI_73_H       (REG_HDMI_BASE + 0xE7)
#define REG_HDMI_74_L       (REG_HDMI_BASE + 0xE8)
#define REG_HDMI_74_H       (REG_HDMI_BASE + 0xE9)
#define REG_HDMI_75_L       (REG_HDMI_BASE + 0xEA)
#define REG_HDMI_75_H       (REG_HDMI_BASE + 0xEB)
#define REG_HDMI_76_L       (REG_HDMI_BASE + 0xEC)
#define REG_HDMI_76_H       (REG_HDMI_BASE + 0xED)
#define REG_HDMI_77_L       (REG_HDMI_BASE + 0xEE)
#define REG_HDMI_77_H       (REG_HDMI_BASE + 0xEF)
#define REG_HDMI_78_L       (REG_HDMI_BASE + 0xF0)
#define REG_HDMI_78_H       (REG_HDMI_BASE + 0xF1)
#define REG_HDMI_79_L       (REG_HDMI_BASE + 0xF2)
#define REG_HDMI_79_H       (REG_HDMI_BASE + 0xF3)
#define REG_HDMI_7A_L       (REG_HDMI_BASE + 0xF4)
#define REG_HDMI_7A_H       (REG_HDMI_BASE + 0xF5)
#define REG_HDMI_7B_L       (REG_HDMI_BASE + 0xF6)
#define REG_HDMI_7B_H       (REG_HDMI_BASE + 0xF7)
#define REG_HDMI_7C_L       (REG_HDMI_BASE + 0xF8)
#define REG_HDMI_7C_H       (REG_HDMI_BASE + 0xF9)
#define REG_HDMI_7D_L       (REG_HDMI_BASE + 0xFA)
#define REG_HDMI_7D_H       (REG_HDMI_BASE + 0xFB)
#define REG_HDMI_7E_L       (REG_HDMI_BASE + 0xFC)
#define REG_HDMI_7E_H       (REG_HDMI_BASE + 0xFD)
#define REG_HDMI_7F_L       (REG_HDMI_BASE + 0xFE)
#define REG_HDMI_7F_H       (REG_HDMI_BASE + 0xFF)

// HDMI2
#define REG_HDMI2_01_L       (REG_HDMI2_BASE + 0x02)
#define REG_HDMI2_01_H       (REG_HDMI2_BASE + 0x03)
#define REG_HDMI2_02_L       (REG_HDMI2_BASE + 0x04)
#define REG_HDMI2_02_H       (REG_HDMI2_BASE + 0x05)
#define REG_HDMI2_03_L       (REG_HDMI2_BASE + 0x06)
#define REG_HDMI2_03_H       (REG_HDMI2_BASE + 0x07)
#define REG_HDMI2_06_L       (REG_HDMI2_BASE + 0x0C)
#define REG_HDMI2_06_H       (REG_HDMI2_BASE + 0x0D)
#define REG_HDMI2_08_L       (REG_HDMI2_BASE + 0x10)
#define REG_HDMI2_08_H       (REG_HDMI2_BASE + 0x11)
#define REG_HDMI2_10_L       (REG_HDMI2_BASE + 0x20)
#define REG_HDMI2_10_H       (REG_HDMI2_BASE + 0x21)
#define REG_HDMI2_11_L       (REG_HDMI2_BASE + 0x22)
#define REG_HDMI2_11_H       (REG_HDMI2_BASE + 0x23)
#define REG_HDMI2_12_L       (REG_HDMI2_BASE + 0x24)
#define REG_HDMI2_12_H       (REG_HDMI2_BASE + 0x25)
#define REG_HDMI2_13_L       (REG_HDMI2_BASE + 0x26)
#define REG_HDMI2_13_H       (REG_HDMI2_BASE + 0x27)
#define REG_HDMI2_15_L       (REG_HDMI2_BASE + 0x2A)
#define REG_HDMI2_15_H       (REG_HDMI2_BASE + 0x2B)
#define REG_HDMI2_20_L       (REG_HDMI2_BASE + 0x40)
#define REG_HDMI2_20_H       (REG_HDMI2_BASE + 0x41)
#define REG_HDMI2_25_L       (REG_HDMI2_BASE + 0x4A)
#define REG_HDMI2_25_H       (REG_HDMI2_BASE + 0x4B)
#define REG_HDMI2_26_L       (REG_HDMI2_BASE + 0x4C)
#define REG_HDMI2_26_H       (REG_HDMI2_BASE + 0x4D)
#define REG_HDMI2_27_L       (REG_HDMI2_BASE + 0x4E)
#define REG_HDMI2_27_H       (REG_HDMI2_BASE + 0x4F)
#define REG_HDMI2_33_L       (REG_HDMI2_BASE + 0x66)
#define REG_HDMI2_34_L       (REG_HDMI2_BASE + 0x68)
#define REG_HDMI2_35_L       (REG_HDMI2_BASE + 0x6A)
#define REG_HDMI2_36_L       (REG_HDMI2_BASE + 0x6C)
#define REG_HDMI2_36_H       (REG_HDMI2_BASE + 0x6D)

//#define REG_MHL_TMDS_BASE       0x2700
#define REG_MHL_TMDS_00_L       (REG_MHL_TMDS_BASE + 0x00)
#define REG_MHL_TMDS_00_H       (REG_MHL_TMDS_BASE + 0x01)
#define REG_MHL_TMDS_01_L       (REG_MHL_TMDS_BASE + 0x02)
#define REG_MHL_TMDS_01_H       (REG_MHL_TMDS_BASE + 0x03)
#define REG_MHL_TMDS_02_L       (REG_MHL_TMDS_BASE + 0x04)
#define REG_MHL_TMDS_02_H       (REG_MHL_TMDS_BASE + 0x05)
#define REG_MHL_TMDS_03_L       (REG_MHL_TMDS_BASE + 0x06)
#define REG_MHL_TMDS_03_H       (REG_MHL_TMDS_BASE + 0x07)
#define REG_MHL_TMDS_04_L       (REG_MHL_TMDS_BASE + 0x08)
#define REG_MHL_TMDS_04_H       (REG_MHL_TMDS_BASE + 0x09)
#define REG_MHL_TMDS_05_L       (REG_MHL_TMDS_BASE + 0x0A)
#define REG_MHL_TMDS_05_H       (REG_MHL_TMDS_BASE + 0x0B)
#define REG_MHL_TMDS_06_L       (REG_MHL_TMDS_BASE + 0x0C)
#define REG_MHL_TMDS_06_H       (REG_MHL_TMDS_BASE + 0x0D)
#define REG_MHL_TMDS_07_L       (REG_MHL_TMDS_BASE + 0x0E)
#define REG_MHL_TMDS_07_H       (REG_MHL_TMDS_BASE + 0x0F)
#define REG_MHL_TMDS_08_L       (REG_MHL_TMDS_BASE + 0x10)
#define REG_MHL_TMDS_08_H       (REG_MHL_TMDS_BASE + 0x11)
#define REG_MHL_TMDS_09_L       (REG_MHL_TMDS_BASE + 0x12)
#define REG_MHL_TMDS_09_H       (REG_MHL_TMDS_BASE + 0x13)
#define REG_MHL_TMDS_0A_L       (REG_MHL_TMDS_BASE + 0x14)
#define REG_MHL_TMDS_0A_H       (REG_MHL_TMDS_BASE + 0x15)
#define REG_MHL_TMDS_0B_L       (REG_MHL_TMDS_BASE + 0x16)
#define REG_MHL_TMDS_0B_H       (REG_MHL_TMDS_BASE + 0x17)
#define REG_MHL_TMDS_0C_L       (REG_MHL_TMDS_BASE + 0x18)
#define REG_MHL_TMDS_0C_H       (REG_MHL_TMDS_BASE + 0x19)
#define REG_MHL_TMDS_0D_L       (REG_MHL_TMDS_BASE + 0x1A)
#define REG_MHL_TMDS_0D_H       (REG_MHL_TMDS_BASE + 0x1B)
#define REG_MHL_TMDS_0E_L       (REG_MHL_TMDS_BASE + 0x1C)
#define REG_MHL_TMDS_0E_H       (REG_MHL_TMDS_BASE + 0x1D)
#define REG_MHL_TMDS_0F_L       (REG_MHL_TMDS_BASE + 0x1E)
#define REG_MHL_TMDS_0F_H       (REG_MHL_TMDS_BASE + 0x1F)
#define REG_MHL_TMDS_10_L       (REG_MHL_TMDS_BASE + 0x20)
#define REG_MHL_TMDS_10_H       (REG_MHL_TMDS_BASE + 0x21)
#define REG_MHL_TMDS_11_L       (REG_MHL_TMDS_BASE + 0x22)
#define REG_MHL_TMDS_11_H       (REG_MHL_TMDS_BASE + 0x23)
#define REG_MHL_TMDS_12_L       (REG_MHL_TMDS_BASE + 0x24)
#define REG_MHL_TMDS_12_H       (REG_MHL_TMDS_BASE + 0x25)
#define REG_MHL_TMDS_13_L       (REG_MHL_TMDS_BASE + 0x26)
#define REG_MHL_TMDS_13_H       (REG_MHL_TMDS_BASE + 0x27)
#define REG_MHL_TMDS_14_L       (REG_MHL_TMDS_BASE + 0x28)
#define REG_MHL_TMDS_14_H       (REG_MHL_TMDS_BASE + 0x29)
#define REG_MHL_TMDS_15_L       (REG_MHL_TMDS_BASE + 0x2A)
#define REG_MHL_TMDS_15_H       (REG_MHL_TMDS_BASE + 0x2B)
#define REG_MHL_TMDS_16_L       (REG_MHL_TMDS_BASE + 0x2C)
#define REG_MHL_TMDS_16_H       (REG_MHL_TMDS_BASE + 0x2D)
#define REG_MHL_TMDS_17_L       (REG_MHL_TMDS_BASE + 0x2E)
#define REG_MHL_TMDS_17_H       (REG_MHL_TMDS_BASE + 0x2F)
#define REG_MHL_TMDS_18_L       (REG_MHL_TMDS_BASE + 0x30)
#define REG_MHL_TMDS_18_H       (REG_MHL_TMDS_BASE + 0x31)
#define REG_MHL_TMDS_19_L       (REG_MHL_TMDS_BASE + 0x32)
#define REG_MHL_TMDS_19_H       (REG_MHL_TMDS_BASE + 0x33)
#define REG_MHL_TMDS_1A_L       (REG_MHL_TMDS_BASE + 0x34)
#define REG_MHL_TMDS_1A_H       (REG_MHL_TMDS_BASE + 0x35)
#define REG_MHL_TMDS_1B_L       (REG_MHL_TMDS_BASE + 0x36)
#define REG_MHL_TMDS_1B_H       (REG_MHL_TMDS_BASE + 0x37)
#define REG_MHL_TMDS_1C_L       (REG_MHL_TMDS_BASE + 0x38)
#define REG_MHL_TMDS_1C_H       (REG_MHL_TMDS_BASE + 0x39)
#define REG_MHL_TMDS_1D_L       (REG_MHL_TMDS_BASE + 0x3A)
#define REG_MHL_TMDS_1D_H       (REG_MHL_TMDS_BASE + 0x3B)
#define REG_MHL_TMDS_1E_L       (REG_MHL_TMDS_BASE + 0x3C)
#define REG_MHL_TMDS_1E_H       (REG_MHL_TMDS_BASE + 0x3D)
#define REG_MHL_TMDS_1F_L       (REG_MHL_TMDS_BASE + 0x3E)
#define REG_MHL_TMDS_1F_H       (REG_MHL_TMDS_BASE + 0x3F)
#define REG_MHL_TMDS_20_L       (REG_MHL_TMDS_BASE + 0x40)
#define REG_MHL_TMDS_20_H       (REG_MHL_TMDS_BASE + 0x41)
#define REG_MHL_TMDS_21_L       (REG_MHL_TMDS_BASE + 0x42)
#define REG_MHL_TMDS_21_H       (REG_MHL_TMDS_BASE + 0x43)
#define REG_MHL_TMDS_22_L       (REG_MHL_TMDS_BASE + 0x44)
#define REG_MHL_TMDS_22_H       (REG_MHL_TMDS_BASE + 0x45)
#define REG_MHL_TMDS_23_L       (REG_MHL_TMDS_BASE + 0x46)
#define REG_MHL_TMDS_23_H       (REG_MHL_TMDS_BASE + 0x47)
#define REG_MHL_TMDS_24_L       (REG_MHL_TMDS_BASE + 0x48)
#define REG_MHL_TMDS_24_H       (REG_MHL_TMDS_BASE + 0x49)
#define REG_MHL_TMDS_25_L       (REG_MHL_TMDS_BASE + 0x4A)
#define REG_MHL_TMDS_25_H       (REG_MHL_TMDS_BASE + 0x4B)
#define REG_MHL_TMDS_26_L       (REG_MHL_TMDS_BASE + 0x4C)
#define REG_MHL_TMDS_26_H       (REG_MHL_TMDS_BASE + 0x4D)
#define REG_MHL_TMDS_27_L       (REG_MHL_TMDS_BASE + 0x4E)
#define REG_MHL_TMDS_27_H       (REG_MHL_TMDS_BASE + 0x4F)
#define REG_MHL_TMDS_28_L       (REG_MHL_TMDS_BASE + 0x50)
#define REG_MHL_TMDS_28_H       (REG_MHL_TMDS_BASE + 0x51)
#define REG_MHL_TMDS_29_L       (REG_MHL_TMDS_BASE + 0x52)
#define REG_MHL_TMDS_29_H       (REG_MHL_TMDS_BASE + 0x53)
#define REG_MHL_TMDS_2A_L       (REG_MHL_TMDS_BASE + 0x54)
#define REG_MHL_TMDS_2A_H       (REG_MHL_TMDS_BASE + 0x55)
#define REG_MHL_TMDS_2B_L       (REG_MHL_TMDS_BASE + 0x56)
#define REG_MHL_TMDS_2B_H       (REG_MHL_TMDS_BASE + 0x57)
#define REG_MHL_TMDS_2C_L       (REG_MHL_TMDS_BASE + 0x58)
#define REG_MHL_TMDS_2C_H       (REG_MHL_TMDS_BASE + 0x59)
#define REG_MHL_TMDS_2D_L       (REG_MHL_TMDS_BASE + 0x5A)
#define REG_MHL_TMDS_2D_H       (REG_MHL_TMDS_BASE + 0x5B)
#define REG_MHL_TMDS_2E_L       (REG_MHL_TMDS_BASE + 0x5C)
#define REG_MHL_TMDS_2E_H       (REG_MHL_TMDS_BASE + 0x5D)
#define REG_MHL_TMDS_2F_L       (REG_MHL_TMDS_BASE + 0x5E)
#define REG_MHL_TMDS_2F_H       (REG_MHL_TMDS_BASE + 0x5F)
#define REG_MHL_TMDS_30_L       (REG_MHL_TMDS_BASE + 0x60)
#define REG_MHL_TMDS_30_H       (REG_MHL_TMDS_BASE + 0x61)
#define REG_MHL_TMDS_31_L       (REG_MHL_TMDS_BASE + 0x62)
#define REG_MHL_TMDS_31_H       (REG_MHL_TMDS_BASE + 0x63)
#define REG_MHL_TMDS_32_L       (REG_MHL_TMDS_BASE + 0x64)
#define REG_MHL_TMDS_32_H       (REG_MHL_TMDS_BASE + 0x65)
#define REG_MHL_TMDS_33_L       (REG_MHL_TMDS_BASE + 0x66)
#define REG_MHL_TMDS_33_H       (REG_MHL_TMDS_BASE + 0x67)
#define REG_MHL_TMDS_34_L       (REG_MHL_TMDS_BASE + 0x68)
#define REG_MHL_TMDS_34_H       (REG_MHL_TMDS_BASE + 0x69)
#define REG_MHL_TMDS_35_L       (REG_MHL_TMDS_BASE + 0x6A)
#define REG_MHL_TMDS_35_H       (REG_MHL_TMDS_BASE + 0x6B)
#define REG_MHL_TMDS_36_L       (REG_MHL_TMDS_BASE + 0x6C)
#define REG_MHL_TMDS_36_H       (REG_MHL_TMDS_BASE + 0x6D)
#define REG_MHL_TMDS_37_L       (REG_MHL_TMDS_BASE + 0x6E)
#define REG_MHL_TMDS_37_H       (REG_MHL_TMDS_BASE + 0x6F)
#define REG_MHL_TMDS_38_L       (REG_MHL_TMDS_BASE + 0x70)
#define REG_MHL_TMDS_38_H       (REG_MHL_TMDS_BASE + 0x71)
#define REG_MHL_TMDS_39_L       (REG_MHL_TMDS_BASE + 0x72)
#define REG_MHL_TMDS_39_H       (REG_MHL_TMDS_BASE + 0x73)
#define REG_MHL_TMDS_3A_L       (REG_MHL_TMDS_BASE + 0x74)
#define REG_MHL_TMDS_3A_H       (REG_MHL_TMDS_BASE + 0x75)
#define REG_MHL_TMDS_3B_L       (REG_MHL_TMDS_BASE + 0x76)
#define REG_MHL_TMDS_3B_H       (REG_MHL_TMDS_BASE + 0x77)
#define REG_MHL_TMDS_3C_L       (REG_MHL_TMDS_BASE + 0x78)
#define REG_MHL_TMDS_3C_H       (REG_MHL_TMDS_BASE + 0x79)
#define REG_MHL_TMDS_3D_L       (REG_MHL_TMDS_BASE + 0x7A)
#define REG_MHL_TMDS_3D_H       (REG_MHL_TMDS_BASE + 0x7B)
#define REG_MHL_TMDS_3E_L       (REG_MHL_TMDS_BASE + 0x7C)
#define REG_MHL_TMDS_3E_H       (REG_MHL_TMDS_BASE + 0x7D)
#define REG_MHL_TMDS_3F_L       (REG_MHL_TMDS_BASE + 0x7E)
#define REG_MHL_TMDS_3F_H       (REG_MHL_TMDS_BASE + 0x7F)
#define REG_MHL_TMDS_40_L       (REG_MHL_TMDS_BASE + 0x80)
#define REG_MHL_TMDS_40_H       (REG_MHL_TMDS_BASE + 0x81)
#define REG_MHL_TMDS_41_L       (REG_MHL_TMDS_BASE + 0x82)
#define REG_MHL_TMDS_41_H       (REG_MHL_TMDS_BASE + 0x83)
#define REG_MHL_TMDS_42_L       (REG_MHL_TMDS_BASE + 0x84)
#define REG_MHL_TMDS_42_H       (REG_MHL_TMDS_BASE + 0x85)
#define REG_MHL_TMDS_43_L       (REG_MHL_TMDS_BASE + 0x86)
#define REG_MHL_TMDS_43_H       (REG_MHL_TMDS_BASE + 0x87)
#define REG_MHL_TMDS_44_L       (REG_MHL_TMDS_BASE + 0x88)
#define REG_MHL_TMDS_44_H       (REG_MHL_TMDS_BASE + 0x89)
#define REG_MHL_TMDS_45_L       (REG_MHL_TMDS_BASE + 0x8A)
#define REG_MHL_TMDS_45_H       (REG_MHL_TMDS_BASE + 0x8B)
#define REG_MHL_TMDS_46_L       (REG_MHL_TMDS_BASE + 0x8C)
#define REG_MHL_TMDS_46_H       (REG_MHL_TMDS_BASE + 0x8D)
#define REG_MHL_TMDS_47_L       (REG_MHL_TMDS_BASE + 0x8E)
#define REG_MHL_TMDS_47_H       (REG_MHL_TMDS_BASE + 0x8F)
#define REG_MHL_TMDS_48_L       (REG_MHL_TMDS_BASE + 0x90)
#define REG_MHL_TMDS_48_H       (REG_MHL_TMDS_BASE + 0x91)
#define REG_MHL_TMDS_49_L       (REG_MHL_TMDS_BASE + 0x92)
#define REG_MHL_TMDS_49_H       (REG_MHL_TMDS_BASE + 0x93)
#define REG_MHL_TMDS_4A_L       (REG_MHL_TMDS_BASE + 0x94)
#define REG_MHL_TMDS_4A_H       (REG_MHL_TMDS_BASE + 0x95)
#define REG_MHL_TMDS_4B_L       (REG_MHL_TMDS_BASE + 0x96)
#define REG_MHL_TMDS_4B_H       (REG_MHL_TMDS_BASE + 0x97)
#define REG_MHL_TMDS_4C_L       (REG_MHL_TMDS_BASE + 0x98)
#define REG_MHL_TMDS_4C_H       (REG_MHL_TMDS_BASE + 0x99)
#define REG_MHL_TMDS_4D_L       (REG_MHL_TMDS_BASE + 0x9A)
#define REG_MHL_TMDS_4D_H       (REG_MHL_TMDS_BASE + 0x9B)
#define REG_MHL_TMDS_4E_L       (REG_MHL_TMDS_BASE + 0x9C)
#define REG_MHL_TMDS_4E_H       (REG_MHL_TMDS_BASE + 0x9D)
#define REG_MHL_TMDS_4F_L       (REG_MHL_TMDS_BASE + 0x9E)
#define REG_MHL_TMDS_4F_H       (REG_MHL_TMDS_BASE + 0x9F)
#define REG_MHL_TMDS_50_L       (REG_MHL_TMDS_BASE + 0xA0)
#define REG_MHL_TMDS_50_H       (REG_MHL_TMDS_BASE + 0xA1)
#define REG_MHL_TMDS_51_L       (REG_MHL_TMDS_BASE + 0xA2)
#define REG_MHL_TMDS_51_H       (REG_MHL_TMDS_BASE + 0xA3)
#define REG_MHL_TMDS_52_L       (REG_MHL_TMDS_BASE + 0xA4)
#define REG_MHL_TMDS_52_H       (REG_MHL_TMDS_BASE + 0xA5)
#define REG_MHL_TMDS_53_L       (REG_MHL_TMDS_BASE + 0xA6)
#define REG_MHL_TMDS_53_H       (REG_MHL_TMDS_BASE + 0xA7)
#define REG_MHL_TMDS_54_L       (REG_MHL_TMDS_BASE + 0xA8)
#define REG_MHL_TMDS_54_H       (REG_MHL_TMDS_BASE + 0xA9)
#define REG_MHL_TMDS_55_L       (REG_MHL_TMDS_BASE + 0xAA)
#define REG_MHL_TMDS_55_H       (REG_MHL_TMDS_BASE + 0xAB)
#define REG_MHL_TMDS_56_L       (REG_MHL_TMDS_BASE + 0xAC)
#define REG_MHL_TMDS_56_H       (REG_MHL_TMDS_BASE + 0xAD)
#define REG_MHL_TMDS_57_L       (REG_MHL_TMDS_BASE + 0xAE)
#define REG_MHL_TMDS_57_H       (REG_MHL_TMDS_BASE + 0xAF)
#define REG_MHL_TMDS_58_L       (REG_MHL_TMDS_BASE + 0xB0)
#define REG_MHL_TMDS_58_H       (REG_MHL_TMDS_BASE + 0xB1)
#define REG_MHL_TMDS_59_L       (REG_MHL_TMDS_BASE + 0xB2)
#define REG_MHL_TMDS_59_H       (REG_MHL_TMDS_BASE + 0xB3)
#define REG_MHL_TMDS_5A_L       (REG_MHL_TMDS_BASE + 0xB4)
#define REG_MHL_TMDS_5A_H       (REG_MHL_TMDS_BASE + 0xB5)
#define REG_MHL_TMDS_5B_L       (REG_MHL_TMDS_BASE + 0xB6)
#define REG_MHL_TMDS_5B_H       (REG_MHL_TMDS_BASE + 0xB7)
#define REG_MHL_TMDS_5C_L       (REG_MHL_TMDS_BASE + 0xB8)
#define REG_MHL_TMDS_5C_H       (REG_MHL_TMDS_BASE + 0xB9)
#define REG_MHL_TMDS_5D_L       (REG_MHL_TMDS_BASE + 0xBA)
#define REG_MHL_TMDS_5D_H       (REG_MHL_TMDS_BASE + 0xBB)
#define REG_MHL_TMDS_5E_L       (REG_MHL_TMDS_BASE + 0xBC)
#define REG_MHL_TMDS_5E_H       (REG_MHL_TMDS_BASE + 0xBD)
#define REG_MHL_TMDS_5F_L       (REG_MHL_TMDS_BASE + 0xBE)
#define REG_MHL_TMDS_5F_H       (REG_MHL_TMDS_BASE + 0xBF)
#define REG_MHL_TMDS_60_L       (REG_MHL_TMDS_BASE + 0xC0)
#define REG_MHL_TMDS_60_H       (REG_MHL_TMDS_BASE + 0xC1)
#define REG_MHL_TMDS_61_L       (REG_MHL_TMDS_BASE + 0xC2)
#define REG_MHL_TMDS_61_H       (REG_MHL_TMDS_BASE + 0xC3)
#define REG_MHL_TMDS_62_L       (REG_MHL_TMDS_BASE + 0xC4)
#define REG_MHL_TMDS_62_H       (REG_MHL_TMDS_BASE + 0xC5)
#define REG_MHL_TMDS_63_L       (REG_MHL_TMDS_BASE + 0xC6)
#define REG_MHL_TMDS_63_H       (REG_MHL_TMDS_BASE + 0xC7)
#define REG_MHL_TMDS_64_L       (REG_MHL_TMDS_BASE + 0xC8)
#define REG_MHL_TMDS_64_H       (REG_MHL_TMDS_BASE + 0xC9)
#define REG_MHL_TMDS_65_L       (REG_MHL_TMDS_BASE + 0xCA)
#define REG_MHL_TMDS_65_H       (REG_MHL_TMDS_BASE + 0xCB)
#define REG_MHL_TMDS_66_L       (REG_MHL_TMDS_BASE + 0xCC)
#define REG_MHL_TMDS_66_H       (REG_MHL_TMDS_BASE + 0xCD)
#define REG_MHL_TMDS_67_L       (REG_MHL_TMDS_BASE + 0xCE)
#define REG_MHL_TMDS_67_H       (REG_MHL_TMDS_BASE + 0xCF)
#define REG_MHL_TMDS_68_L       (REG_MHL_TMDS_BASE + 0xD0)
#define REG_MHL_TMDS_68_H       (REG_MHL_TMDS_BASE + 0xD1)
#define REG_MHL_TMDS_69_L       (REG_MHL_TMDS_BASE + 0xD2)
#define REG_MHL_TMDS_69_H       (REG_MHL_TMDS_BASE + 0xD3)
#define REG_MHL_TMDS_6A_L       (REG_MHL_TMDS_BASE + 0xD4)
#define REG_MHL_TMDS_6A_H       (REG_MHL_TMDS_BASE + 0xD5)
#define REG_MHL_TMDS_6B_L       (REG_MHL_TMDS_BASE + 0xD6)
#define REG_MHL_TMDS_6B_H       (REG_MHL_TMDS_BASE + 0xD7)
#define REG_MHL_TMDS_6C_L       (REG_MHL_TMDS_BASE + 0xD8)
#define REG_MHL_TMDS_6C_H       (REG_MHL_TMDS_BASE + 0xD9)
#define REG_MHL_TMDS_6D_L       (REG_MHL_TMDS_BASE + 0xDA)
#define REG_MHL_TMDS_6D_H       (REG_MHL_TMDS_BASE + 0xDB)
#define REG_MHL_TMDS_6E_L       (REG_MHL_TMDS_BASE + 0xDC)
#define REG_MHL_TMDS_6E_H       (REG_MHL_TMDS_BASE + 0xDD)
#define REG_MHL_TMDS_6F_L       (REG_MHL_TMDS_BASE + 0xDE)
#define REG_MHL_TMDS_6F_H       (REG_MHL_TMDS_BASE + 0xDF)
#define REG_MHL_TMDS_70_L       (REG_MHL_TMDS_BASE + 0xE0)
#define REG_MHL_TMDS_70_H       (REG_MHL_TMDS_BASE + 0xE1)
#define REG_MHL_TMDS_71_L       (REG_MHL_TMDS_BASE + 0xE2)
#define REG_MHL_TMDS_71_H       (REG_MHL_TMDS_BASE + 0xE3)
#define REG_MHL_TMDS_72_L       (REG_MHL_TMDS_BASE + 0xE4)
#define REG_MHL_TMDS_72_H       (REG_MHL_TMDS_BASE + 0xE5)
#define REG_MHL_TMDS_73_L       (REG_MHL_TMDS_BASE + 0xE6)
#define REG_MHL_TMDS_73_H       (REG_MHL_TMDS_BASE + 0xE7)
#define REG_MHL_TMDS_74_L       (REG_MHL_TMDS_BASE + 0xE8)
#define REG_MHL_TMDS_74_H       (REG_MHL_TMDS_BASE + 0xE9)
#define REG_MHL_TMDS_75_L       (REG_MHL_TMDS_BASE + 0xEA)
#define REG_MHL_TMDS_75_H       (REG_MHL_TMDS_BASE + 0xEB)
#define REG_MHL_TMDS_76_L       (REG_MHL_TMDS_BASE + 0xEC)
#define REG_MHL_TMDS_76_H       (REG_MHL_TMDS_BASE + 0xED)
#define REG_MHL_TMDS_77_L       (REG_MHL_TMDS_BASE + 0xEE)
#define REG_MHL_TMDS_77_H       (REG_MHL_TMDS_BASE + 0xEF)
#define REG_MHL_TMDS_78_L       (REG_MHL_TMDS_BASE + 0xF0)
#define REG_MHL_TMDS_78_H       (REG_MHL_TMDS_BASE + 0xF1)
#define REG_MHL_TMDS_79_L       (REG_MHL_TMDS_BASE + 0xF2)
#define REG_MHL_TMDS_79_H       (REG_MHL_TMDS_BASE + 0xF3)
#define REG_MHL_TMDS_7A_L       (REG_MHL_TMDS_BASE + 0xF4)
#define REG_MHL_TMDS_7A_H       (REG_MHL_TMDS_BASE + 0xF5)
#define REG_MHL_TMDS_7B_L       (REG_MHL_TMDS_BASE + 0xF6)
#define REG_MHL_TMDS_7B_H       (REG_MHL_TMDS_BASE + 0xF7)
#define REG_MHL_TMDS_7C_L       (REG_MHL_TMDS_BASE + 0xF8)
#define REG_MHL_TMDS_7C_H       (REG_MHL_TMDS_BASE + 0xF9)
#define REG_MHL_TMDS_7D_L       (REG_MHL_TMDS_BASE + 0xFA)
#define REG_MHL_TMDS_7D_H       (REG_MHL_TMDS_BASE + 0xFB)
#define REG_MHL_TMDS_7E_L       (REG_MHL_TMDS_BASE + 0xFC)
#define REG_MHL_TMDS_7E_H       (REG_MHL_TMDS_BASE + 0xFD)
#define REG_MHL_TMDS_7F_L       (REG_MHL_TMDS_BASE + 0xFE)
#define REG_MHL_TMDS_7F_H       (REG_MHL_TMDS_BASE + 0xFF)

//=============================================================

// CHIP
#define REG_CHIP_05_L                (REG_CHIP_BASE + 0x0A)

//CHIP_GPIO1
#define REG_CHIP_GPIO1_10_L          (REG_CHIP_GPIO1_BASE + 0x20)

// COMBO_PHY0_P0
#define REG_COMBO_PHY0_P0_00_L       (REG_COMBO_PHY0_P0_BASE + 0x00)
#define REG_COMBO_PHY0_P0_00_H       (REG_COMBO_PHY0_P0_BASE + 0x01)
#define REG_COMBO_PHY0_P0_01_L       (REG_COMBO_PHY0_P0_BASE + 0x02)
#define REG_COMBO_PHY0_P0_01_H       (REG_COMBO_PHY0_P0_BASE + 0x03)
#define REG_COMBO_PHY0_P0_02_L       (REG_COMBO_PHY0_P0_BASE + 0x04)
#define REG_COMBO_PHY0_P0_02_H       (REG_COMBO_PHY0_P0_BASE + 0x05)
#define REG_COMBO_PHY0_P0_03_L       (REG_COMBO_PHY0_P0_BASE + 0x06)
#define REG_COMBO_PHY0_P0_03_H       (REG_COMBO_PHY0_P0_BASE + 0x07)
#define REG_COMBO_PHY0_P0_04_L       (REG_COMBO_PHY0_P0_BASE + 0x08)
#define REG_COMBO_PHY0_P0_04_H       (REG_COMBO_PHY0_P0_BASE + 0x09)
#define REG_COMBO_PHY0_P0_05_L       (REG_COMBO_PHY0_P0_BASE + 0x0A)
#define REG_COMBO_PHY0_P0_05_H       (REG_COMBO_PHY0_P0_BASE + 0x0B)
#define REG_COMBO_PHY0_P0_06_L       (REG_COMBO_PHY0_P0_BASE + 0x0C)
#define REG_COMBO_PHY0_P0_06_H       (REG_COMBO_PHY0_P0_BASE + 0x0D)
#define REG_COMBO_PHY0_P0_07_L       (REG_COMBO_PHY0_P0_BASE + 0x0E)
#define REG_COMBO_PHY0_P0_07_H       (REG_COMBO_PHY0_P0_BASE + 0x0F)
#define REG_COMBO_PHY0_P0_08_L       (REG_COMBO_PHY0_P0_BASE + 0x10)
#define REG_COMBO_PHY0_P0_08_H       (REG_COMBO_PHY0_P0_BASE + 0x11)
#define REG_COMBO_PHY0_P0_09_L       (REG_COMBO_PHY0_P0_BASE + 0x12)
#define REG_COMBO_PHY0_P0_09_H       (REG_COMBO_PHY0_P0_BASE + 0x13)
#define REG_COMBO_PHY0_P0_0A_L       (REG_COMBO_PHY0_P0_BASE + 0x14)
#define REG_COMBO_PHY0_P0_0A_H       (REG_COMBO_PHY0_P0_BASE + 0x15)
#define REG_COMBO_PHY0_P0_0B_L       (REG_COMBO_PHY0_P0_BASE + 0x16)
#define REG_COMBO_PHY0_P0_0B_H       (REG_COMBO_PHY0_P0_BASE + 0x17)
#define REG_COMBO_PHY0_P0_0C_L       (REG_COMBO_PHY0_P0_BASE + 0x18)
#define REG_COMBO_PHY0_P0_0C_H       (REG_COMBO_PHY0_P0_BASE + 0x19)
#define REG_COMBO_PHY0_P0_0D_L       (REG_COMBO_PHY0_P0_BASE + 0x1A)
#define REG_COMBO_PHY0_P0_0D_H       (REG_COMBO_PHY0_P0_BASE + 0x1B)
#define REG_COMBO_PHY0_P0_0E_L       (REG_COMBO_PHY0_P0_BASE + 0x1C)
#define REG_COMBO_PHY0_P0_0E_H       (REG_COMBO_PHY0_P0_BASE + 0x1D)
#define REG_COMBO_PHY0_P0_0F_L       (REG_COMBO_PHY0_P0_BASE + 0x1E)
#define REG_COMBO_PHY0_P0_0F_H       (REG_COMBO_PHY0_P0_BASE + 0x1F)
#define REG_COMBO_PHY0_P0_10_L       (REG_COMBO_PHY0_P0_BASE + 0x20)
#define REG_COMBO_PHY0_P0_10_H       (REG_COMBO_PHY0_P0_BASE + 0x21)
#define REG_COMBO_PHY0_P0_11_L       (REG_COMBO_PHY0_P0_BASE + 0x22)
#define REG_COMBO_PHY0_P0_11_H       (REG_COMBO_PHY0_P0_BASE + 0x23)
#define REG_COMBO_PHY0_P0_12_L       (REG_COMBO_PHY0_P0_BASE + 0x24)
#define REG_COMBO_PHY0_P0_12_H       (REG_COMBO_PHY0_P0_BASE + 0x25)
#define REG_COMBO_PHY0_P0_13_L       (REG_COMBO_PHY0_P0_BASE + 0x26)
#define REG_COMBO_PHY0_P0_13_H       (REG_COMBO_PHY0_P0_BASE + 0x27)
#define REG_COMBO_PHY0_P0_14_L       (REG_COMBO_PHY0_P0_BASE + 0x28)
#define REG_COMBO_PHY0_P0_14_H       (REG_COMBO_PHY0_P0_BASE + 0x29)
#define REG_COMBO_PHY0_P0_15_L       (REG_COMBO_PHY0_P0_BASE + 0x2A)
#define REG_COMBO_PHY0_P0_15_H       (REG_COMBO_PHY0_P0_BASE + 0x2B)
#define REG_COMBO_PHY0_P0_16_L       (REG_COMBO_PHY0_P0_BASE + 0x2C)
#define REG_COMBO_PHY0_P0_16_H       (REG_COMBO_PHY0_P0_BASE + 0x2D)
#define REG_COMBO_PHY0_P0_17_L       (REG_COMBO_PHY0_P0_BASE + 0x2E)
#define REG_COMBO_PHY0_P0_17_H       (REG_COMBO_PHY0_P0_BASE + 0x2F)
#define REG_COMBO_PHY0_P0_18_L       (REG_COMBO_PHY0_P0_BASE + 0x30)
#define REG_COMBO_PHY0_P0_18_H       (REG_COMBO_PHY0_P0_BASE + 0x31)
#define REG_COMBO_PHY0_P0_19_L       (REG_COMBO_PHY0_P0_BASE + 0x32)
#define REG_COMBO_PHY0_P0_19_H       (REG_COMBO_PHY0_P0_BASE + 0x33)
#define REG_COMBO_PHY0_P0_1A_L       (REG_COMBO_PHY0_P0_BASE + 0x34)
#define REG_COMBO_PHY0_P0_1A_H       (REG_COMBO_PHY0_P0_BASE + 0x35)
#define REG_COMBO_PHY0_P0_1B_L       (REG_COMBO_PHY0_P0_BASE + 0x36)
#define REG_COMBO_PHY0_P0_1B_H       (REG_COMBO_PHY0_P0_BASE + 0x37)
#define REG_COMBO_PHY0_P0_1C_L       (REG_COMBO_PHY0_P0_BASE + 0x38)
#define REG_COMBO_PHY0_P0_1C_H       (REG_COMBO_PHY0_P0_BASE + 0x39)
#define REG_COMBO_PHY0_P0_1D_L       (REG_COMBO_PHY0_P0_BASE + 0x3A)
#define REG_COMBO_PHY0_P0_1D_H       (REG_COMBO_PHY0_P0_BASE + 0x3B)
#define REG_COMBO_PHY0_P0_1E_L       (REG_COMBO_PHY0_P0_BASE + 0x3C)
#define REG_COMBO_PHY0_P0_1E_H       (REG_COMBO_PHY0_P0_BASE + 0x3D)
#define REG_COMBO_PHY0_P0_1F_L       (REG_COMBO_PHY0_P0_BASE + 0x3E)
#define REG_COMBO_PHY0_P0_1F_H       (REG_COMBO_PHY0_P0_BASE + 0x3F)
#define REG_COMBO_PHY0_P0_20_L       (REG_COMBO_PHY0_P0_BASE + 0x40)
#define REG_COMBO_PHY0_P0_20_H       (REG_COMBO_PHY0_P0_BASE + 0x41)
#define REG_COMBO_PHY0_P0_21_L       (REG_COMBO_PHY0_P0_BASE + 0x42)
#define REG_COMBO_PHY0_P0_21_H       (REG_COMBO_PHY0_P0_BASE + 0x43)
#define REG_COMBO_PHY0_P0_22_L       (REG_COMBO_PHY0_P0_BASE + 0x44)
#define REG_COMBO_PHY0_P0_22_H       (REG_COMBO_PHY0_P0_BASE + 0x45)
#define REG_COMBO_PHY0_P0_23_L       (REG_COMBO_PHY0_P0_BASE + 0x46)
#define REG_COMBO_PHY0_P0_23_H       (REG_COMBO_PHY0_P0_BASE + 0x47)
#define REG_COMBO_PHY0_P0_24_L       (REG_COMBO_PHY0_P0_BASE + 0x48)
#define REG_COMBO_PHY0_P0_24_H       (REG_COMBO_PHY0_P0_BASE + 0x49)
#define REG_COMBO_PHY0_P0_25_L       (REG_COMBO_PHY0_P0_BASE + 0x4A)
#define REG_COMBO_PHY0_P0_25_H       (REG_COMBO_PHY0_P0_BASE + 0x4B)
#define REG_COMBO_PHY0_P0_26_L       (REG_COMBO_PHY0_P0_BASE + 0x4C)
#define REG_COMBO_PHY0_P0_26_H       (REG_COMBO_PHY0_P0_BASE + 0x4D)
#define REG_COMBO_PHY0_P0_27_L       (REG_COMBO_PHY0_P0_BASE + 0x4E)
#define REG_COMBO_PHY0_P0_27_H       (REG_COMBO_PHY0_P0_BASE + 0x4F)
#define REG_COMBO_PHY0_P0_28_L       (REG_COMBO_PHY0_P0_BASE + 0x50)
#define REG_COMBO_PHY0_P0_28_H       (REG_COMBO_PHY0_P0_BASE + 0x51)
#define REG_COMBO_PHY0_P0_29_L       (REG_COMBO_PHY0_P0_BASE + 0x52)
#define REG_COMBO_PHY0_P0_29_H       (REG_COMBO_PHY0_P0_BASE + 0x53)
#define REG_COMBO_PHY0_P0_2A_L       (REG_COMBO_PHY0_P0_BASE + 0x54)
#define REG_COMBO_PHY0_P0_2A_H       (REG_COMBO_PHY0_P0_BASE + 0x55)
#define REG_COMBO_PHY0_P0_2B_L       (REG_COMBO_PHY0_P0_BASE + 0x56)
#define REG_COMBO_PHY0_P0_2B_H       (REG_COMBO_PHY0_P0_BASE + 0x57)
#define REG_COMBO_PHY0_P0_2C_L       (REG_COMBO_PHY0_P0_BASE + 0x58)
#define REG_COMBO_PHY0_P0_2C_H       (REG_COMBO_PHY0_P0_BASE + 0x59)
#define REG_COMBO_PHY0_P0_2D_L       (REG_COMBO_PHY0_P0_BASE + 0x5A)
#define REG_COMBO_PHY0_P0_2D_H       (REG_COMBO_PHY0_P0_BASE + 0x5B)
#define REG_COMBO_PHY0_P0_2E_L       (REG_COMBO_PHY0_P0_BASE + 0x5C)
#define REG_COMBO_PHY0_P0_2E_H       (REG_COMBO_PHY0_P0_BASE + 0x5D)
#define REG_COMBO_PHY0_P0_2F_L       (REG_COMBO_PHY0_P0_BASE + 0x5E)
#define REG_COMBO_PHY0_P0_2F_H       (REG_COMBO_PHY0_P0_BASE + 0x5F)
#define REG_COMBO_PHY0_P0_30_L       (REG_COMBO_PHY0_P0_BASE + 0x60)
#define REG_COMBO_PHY0_P0_30_H       (REG_COMBO_PHY0_P0_BASE + 0x61)
#define REG_COMBO_PHY0_P0_31_L       (REG_COMBO_PHY0_P0_BASE + 0x62)
#define REG_COMBO_PHY0_P0_31_H       (REG_COMBO_PHY0_P0_BASE + 0x63)
#define REG_COMBO_PHY0_P0_32_L       (REG_COMBO_PHY0_P0_BASE + 0x64)
#define REG_COMBO_PHY0_P0_32_H       (REG_COMBO_PHY0_P0_BASE + 0x65)
#define REG_COMBO_PHY0_P0_33_L       (REG_COMBO_PHY0_P0_BASE + 0x66)
#define REG_COMBO_PHY0_P0_33_H       (REG_COMBO_PHY0_P0_BASE + 0x67)
#define REG_COMBO_PHY0_P0_34_L       (REG_COMBO_PHY0_P0_BASE + 0x68)
#define REG_COMBO_PHY0_P0_34_H       (REG_COMBO_PHY0_P0_BASE + 0x69)
#define REG_COMBO_PHY0_P0_35_L       (REG_COMBO_PHY0_P0_BASE + 0x6A)
#define REG_COMBO_PHY0_P0_35_H       (REG_COMBO_PHY0_P0_BASE + 0x6B)
#define REG_COMBO_PHY0_P0_36_L       (REG_COMBO_PHY0_P0_BASE + 0x6C)
#define REG_COMBO_PHY0_P0_36_H       (REG_COMBO_PHY0_P0_BASE + 0x6D)
#define REG_COMBO_PHY0_P0_37_L       (REG_COMBO_PHY0_P0_BASE + 0x6E)
#define REG_COMBO_PHY0_P0_37_H       (REG_COMBO_PHY0_P0_BASE + 0x6F)
#define REG_COMBO_PHY0_P0_38_L       (REG_COMBO_PHY0_P0_BASE + 0x70)
#define REG_COMBO_PHY0_P0_38_H       (REG_COMBO_PHY0_P0_BASE + 0x71)
#define REG_COMBO_PHY0_P0_39_L       (REG_COMBO_PHY0_P0_BASE + 0x72)
#define REG_COMBO_PHY0_P0_39_H       (REG_COMBO_PHY0_P0_BASE + 0x73)
#define REG_COMBO_PHY0_P0_3A_L       (REG_COMBO_PHY0_P0_BASE + 0x74)
#define REG_COMBO_PHY0_P0_3A_H       (REG_COMBO_PHY0_P0_BASE + 0x75)
#define REG_COMBO_PHY0_P0_3B_L       (REG_COMBO_PHY0_P0_BASE + 0x76)
#define REG_COMBO_PHY0_P0_3B_H       (REG_COMBO_PHY0_P0_BASE + 0x77)
#define REG_COMBO_PHY0_P0_3C_L       (REG_COMBO_PHY0_P0_BASE + 0x78)
#define REG_COMBO_PHY0_P0_3C_H       (REG_COMBO_PHY0_P0_BASE + 0x79)
#define REG_COMBO_PHY0_P0_3D_L       (REG_COMBO_PHY0_P0_BASE + 0x7A)
#define REG_COMBO_PHY0_P0_3D_H       (REG_COMBO_PHY0_P0_BASE + 0x7B)
#define REG_COMBO_PHY0_P0_3E_L       (REG_COMBO_PHY0_P0_BASE + 0x7C)
#define REG_COMBO_PHY0_P0_3E_H       (REG_COMBO_PHY0_P0_BASE + 0x7D)
#define REG_COMBO_PHY0_P0_3F_L       (REG_COMBO_PHY0_P0_BASE + 0x7E)
#define REG_COMBO_PHY0_P0_3F_H       (REG_COMBO_PHY0_P0_BASE + 0x7F)
#define REG_COMBO_PHY0_P0_40_L       (REG_COMBO_PHY0_P0_BASE + 0x80)
#define REG_COMBO_PHY0_P0_40_H       (REG_COMBO_PHY0_P0_BASE + 0x81)
#define REG_COMBO_PHY0_P0_41_L       (REG_COMBO_PHY0_P0_BASE + 0x82)
#define REG_COMBO_PHY0_P0_41_H       (REG_COMBO_PHY0_P0_BASE + 0x83)
#define REG_COMBO_PHY0_P0_42_L       (REG_COMBO_PHY0_P0_BASE + 0x84)
#define REG_COMBO_PHY0_P0_42_H       (REG_COMBO_PHY0_P0_BASE + 0x85)
#define REG_COMBO_PHY0_P0_43_L       (REG_COMBO_PHY0_P0_BASE + 0x86)
#define REG_COMBO_PHY0_P0_43_H       (REG_COMBO_PHY0_P0_BASE + 0x87)
#define REG_COMBO_PHY0_P0_44_L       (REG_COMBO_PHY0_P0_BASE + 0x88)
#define REG_COMBO_PHY0_P0_44_H       (REG_COMBO_PHY0_P0_BASE + 0x89)
#define REG_COMBO_PHY0_P0_45_L       (REG_COMBO_PHY0_P0_BASE + 0x8A)
#define REG_COMBO_PHY0_P0_45_H       (REG_COMBO_PHY0_P0_BASE + 0x8B)
#define REG_COMBO_PHY0_P0_46_L       (REG_COMBO_PHY0_P0_BASE + 0x8C)
#define REG_COMBO_PHY0_P0_46_H       (REG_COMBO_PHY0_P0_BASE + 0x8D)
#define REG_COMBO_PHY0_P0_47_L       (REG_COMBO_PHY0_P0_BASE + 0x8E)
#define REG_COMBO_PHY0_P0_47_H       (REG_COMBO_PHY0_P0_BASE + 0x8F)
#define REG_COMBO_PHY0_P0_48_L       (REG_COMBO_PHY0_P0_BASE + 0x90)
#define REG_COMBO_PHY0_P0_48_H       (REG_COMBO_PHY0_P0_BASE + 0x91)
#define REG_COMBO_PHY0_P0_49_L       (REG_COMBO_PHY0_P0_BASE + 0x92)
#define REG_COMBO_PHY0_P0_49_H       (REG_COMBO_PHY0_P0_BASE + 0x93)
#define REG_COMBO_PHY0_P0_4A_L       (REG_COMBO_PHY0_P0_BASE + 0x94)
#define REG_COMBO_PHY0_P0_4A_H       (REG_COMBO_PHY0_P0_BASE + 0x95)
#define REG_COMBO_PHY0_P0_4B_L       (REG_COMBO_PHY0_P0_BASE + 0x96)
#define REG_COMBO_PHY0_P0_4B_H       (REG_COMBO_PHY0_P0_BASE + 0x97)
#define REG_COMBO_PHY0_P0_4C_L       (REG_COMBO_PHY0_P0_BASE + 0x98)
#define REG_COMBO_PHY0_P0_4C_H       (REG_COMBO_PHY0_P0_BASE + 0x99)
#define REG_COMBO_PHY0_P0_4D_L       (REG_COMBO_PHY0_P0_BASE + 0x9A)
#define REG_COMBO_PHY0_P0_4D_H       (REG_COMBO_PHY0_P0_BASE + 0x9B)
#define REG_COMBO_PHY0_P0_4E_L       (REG_COMBO_PHY0_P0_BASE + 0x9C)
#define REG_COMBO_PHY0_P0_4E_H       (REG_COMBO_PHY0_P0_BASE + 0x9D)
#define REG_COMBO_PHY0_P0_4F_L       (REG_COMBO_PHY0_P0_BASE + 0x9E)
#define REG_COMBO_PHY0_P0_4F_H       (REG_COMBO_PHY0_P0_BASE + 0x9F)
#define REG_COMBO_PHY0_P0_50_L       (REG_COMBO_PHY0_P0_BASE + 0xA0)
#define REG_COMBO_PHY0_P0_50_H       (REG_COMBO_PHY0_P0_BASE + 0xA1)
#define REG_COMBO_PHY0_P0_51_L       (REG_COMBO_PHY0_P0_BASE + 0xA2)
#define REG_COMBO_PHY0_P0_51_H       (REG_COMBO_PHY0_P0_BASE + 0xA3)
#define REG_COMBO_PHY0_P0_52_L       (REG_COMBO_PHY0_P0_BASE + 0xA4)
#define REG_COMBO_PHY0_P0_52_H       (REG_COMBO_PHY0_P0_BASE + 0xA5)
#define REG_COMBO_PHY0_P0_53_L       (REG_COMBO_PHY0_P0_BASE + 0xA6)
#define REG_COMBO_PHY0_P0_53_H       (REG_COMBO_PHY0_P0_BASE + 0xA7)
#define REG_COMBO_PHY0_P0_54_L       (REG_COMBO_PHY0_P0_BASE + 0xA8)
#define REG_COMBO_PHY0_P0_54_H       (REG_COMBO_PHY0_P0_BASE + 0xA9)
#define REG_COMBO_PHY0_P0_55_L       (REG_COMBO_PHY0_P0_BASE + 0xAA)
#define REG_COMBO_PHY0_P0_55_H       (REG_COMBO_PHY0_P0_BASE + 0xAB)
#define REG_COMBO_PHY0_P0_56_L       (REG_COMBO_PHY0_P0_BASE + 0xAC)
#define REG_COMBO_PHY0_P0_56_H       (REG_COMBO_PHY0_P0_BASE + 0xAD)
#define REG_COMBO_PHY0_P0_57_L       (REG_COMBO_PHY0_P0_BASE + 0xAE)
#define REG_COMBO_PHY0_P0_57_H       (REG_COMBO_PHY0_P0_BASE + 0xAF)
#define REG_COMBO_PHY0_P0_58_L       (REG_COMBO_PHY0_P0_BASE + 0xB0)
#define REG_COMBO_PHY0_P0_58_H       (REG_COMBO_PHY0_P0_BASE + 0xB1)
#define REG_COMBO_PHY0_P0_59_L       (REG_COMBO_PHY0_P0_BASE + 0xB2)
#define REG_COMBO_PHY0_P0_59_H       (REG_COMBO_PHY0_P0_BASE + 0xB3)
#define REG_COMBO_PHY0_P0_5A_L       (REG_COMBO_PHY0_P0_BASE + 0xB4)
#define REG_COMBO_PHY0_P0_5A_H       (REG_COMBO_PHY0_P0_BASE + 0xB5)
#define REG_COMBO_PHY0_P0_5B_L       (REG_COMBO_PHY0_P0_BASE + 0xB6)
#define REG_COMBO_PHY0_P0_5B_H       (REG_COMBO_PHY0_P0_BASE + 0xB7)
#define REG_COMBO_PHY0_P0_5C_L       (REG_COMBO_PHY0_P0_BASE + 0xB8)
#define REG_COMBO_PHY0_P0_5C_H       (REG_COMBO_PHY0_P0_BASE + 0xB9)
#define REG_COMBO_PHY0_P0_5D_L       (REG_COMBO_PHY0_P0_BASE + 0xBA)
#define REG_COMBO_PHY0_P0_5D_H       (REG_COMBO_PHY0_P0_BASE + 0xBB)
#define REG_COMBO_PHY0_P0_5E_L       (REG_COMBO_PHY0_P0_BASE + 0xBC)
#define REG_COMBO_PHY0_P0_5E_H       (REG_COMBO_PHY0_P0_BASE + 0xBD)
#define REG_COMBO_PHY0_P0_5F_L       (REG_COMBO_PHY0_P0_BASE + 0xBE)
#define REG_COMBO_PHY0_P0_5F_H       (REG_COMBO_PHY0_P0_BASE + 0xBF)
#define REG_COMBO_PHY0_P0_60_L       (REG_COMBO_PHY0_P0_BASE + 0xC0)
#define REG_COMBO_PHY0_P0_60_H       (REG_COMBO_PHY0_P0_BASE + 0xC1)
#define REG_COMBO_PHY0_P0_61_L       (REG_COMBO_PHY0_P0_BASE + 0xC2)
#define REG_COMBO_PHY0_P0_61_H       (REG_COMBO_PHY0_P0_BASE + 0xC3)
#define REG_COMBO_PHY0_P0_62_L       (REG_COMBO_PHY0_P0_BASE + 0xC4)
#define REG_COMBO_PHY0_P0_62_H       (REG_COMBO_PHY0_P0_BASE + 0xC5)
#define REG_COMBO_PHY0_P0_63_L       (REG_COMBO_PHY0_P0_BASE + 0xC6)
#define REG_COMBO_PHY0_P0_63_H       (REG_COMBO_PHY0_P0_BASE + 0xC7)
#define REG_COMBO_PHY0_P0_64_L       (REG_COMBO_PHY0_P0_BASE + 0xC8)
#define REG_COMBO_PHY0_P0_64_H       (REG_COMBO_PHY0_P0_BASE + 0xC9)
#define REG_COMBO_PHY0_P0_65_L       (REG_COMBO_PHY0_P0_BASE + 0xCA)
#define REG_COMBO_PHY0_P0_65_H       (REG_COMBO_PHY0_P0_BASE + 0xCB)
#define REG_COMBO_PHY0_P0_66_L       (REG_COMBO_PHY0_P0_BASE + 0xCC)
#define REG_COMBO_PHY0_P0_66_H       (REG_COMBO_PHY0_P0_BASE + 0xCD)
#define REG_COMBO_PHY0_P0_67_L       (REG_COMBO_PHY0_P0_BASE + 0xCE)
#define REG_COMBO_PHY0_P0_67_H       (REG_COMBO_PHY0_P0_BASE + 0xCF)
#define REG_COMBO_PHY0_P0_68_L       (REG_COMBO_PHY0_P0_BASE + 0xD0)
#define REG_COMBO_PHY0_P0_68_H       (REG_COMBO_PHY0_P0_BASE + 0xD1)
#define REG_COMBO_PHY0_P0_69_L       (REG_COMBO_PHY0_P0_BASE + 0xD2)
#define REG_COMBO_PHY0_P0_69_H       (REG_COMBO_PHY0_P0_BASE + 0xD3)
#define REG_COMBO_PHY0_P0_6A_L       (REG_COMBO_PHY0_P0_BASE + 0xD4)
#define REG_COMBO_PHY0_P0_6A_H       (REG_COMBO_PHY0_P0_BASE + 0xD5)
#define REG_COMBO_PHY0_P0_6B_L       (REG_COMBO_PHY0_P0_BASE + 0xD6)
#define REG_COMBO_PHY0_P0_6B_H       (REG_COMBO_PHY0_P0_BASE + 0xD7)
#define REG_COMBO_PHY0_P0_6C_L       (REG_COMBO_PHY0_P0_BASE + 0xD8)
#define REG_COMBO_PHY0_P0_6C_H       (REG_COMBO_PHY0_P0_BASE + 0xD9)
#define REG_COMBO_PHY0_P0_6D_L       (REG_COMBO_PHY0_P0_BASE + 0xDA)
#define REG_COMBO_PHY0_P0_6D_H       (REG_COMBO_PHY0_P0_BASE + 0xDB)
#define REG_COMBO_PHY0_P0_6E_L       (REG_COMBO_PHY0_P0_BASE + 0xDC)
#define REG_COMBO_PHY0_P0_6E_H       (REG_COMBO_PHY0_P0_BASE + 0xDD)
#define REG_COMBO_PHY0_P0_6F_L       (REG_COMBO_PHY0_P0_BASE + 0xDE)
#define REG_COMBO_PHY0_P0_6F_H       (REG_COMBO_PHY0_P0_BASE + 0xDF)
#define REG_COMBO_PHY0_P0_70_L       (REG_COMBO_PHY0_P0_BASE + 0xE0)
#define REG_COMBO_PHY0_P0_70_H       (REG_COMBO_PHY0_P0_BASE + 0xE1)
#define REG_COMBO_PHY0_P0_71_L       (REG_COMBO_PHY0_P0_BASE + 0xE2)
#define REG_COMBO_PHY0_P0_71_H       (REG_COMBO_PHY0_P0_BASE + 0xE3)
#define REG_COMBO_PHY0_P0_72_L       (REG_COMBO_PHY0_P0_BASE + 0xE4)
#define REG_COMBO_PHY0_P0_72_H       (REG_COMBO_PHY0_P0_BASE + 0xE5)
#define REG_COMBO_PHY0_P0_73_L       (REG_COMBO_PHY0_P0_BASE + 0xE6)
#define REG_COMBO_PHY0_P0_73_H       (REG_COMBO_PHY0_P0_BASE + 0xE7)
#define REG_COMBO_PHY0_P0_74_L       (REG_COMBO_PHY0_P0_BASE + 0xE8)
#define REG_COMBO_PHY0_P0_74_H       (REG_COMBO_PHY0_P0_BASE + 0xE9)
#define REG_COMBO_PHY0_P0_75_L       (REG_COMBO_PHY0_P0_BASE + 0xEA)
#define REG_COMBO_PHY0_P0_75_H       (REG_COMBO_PHY0_P0_BASE + 0xEB)
#define REG_COMBO_PHY0_P0_76_L       (REG_COMBO_PHY0_P0_BASE + 0xEC)
#define REG_COMBO_PHY0_P0_76_H       (REG_COMBO_PHY0_P0_BASE + 0xED)
#define REG_COMBO_PHY0_P0_77_L       (REG_COMBO_PHY0_P0_BASE + 0xEE)
#define REG_COMBO_PHY0_P0_77_H       (REG_COMBO_PHY0_P0_BASE + 0xEF)
#define REG_COMBO_PHY0_P0_78_L       (REG_COMBO_PHY0_P0_BASE + 0xF0)
#define REG_COMBO_PHY0_P0_78_H       (REG_COMBO_PHY0_P0_BASE + 0xF1)
#define REG_COMBO_PHY0_P0_79_L       (REG_COMBO_PHY0_P0_BASE + 0xF2)
#define REG_COMBO_PHY0_P0_79_H       (REG_COMBO_PHY0_P0_BASE + 0xF3)
#define REG_COMBO_PHY0_P0_7A_L       (REG_COMBO_PHY0_P0_BASE + 0xF4)
#define REG_COMBO_PHY0_P0_7A_H       (REG_COMBO_PHY0_P0_BASE + 0xF5)
#define REG_COMBO_PHY0_P0_7B_L       (REG_COMBO_PHY0_P0_BASE + 0xF6)
#define REG_COMBO_PHY0_P0_7B_H       (REG_COMBO_PHY0_P0_BASE + 0xF7)
#define REG_COMBO_PHY0_P0_7C_L       (REG_COMBO_PHY0_P0_BASE + 0xF8)
#define REG_COMBO_PHY0_P0_7C_H       (REG_COMBO_PHY0_P0_BASE + 0xF9)
#define REG_COMBO_PHY0_P0_7D_L       (REG_COMBO_PHY0_P0_BASE + 0xFA)
#define REG_COMBO_PHY0_P0_7D_H       (REG_COMBO_PHY0_P0_BASE + 0xFB)
#define REG_COMBO_PHY0_P0_7E_L       (REG_COMBO_PHY0_P0_BASE + 0xFC)
#define REG_COMBO_PHY0_P0_7E_H       (REG_COMBO_PHY0_P0_BASE + 0xFD)
#define REG_COMBO_PHY0_P0_7F_L       (REG_COMBO_PHY0_P0_BASE + 0xFE)
#define REG_COMBO_PHY0_P0_7F_H       (REG_COMBO_PHY0_P0_BASE + 0xFF)

// COMBO_PHY1_P0
#define REG_COMBO_PHY1_P0_00_L       (REG_COMBO_PHY1_P0_BASE + 0x00)
#define REG_COMBO_PHY1_P0_00_H       (REG_COMBO_PHY1_P0_BASE + 0x01)
#define REG_COMBO_PHY1_P0_01_L       (REG_COMBO_PHY1_P0_BASE + 0x02)
#define REG_COMBO_PHY1_P0_01_H       (REG_COMBO_PHY1_P0_BASE + 0x03)
#define REG_COMBO_PHY1_P0_02_L       (REG_COMBO_PHY1_P0_BASE + 0x04)
#define REG_COMBO_PHY1_P0_02_H       (REG_COMBO_PHY1_P0_BASE + 0x05)
#define REG_COMBO_PHY1_P0_03_L       (REG_COMBO_PHY1_P0_BASE + 0x06)
#define REG_COMBO_PHY1_P0_03_H       (REG_COMBO_PHY1_P0_BASE + 0x07)
#define REG_COMBO_PHY1_P0_04_L       (REG_COMBO_PHY1_P0_BASE + 0x08)
#define REG_COMBO_PHY1_P0_04_H       (REG_COMBO_PHY1_P0_BASE + 0x09)
#define REG_COMBO_PHY1_P0_05_L       (REG_COMBO_PHY1_P0_BASE + 0x0A)
#define REG_COMBO_PHY1_P0_05_H       (REG_COMBO_PHY1_P0_BASE + 0x0B)
#define REG_COMBO_PHY1_P0_06_L       (REG_COMBO_PHY1_P0_BASE + 0x0C)
#define REG_COMBO_PHY1_P0_06_H       (REG_COMBO_PHY1_P0_BASE + 0x0D)
#define REG_COMBO_PHY1_P0_07_L       (REG_COMBO_PHY1_P0_BASE + 0x0E)
#define REG_COMBO_PHY1_P0_07_H       (REG_COMBO_PHY1_P0_BASE + 0x0F)
#define REG_COMBO_PHY1_P0_08_L       (REG_COMBO_PHY1_P0_BASE + 0x10)
#define REG_COMBO_PHY1_P0_08_H       (REG_COMBO_PHY1_P0_BASE + 0x11)
#define REG_COMBO_PHY1_P0_09_L       (REG_COMBO_PHY1_P0_BASE + 0x12)
#define REG_COMBO_PHY1_P0_09_H       (REG_COMBO_PHY1_P0_BASE + 0x13)
#define REG_COMBO_PHY1_P0_0A_L       (REG_COMBO_PHY1_P0_BASE + 0x14)
#define REG_COMBO_PHY1_P0_0A_H       (REG_COMBO_PHY1_P0_BASE + 0x15)
#define REG_COMBO_PHY1_P0_0B_L       (REG_COMBO_PHY1_P0_BASE + 0x16)
#define REG_COMBO_PHY1_P0_0B_H       (REG_COMBO_PHY1_P0_BASE + 0x17)
#define REG_COMBO_PHY1_P0_0C_L       (REG_COMBO_PHY1_P0_BASE + 0x18)
#define REG_COMBO_PHY1_P0_0C_H       (REG_COMBO_PHY1_P0_BASE + 0x19)
#define REG_COMBO_PHY1_P0_0D_L       (REG_COMBO_PHY1_P0_BASE + 0x1A)
#define REG_COMBO_PHY1_P0_0D_H       (REG_COMBO_PHY1_P0_BASE + 0x1B)
#define REG_COMBO_PHY1_P0_0E_L       (REG_COMBO_PHY1_P0_BASE + 0x1C)
#define REG_COMBO_PHY1_P0_0E_H       (REG_COMBO_PHY1_P0_BASE + 0x1D)
#define REG_COMBO_PHY1_P0_0F_L       (REG_COMBO_PHY1_P0_BASE + 0x1E)
#define REG_COMBO_PHY1_P0_0F_H       (REG_COMBO_PHY1_P0_BASE + 0x1F)
#define REG_COMBO_PHY1_P0_10_L       (REG_COMBO_PHY1_P0_BASE + 0x20)
#define REG_COMBO_PHY1_P0_10_H       (REG_COMBO_PHY1_P0_BASE + 0x21)
#define REG_COMBO_PHY1_P0_11_L       (REG_COMBO_PHY1_P0_BASE + 0x22)
#define REG_COMBO_PHY1_P0_11_H       (REG_COMBO_PHY1_P0_BASE + 0x23)
#define REG_COMBO_PHY1_P0_12_L       (REG_COMBO_PHY1_P0_BASE + 0x24)
#define REG_COMBO_PHY1_P0_12_H       (REG_COMBO_PHY1_P0_BASE + 0x25)
#define REG_COMBO_PHY1_P0_13_L       (REG_COMBO_PHY1_P0_BASE + 0x26)
#define REG_COMBO_PHY1_P0_13_H       (REG_COMBO_PHY1_P0_BASE + 0x27)
#define REG_COMBO_PHY1_P0_14_L       (REG_COMBO_PHY1_P0_BASE + 0x28)
#define REG_COMBO_PHY1_P0_14_H       (REG_COMBO_PHY1_P0_BASE + 0x29)
#define REG_COMBO_PHY1_P0_15_L       (REG_COMBO_PHY1_P0_BASE + 0x2A)
#define REG_COMBO_PHY1_P0_15_H       (REG_COMBO_PHY1_P0_BASE + 0x2B)
#define REG_COMBO_PHY1_P0_16_L       (REG_COMBO_PHY1_P0_BASE + 0x2C)
#define REG_COMBO_PHY1_P0_16_H       (REG_COMBO_PHY1_P0_BASE + 0x2D)
#define REG_COMBO_PHY1_P0_17_L       (REG_COMBO_PHY1_P0_BASE + 0x2E)
#define REG_COMBO_PHY1_P0_17_H       (REG_COMBO_PHY1_P0_BASE + 0x2F)
#define REG_COMBO_PHY1_P0_18_L       (REG_COMBO_PHY1_P0_BASE + 0x30)
#define REG_COMBO_PHY1_P0_18_H       (REG_COMBO_PHY1_P0_BASE + 0x31)
#define REG_COMBO_PHY1_P0_19_L       (REG_COMBO_PHY1_P0_BASE + 0x32)
#define REG_COMBO_PHY1_P0_19_H       (REG_COMBO_PHY1_P0_BASE + 0x33)
#define REG_COMBO_PHY1_P0_1A_L       (REG_COMBO_PHY1_P0_BASE + 0x34)
#define REG_COMBO_PHY1_P0_1A_H       (REG_COMBO_PHY1_P0_BASE + 0x35)
#define REG_COMBO_PHY1_P0_1B_L       (REG_COMBO_PHY1_P0_BASE + 0x36)
#define REG_COMBO_PHY1_P0_1B_H       (REG_COMBO_PHY1_P0_BASE + 0x37)
#define REG_COMBO_PHY1_P0_1C_L       (REG_COMBO_PHY1_P0_BASE + 0x38)
#define REG_COMBO_PHY1_P0_1C_H       (REG_COMBO_PHY1_P0_BASE + 0x39)
#define REG_COMBO_PHY1_P0_1D_L       (REG_COMBO_PHY1_P0_BASE + 0x3A)
#define REG_COMBO_PHY1_P0_1D_H       (REG_COMBO_PHY1_P0_BASE + 0x3B)
#define REG_COMBO_PHY1_P0_1E_L       (REG_COMBO_PHY1_P0_BASE + 0x3C)
#define REG_COMBO_PHY1_P0_1E_H       (REG_COMBO_PHY1_P0_BASE + 0x3D)
#define REG_COMBO_PHY1_P0_1F_L       (REG_COMBO_PHY1_P0_BASE + 0x3E)
#define REG_COMBO_PHY1_P0_1F_H       (REG_COMBO_PHY1_P0_BASE + 0x3F)
#define REG_COMBO_PHY1_P0_20_L       (REG_COMBO_PHY1_P0_BASE + 0x40)
#define REG_COMBO_PHY1_P0_20_H       (REG_COMBO_PHY1_P0_BASE + 0x41)
#define REG_COMBO_PHY1_P0_21_L       (REG_COMBO_PHY1_P0_BASE + 0x42)
#define REG_COMBO_PHY1_P0_21_H       (REG_COMBO_PHY1_P0_BASE + 0x43)
#define REG_COMBO_PHY1_P0_22_L       (REG_COMBO_PHY1_P0_BASE + 0x44)
#define REG_COMBO_PHY1_P0_22_H       (REG_COMBO_PHY1_P0_BASE + 0x45)
#define REG_COMBO_PHY1_P0_23_L       (REG_COMBO_PHY1_P0_BASE + 0x46)
#define REG_COMBO_PHY1_P0_23_H       (REG_COMBO_PHY1_P0_BASE + 0x47)
#define REG_COMBO_PHY1_P0_24_L       (REG_COMBO_PHY1_P0_BASE + 0x48)
#define REG_COMBO_PHY1_P0_24_H       (REG_COMBO_PHY1_P0_BASE + 0x49)
#define REG_COMBO_PHY1_P0_25_L       (REG_COMBO_PHY1_P0_BASE + 0x4A)
#define REG_COMBO_PHY1_P0_25_H       (REG_COMBO_PHY1_P0_BASE + 0x4B)
#define REG_COMBO_PHY1_P0_26_L       (REG_COMBO_PHY1_P0_BASE + 0x4C)
#define REG_COMBO_PHY1_P0_26_H       (REG_COMBO_PHY1_P0_BASE + 0x4D)
#define REG_COMBO_PHY1_P0_27_L       (REG_COMBO_PHY1_P0_BASE + 0x4E)
#define REG_COMBO_PHY1_P0_27_H       (REG_COMBO_PHY1_P0_BASE + 0x4F)
#define REG_COMBO_PHY1_P0_28_L       (REG_COMBO_PHY1_P0_BASE + 0x50)
#define REG_COMBO_PHY1_P0_28_H       (REG_COMBO_PHY1_P0_BASE + 0x51)
#define REG_COMBO_PHY1_P0_29_L       (REG_COMBO_PHY1_P0_BASE + 0x52)
#define REG_COMBO_PHY1_P0_29_H       (REG_COMBO_PHY1_P0_BASE + 0x53)
#define REG_COMBO_PHY1_P0_2A_L       (REG_COMBO_PHY1_P0_BASE + 0x54)
#define REG_COMBO_PHY1_P0_2A_H       (REG_COMBO_PHY1_P0_BASE + 0x55)
#define REG_COMBO_PHY1_P0_2B_L       (REG_COMBO_PHY1_P0_BASE + 0x56)
#define REG_COMBO_PHY1_P0_2B_H       (REG_COMBO_PHY1_P0_BASE + 0x57)
#define REG_COMBO_PHY1_P0_2C_L       (REG_COMBO_PHY1_P0_BASE + 0x58)
#define REG_COMBO_PHY1_P0_2C_H       (REG_COMBO_PHY1_P0_BASE + 0x59)
#define REG_COMBO_PHY1_P0_2D_L       (REG_COMBO_PHY1_P0_BASE + 0x5A)
#define REG_COMBO_PHY1_P0_2D_H       (REG_COMBO_PHY1_P0_BASE + 0x5B)
#define REG_COMBO_PHY1_P0_2E_L       (REG_COMBO_PHY1_P0_BASE + 0x5C)
#define REG_COMBO_PHY1_P0_2E_H       (REG_COMBO_PHY1_P0_BASE + 0x5D)
#define REG_COMBO_PHY1_P0_2F_L       (REG_COMBO_PHY1_P0_BASE + 0x5E)
#define REG_COMBO_PHY1_P0_2F_H       (REG_COMBO_PHY1_P0_BASE + 0x5F)
#define REG_COMBO_PHY1_P0_30_L       (REG_COMBO_PHY1_P0_BASE + 0x60)
#define REG_COMBO_PHY1_P0_30_H       (REG_COMBO_PHY1_P0_BASE + 0x61)
#define REG_COMBO_PHY1_P0_31_L       (REG_COMBO_PHY1_P0_BASE + 0x62)
#define REG_COMBO_PHY1_P0_31_H       (REG_COMBO_PHY1_P0_BASE + 0x63)
#define REG_COMBO_PHY1_P0_32_L       (REG_COMBO_PHY1_P0_BASE + 0x64)
#define REG_COMBO_PHY1_P0_32_H       (REG_COMBO_PHY1_P0_BASE + 0x65)
#define REG_COMBO_PHY1_P0_33_L       (REG_COMBO_PHY1_P0_BASE + 0x66)
#define REG_COMBO_PHY1_P0_33_H       (REG_COMBO_PHY1_P0_BASE + 0x67)
#define REG_COMBO_PHY1_P0_34_L       (REG_COMBO_PHY1_P0_BASE + 0x68)
#define REG_COMBO_PHY1_P0_34_H       (REG_COMBO_PHY1_P0_BASE + 0x69)
#define REG_COMBO_PHY1_P0_35_L       (REG_COMBO_PHY1_P0_BASE + 0x6A)
#define REG_COMBO_PHY1_P0_35_H       (REG_COMBO_PHY1_P0_BASE + 0x6B)
#define REG_COMBO_PHY1_P0_36_L       (REG_COMBO_PHY1_P0_BASE + 0x6C)
#define REG_COMBO_PHY1_P0_36_H       (REG_COMBO_PHY1_P0_BASE + 0x6D)
#define REG_COMBO_PHY1_P0_37_L       (REG_COMBO_PHY1_P0_BASE + 0x6E)
#define REG_COMBO_PHY1_P0_37_H       (REG_COMBO_PHY1_P0_BASE + 0x6F)
#define REG_COMBO_PHY1_P0_38_L       (REG_COMBO_PHY1_P0_BASE + 0x70)
#define REG_COMBO_PHY1_P0_38_H       (REG_COMBO_PHY1_P0_BASE + 0x71)
#define REG_COMBO_PHY1_P0_39_L       (REG_COMBO_PHY1_P0_BASE + 0x72)
#define REG_COMBO_PHY1_P0_39_H       (REG_COMBO_PHY1_P0_BASE + 0x73)
#define REG_COMBO_PHY1_P0_3A_L       (REG_COMBO_PHY1_P0_BASE + 0x74)
#define REG_COMBO_PHY1_P0_3A_H       (REG_COMBO_PHY1_P0_BASE + 0x75)
#define REG_COMBO_PHY1_P0_3B_L       (REG_COMBO_PHY1_P0_BASE + 0x76)
#define REG_COMBO_PHY1_P0_3B_H       (REG_COMBO_PHY1_P0_BASE + 0x77)
#define REG_COMBO_PHY1_P0_3C_L       (REG_COMBO_PHY1_P0_BASE + 0x78)
#define REG_COMBO_PHY1_P0_3C_H       (REG_COMBO_PHY1_P0_BASE + 0x79)
#define REG_COMBO_PHY1_P0_3D_L       (REG_COMBO_PHY1_P0_BASE + 0x7A)
#define REG_COMBO_PHY1_P0_3D_H       (REG_COMBO_PHY1_P0_BASE + 0x7B)
#define REG_COMBO_PHY1_P0_3E_L       (REG_COMBO_PHY1_P0_BASE + 0x7C)
#define REG_COMBO_PHY1_P0_3E_H       (REG_COMBO_PHY1_P0_BASE + 0x7D)
#define REG_COMBO_PHY1_P0_3F_L       (REG_COMBO_PHY1_P0_BASE + 0x7E)
#define REG_COMBO_PHY1_P0_3F_H       (REG_COMBO_PHY1_P0_BASE + 0x7F)
#define REG_COMBO_PHY1_P0_40_L       (REG_COMBO_PHY1_P0_BASE + 0x80)
#define REG_COMBO_PHY1_P0_40_H       (REG_COMBO_PHY1_P0_BASE + 0x81)
#define REG_COMBO_PHY1_P0_41_L       (REG_COMBO_PHY1_P0_BASE + 0x82)
#define REG_COMBO_PHY1_P0_41_H       (REG_COMBO_PHY1_P0_BASE + 0x83)
#define REG_COMBO_PHY1_P0_42_L       (REG_COMBO_PHY1_P0_BASE + 0x84)
#define REG_COMBO_PHY1_P0_42_H       (REG_COMBO_PHY1_P0_BASE + 0x85)
#define REG_COMBO_PHY1_P0_43_L       (REG_COMBO_PHY1_P0_BASE + 0x86)
#define REG_COMBO_PHY1_P0_43_H       (REG_COMBO_PHY1_P0_BASE + 0x87)
#define REG_COMBO_PHY1_P0_44_L       (REG_COMBO_PHY1_P0_BASE + 0x88)
#define REG_COMBO_PHY1_P0_44_H       (REG_COMBO_PHY1_P0_BASE + 0x89)
#define REG_COMBO_PHY1_P0_45_L       (REG_COMBO_PHY1_P0_BASE + 0x8A)
#define REG_COMBO_PHY1_P0_45_H       (REG_COMBO_PHY1_P0_BASE + 0x8B)
#define REG_COMBO_PHY1_P0_46_L       (REG_COMBO_PHY1_P0_BASE + 0x8C)
#define REG_COMBO_PHY1_P0_46_H       (REG_COMBO_PHY1_P0_BASE + 0x8D)
#define REG_COMBO_PHY1_P0_47_L       (REG_COMBO_PHY1_P0_BASE + 0x8E)
#define REG_COMBO_PHY1_P0_47_H       (REG_COMBO_PHY1_P0_BASE + 0x8F)
#define REG_COMBO_PHY1_P0_48_L       (REG_COMBO_PHY1_P0_BASE + 0x90)
#define REG_COMBO_PHY1_P0_48_H       (REG_COMBO_PHY1_P0_BASE + 0x91)
#define REG_COMBO_PHY1_P0_49_L       (REG_COMBO_PHY1_P0_BASE + 0x92)
#define REG_COMBO_PHY1_P0_49_H       (REG_COMBO_PHY1_P0_BASE + 0x93)
#define REG_COMBO_PHY1_P0_4A_L       (REG_COMBO_PHY1_P0_BASE + 0x94)
#define REG_COMBO_PHY1_P0_4A_H       (REG_COMBO_PHY1_P0_BASE + 0x95)
#define REG_COMBO_PHY1_P0_4B_L       (REG_COMBO_PHY1_P0_BASE + 0x96)
#define REG_COMBO_PHY1_P0_4B_H       (REG_COMBO_PHY1_P0_BASE + 0x97)
#define REG_COMBO_PHY1_P0_4C_L       (REG_COMBO_PHY1_P0_BASE + 0x98)
#define REG_COMBO_PHY1_P0_4C_H       (REG_COMBO_PHY1_P0_BASE + 0x99)
#define REG_COMBO_PHY1_P0_4D_L       (REG_COMBO_PHY1_P0_BASE + 0x9A)
#define REG_COMBO_PHY1_P0_4D_H       (REG_COMBO_PHY1_P0_BASE + 0x9B)
#define REG_COMBO_PHY1_P0_4E_L       (REG_COMBO_PHY1_P0_BASE + 0x9C)
#define REG_COMBO_PHY1_P0_4E_H       (REG_COMBO_PHY1_P0_BASE + 0x9D)
#define REG_COMBO_PHY1_P0_4F_L       (REG_COMBO_PHY1_P0_BASE + 0x9E)
#define REG_COMBO_PHY1_P0_4F_H       (REG_COMBO_PHY1_P0_BASE + 0x9F)
#define REG_COMBO_PHY1_P0_50_L       (REG_COMBO_PHY1_P0_BASE + 0xA0)
#define REG_COMBO_PHY1_P0_50_H       (REG_COMBO_PHY1_P0_BASE + 0xA1)
#define REG_COMBO_PHY1_P0_51_L       (REG_COMBO_PHY1_P0_BASE + 0xA2)
#define REG_COMBO_PHY1_P0_51_H       (REG_COMBO_PHY1_P0_BASE + 0xA3)
#define REG_COMBO_PHY1_P0_52_L       (REG_COMBO_PHY1_P0_BASE + 0xA4)
#define REG_COMBO_PHY1_P0_52_H       (REG_COMBO_PHY1_P0_BASE + 0xA5)
#define REG_COMBO_PHY1_P0_53_L       (REG_COMBO_PHY1_P0_BASE + 0xA6)
#define REG_COMBO_PHY1_P0_53_H       (REG_COMBO_PHY1_P0_BASE + 0xA7)
#define REG_COMBO_PHY1_P0_54_L       (REG_COMBO_PHY1_P0_BASE + 0xA8)
#define REG_COMBO_PHY1_P0_54_H       (REG_COMBO_PHY1_P0_BASE + 0xA9)
#define REG_COMBO_PHY1_P0_55_L       (REG_COMBO_PHY1_P0_BASE + 0xAA)
#define REG_COMBO_PHY1_P0_55_H       (REG_COMBO_PHY1_P0_BASE + 0xAB)
#define REG_COMBO_PHY1_P0_56_L       (REG_COMBO_PHY1_P0_BASE + 0xAC)
#define REG_COMBO_PHY1_P0_56_H       (REG_COMBO_PHY1_P0_BASE + 0xAD)
#define REG_COMBO_PHY1_P0_57_L       (REG_COMBO_PHY1_P0_BASE + 0xAE)
#define REG_COMBO_PHY1_P0_57_H       (REG_COMBO_PHY1_P0_BASE + 0xAF)
#define REG_COMBO_PHY1_P0_58_L       (REG_COMBO_PHY1_P0_BASE + 0xB0)
#define REG_COMBO_PHY1_P0_58_H       (REG_COMBO_PHY1_P0_BASE + 0xB1)
#define REG_COMBO_PHY1_P0_59_L       (REG_COMBO_PHY1_P0_BASE + 0xB2)
#define REG_COMBO_PHY1_P0_59_H       (REG_COMBO_PHY1_P0_BASE + 0xB3)
#define REG_COMBO_PHY1_P0_5A_L       (REG_COMBO_PHY1_P0_BASE + 0xB4)
#define REG_COMBO_PHY1_P0_5A_H       (REG_COMBO_PHY1_P0_BASE + 0xB5)
#define REG_COMBO_PHY1_P0_5B_L       (REG_COMBO_PHY1_P0_BASE + 0xB6)
#define REG_COMBO_PHY1_P0_5B_H       (REG_COMBO_PHY1_P0_BASE + 0xB7)
#define REG_COMBO_PHY1_P0_5C_L       (REG_COMBO_PHY1_P0_BASE + 0xB8)
#define REG_COMBO_PHY1_P0_5C_H       (REG_COMBO_PHY1_P0_BASE + 0xB9)
#define REG_COMBO_PHY1_P0_5D_L       (REG_COMBO_PHY1_P0_BASE + 0xBA)
#define REG_COMBO_PHY1_P0_5D_H       (REG_COMBO_PHY1_P0_BASE + 0xBB)
#define REG_COMBO_PHY1_P0_5E_L       (REG_COMBO_PHY1_P0_BASE + 0xBC)
#define REG_COMBO_PHY1_P0_5E_H       (REG_COMBO_PHY1_P0_BASE + 0xBD)
#define REG_COMBO_PHY1_P0_5F_L       (REG_COMBO_PHY1_P0_BASE + 0xBE)
#define REG_COMBO_PHY1_P0_5F_H       (REG_COMBO_PHY1_P0_BASE + 0xBF)
#define REG_COMBO_PHY1_P0_60_L       (REG_COMBO_PHY1_P0_BASE + 0xC0)
#define REG_COMBO_PHY1_P0_60_H       (REG_COMBO_PHY1_P0_BASE + 0xC1)
#define REG_COMBO_PHY1_P0_61_L       (REG_COMBO_PHY1_P0_BASE + 0xC2)
#define REG_COMBO_PHY1_P0_61_H       (REG_COMBO_PHY1_P0_BASE + 0xC3)
#define REG_COMBO_PHY1_P0_62_L       (REG_COMBO_PHY1_P0_BASE + 0xC4)
#define REG_COMBO_PHY1_P0_62_H       (REG_COMBO_PHY1_P0_BASE + 0xC5)
#define REG_COMBO_PHY1_P0_63_L       (REG_COMBO_PHY1_P0_BASE + 0xC6)
#define REG_COMBO_PHY1_P0_63_H       (REG_COMBO_PHY1_P0_BASE + 0xC7)
#define REG_COMBO_PHY1_P0_64_L       (REG_COMBO_PHY1_P0_BASE + 0xC8)
#define REG_COMBO_PHY1_P0_64_H       (REG_COMBO_PHY1_P0_BASE + 0xC9)
#define REG_COMBO_PHY1_P0_65_L       (REG_COMBO_PHY1_P0_BASE + 0xCA)
#define REG_COMBO_PHY1_P0_65_H       (REG_COMBO_PHY1_P0_BASE + 0xCB)
#define REG_COMBO_PHY1_P0_66_L       (REG_COMBO_PHY1_P0_BASE + 0xCC)
#define REG_COMBO_PHY1_P0_66_H       (REG_COMBO_PHY1_P0_BASE + 0xCD)
#define REG_COMBO_PHY1_P0_67_L       (REG_COMBO_PHY1_P0_BASE + 0xCE)
#define REG_COMBO_PHY1_P0_67_H       (REG_COMBO_PHY1_P0_BASE + 0xCF)
#define REG_COMBO_PHY1_P0_68_L       (REG_COMBO_PHY1_P0_BASE + 0xD0)
#define REG_COMBO_PHY1_P0_68_H       (REG_COMBO_PHY1_P0_BASE + 0xD1)
#define REG_COMBO_PHY1_P0_69_L       (REG_COMBO_PHY1_P0_BASE + 0xD2)
#define REG_COMBO_PHY1_P0_69_H       (REG_COMBO_PHY1_P0_BASE + 0xD3)
#define REG_COMBO_PHY1_P0_6A_L       (REG_COMBO_PHY1_P0_BASE + 0xD4)
#define REG_COMBO_PHY1_P0_6A_H       (REG_COMBO_PHY1_P0_BASE + 0xD5)
#define REG_COMBO_PHY1_P0_6B_L       (REG_COMBO_PHY1_P0_BASE + 0xD6)
#define REG_COMBO_PHY1_P0_6B_H       (REG_COMBO_PHY1_P0_BASE + 0xD7)
#define REG_COMBO_PHY1_P0_6C_L       (REG_COMBO_PHY1_P0_BASE + 0xD8)
#define REG_COMBO_PHY1_P0_6C_H       (REG_COMBO_PHY1_P0_BASE + 0xD9)
#define REG_COMBO_PHY1_P0_6D_L       (REG_COMBO_PHY1_P0_BASE + 0xDA)
#define REG_COMBO_PHY1_P0_6D_H       (REG_COMBO_PHY1_P0_BASE + 0xDB)
#define REG_COMBO_PHY1_P0_6E_L       (REG_COMBO_PHY1_P0_BASE + 0xDC)
#define REG_COMBO_PHY1_P0_6E_H       (REG_COMBO_PHY1_P0_BASE + 0xDD)
#define REG_COMBO_PHY1_P0_6F_L       (REG_COMBO_PHY1_P0_BASE + 0xDE)
#define REG_COMBO_PHY1_P0_6F_H       (REG_COMBO_PHY1_P0_BASE + 0xDF)
#define REG_COMBO_PHY1_P0_70_L       (REG_COMBO_PHY1_P0_BASE + 0xE0)
#define REG_COMBO_PHY1_P0_70_H       (REG_COMBO_PHY1_P0_BASE + 0xE1)
#define REG_COMBO_PHY1_P0_71_L       (REG_COMBO_PHY1_P0_BASE + 0xE2)
#define REG_COMBO_PHY1_P0_71_H       (REG_COMBO_PHY1_P0_BASE + 0xE3)
#define REG_COMBO_PHY1_P0_72_L       (REG_COMBO_PHY1_P0_BASE + 0xE4)
#define REG_COMBO_PHY1_P0_72_H       (REG_COMBO_PHY1_P0_BASE + 0xE5)
#define REG_COMBO_PHY1_P0_73_L       (REG_COMBO_PHY1_P0_BASE + 0xE6)
#define REG_COMBO_PHY1_P0_73_H       (REG_COMBO_PHY1_P0_BASE + 0xE7)
#define REG_COMBO_PHY1_P0_74_L       (REG_COMBO_PHY1_P0_BASE + 0xE8)
#define REG_COMBO_PHY1_P0_74_H       (REG_COMBO_PHY1_P0_BASE + 0xE9)
#define REG_COMBO_PHY1_P0_75_L       (REG_COMBO_PHY1_P0_BASE + 0xEA)
#define REG_COMBO_PHY1_P0_75_H       (REG_COMBO_PHY1_P0_BASE + 0xEB)
#define REG_COMBO_PHY1_P0_76_L       (REG_COMBO_PHY1_P0_BASE + 0xEC)
#define REG_COMBO_PHY1_P0_76_H       (REG_COMBO_PHY1_P0_BASE + 0xED)
#define REG_COMBO_PHY1_P0_77_L       (REG_COMBO_PHY1_P0_BASE + 0xEE)
#define REG_COMBO_PHY1_P0_77_H       (REG_COMBO_PHY1_P0_BASE + 0xEF)
#define REG_COMBO_PHY1_P0_78_L       (REG_COMBO_PHY1_P0_BASE + 0xF0)
#define REG_COMBO_PHY1_P0_78_H       (REG_COMBO_PHY1_P0_BASE + 0xF1)
#define REG_COMBO_PHY1_P0_79_L       (REG_COMBO_PHY1_P0_BASE + 0xF2)
#define REG_COMBO_PHY1_P0_79_H       (REG_COMBO_PHY1_P0_BASE + 0xF3)
#define REG_COMBO_PHY1_P0_7A_L       (REG_COMBO_PHY1_P0_BASE + 0xF4)
#define REG_COMBO_PHY1_P0_7A_H       (REG_COMBO_PHY1_P0_BASE + 0xF5)
#define REG_COMBO_PHY1_P0_7B_L       (REG_COMBO_PHY1_P0_BASE + 0xF6)
#define REG_COMBO_PHY1_P0_7B_H       (REG_COMBO_PHY1_P0_BASE + 0xF7)
#define REG_COMBO_PHY1_P0_7C_L       (REG_COMBO_PHY1_P0_BASE + 0xF8)
#define REG_COMBO_PHY1_P0_7C_H       (REG_COMBO_PHY1_P0_BASE + 0xF9)
#define REG_COMBO_PHY1_P0_7D_L       (REG_COMBO_PHY1_P0_BASE + 0xFA)
#define REG_COMBO_PHY1_P0_7D_H       (REG_COMBO_PHY1_P0_BASE + 0xFB)
#define REG_COMBO_PHY1_P0_7E_L       (REG_COMBO_PHY1_P0_BASE + 0xFC)
#define REG_COMBO_PHY1_P0_7E_H       (REG_COMBO_PHY1_P0_BASE + 0xFD)
#define REG_COMBO_PHY1_P0_7F_L       (REG_COMBO_PHY1_P0_BASE + 0xFE)
#define REG_COMBO_PHY1_P0_7F_H       (REG_COMBO_PHY1_P0_BASE + 0xFF)

// COMBO_PHY0_P1
#define REG_COMBO_PHY0_P1_00_L       (REG_COMBO_PHY0_P1_BASE + 0x00)
#define REG_COMBO_PHY0_P1_00_H       (REG_COMBO_PHY0_P1_BASE + 0x01)
#define REG_COMBO_PHY0_P1_01_L       (REG_COMBO_PHY0_P1_BASE + 0x02)
#define REG_COMBO_PHY0_P1_01_H       (REG_COMBO_PHY0_P1_BASE + 0x03)
#define REG_COMBO_PHY0_P1_02_L       (REG_COMBO_PHY0_P1_BASE + 0x04)
#define REG_COMBO_PHY0_P1_02_H       (REG_COMBO_PHY0_P1_BASE + 0x05)
#define REG_COMBO_PHY0_P1_03_L       (REG_COMBO_PHY0_P1_BASE + 0x06)
#define REG_COMBO_PHY0_P1_03_H       (REG_COMBO_PHY0_P1_BASE + 0x07)
#define REG_COMBO_PHY0_P1_04_L       (REG_COMBO_PHY0_P1_BASE + 0x08)
#define REG_COMBO_PHY0_P1_04_H       (REG_COMBO_PHY0_P1_BASE + 0x09)
#define REG_COMBO_PHY0_P1_05_L       (REG_COMBO_PHY0_P1_BASE + 0x0A)
#define REG_COMBO_PHY0_P1_05_H       (REG_COMBO_PHY0_P1_BASE + 0x0B)
#define REG_COMBO_PHY0_P1_06_L       (REG_COMBO_PHY0_P1_BASE + 0x0C)
#define REG_COMBO_PHY0_P1_06_H       (REG_COMBO_PHY0_P1_BASE + 0x0D)
#define REG_COMBO_PHY0_P1_07_L       (REG_COMBO_PHY0_P1_BASE + 0x0E)
#define REG_COMBO_PHY0_P1_07_H       (REG_COMBO_PHY0_P1_BASE + 0x0F)
#define REG_COMBO_PHY0_P1_08_L       (REG_COMBO_PHY0_P1_BASE + 0x10)
#define REG_COMBO_PHY0_P1_08_H       (REG_COMBO_PHY0_P1_BASE + 0x11)
#define REG_COMBO_PHY0_P1_09_L       (REG_COMBO_PHY0_P1_BASE + 0x12)
#define REG_COMBO_PHY0_P1_09_H       (REG_COMBO_PHY0_P1_BASE + 0x13)
#define REG_COMBO_PHY0_P1_0A_L       (REG_COMBO_PHY0_P1_BASE + 0x14)
#define REG_COMBO_PHY0_P1_0A_H       (REG_COMBO_PHY0_P1_BASE + 0x15)
#define REG_COMBO_PHY0_P1_0B_L       (REG_COMBO_PHY0_P1_BASE + 0x16)
#define REG_COMBO_PHY0_P1_0B_H       (REG_COMBO_PHY0_P1_BASE + 0x17)
#define REG_COMBO_PHY0_P1_0C_L       (REG_COMBO_PHY0_P1_BASE + 0x18)
#define REG_COMBO_PHY0_P1_0C_H       (REG_COMBO_PHY0_P1_BASE + 0x19)
#define REG_COMBO_PHY0_P1_0D_L       (REG_COMBO_PHY0_P1_BASE + 0x1A)
#define REG_COMBO_PHY0_P1_0D_H       (REG_COMBO_PHY0_P1_BASE + 0x1B)
#define REG_COMBO_PHY0_P1_0E_L       (REG_COMBO_PHY0_P1_BASE + 0x1C)
#define REG_COMBO_PHY0_P1_0E_H       (REG_COMBO_PHY0_P1_BASE + 0x1D)
#define REG_COMBO_PHY0_P1_0F_L       (REG_COMBO_PHY0_P1_BASE + 0x1E)
#define REG_COMBO_PHY0_P1_0F_H       (REG_COMBO_PHY0_P1_BASE + 0x1F)
#define REG_COMBO_PHY0_P1_10_L       (REG_COMBO_PHY0_P1_BASE + 0x20)
#define REG_COMBO_PHY0_P1_10_H       (REG_COMBO_PHY0_P1_BASE + 0x21)
#define REG_COMBO_PHY0_P1_11_L       (REG_COMBO_PHY0_P1_BASE + 0x22)
#define REG_COMBO_PHY0_P1_11_H       (REG_COMBO_PHY0_P1_BASE + 0x23)
#define REG_COMBO_PHY0_P1_12_L       (REG_COMBO_PHY0_P1_BASE + 0x24)
#define REG_COMBO_PHY0_P1_12_H       (REG_COMBO_PHY0_P1_BASE + 0x25)
#define REG_COMBO_PHY0_P1_13_L       (REG_COMBO_PHY0_P1_BASE + 0x26)
#define REG_COMBO_PHY0_P1_13_H       (REG_COMBO_PHY0_P1_BASE + 0x27)
#define REG_COMBO_PHY0_P1_14_L       (REG_COMBO_PHY0_P1_BASE + 0x28)
#define REG_COMBO_PHY0_P1_14_H       (REG_COMBO_PHY0_P1_BASE + 0x29)
#define REG_COMBO_PHY0_P1_15_L       (REG_COMBO_PHY0_P1_BASE + 0x2A)
#define REG_COMBO_PHY0_P1_15_H       (REG_COMBO_PHY0_P1_BASE + 0x2B)
#define REG_COMBO_PHY0_P1_16_L       (REG_COMBO_PHY0_P1_BASE + 0x2C)
#define REG_COMBO_PHY0_P1_16_H       (REG_COMBO_PHY0_P1_BASE + 0x2D)
#define REG_COMBO_PHY0_P1_17_L       (REG_COMBO_PHY0_P1_BASE + 0x2E)
#define REG_COMBO_PHY0_P1_17_H       (REG_COMBO_PHY0_P1_BASE + 0x2F)
#define REG_COMBO_PHY0_P1_18_L       (REG_COMBO_PHY0_P1_BASE + 0x30)
#define REG_COMBO_PHY0_P1_18_H       (REG_COMBO_PHY0_P1_BASE + 0x31)
#define REG_COMBO_PHY0_P1_19_L       (REG_COMBO_PHY0_P1_BASE + 0x32)
#define REG_COMBO_PHY0_P1_19_H       (REG_COMBO_PHY0_P1_BASE + 0x33)
#define REG_COMBO_PHY0_P1_1A_L       (REG_COMBO_PHY0_P1_BASE + 0x34)
#define REG_COMBO_PHY0_P1_1A_H       (REG_COMBO_PHY0_P1_BASE + 0x35)
#define REG_COMBO_PHY0_P1_1B_L       (REG_COMBO_PHY0_P1_BASE + 0x36)
#define REG_COMBO_PHY0_P1_1B_H       (REG_COMBO_PHY0_P1_BASE + 0x37)
#define REG_COMBO_PHY0_P1_1C_L       (REG_COMBO_PHY0_P1_BASE + 0x38)
#define REG_COMBO_PHY0_P1_1C_H       (REG_COMBO_PHY0_P1_BASE + 0x39)
#define REG_COMBO_PHY0_P1_1D_L       (REG_COMBO_PHY0_P1_BASE + 0x3A)
#define REG_COMBO_PHY0_P1_1D_H       (REG_COMBO_PHY0_P1_BASE + 0x3B)
#define REG_COMBO_PHY0_P1_1E_L       (REG_COMBO_PHY0_P1_BASE + 0x3C)
#define REG_COMBO_PHY0_P1_1E_H       (REG_COMBO_PHY0_P1_BASE + 0x3D)
#define REG_COMBO_PHY0_P1_1F_L       (REG_COMBO_PHY0_P1_BASE + 0x3E)
#define REG_COMBO_PHY0_P1_1F_H       (REG_COMBO_PHY0_P1_BASE + 0x3F)
#define REG_COMBO_PHY0_P1_20_L       (REG_COMBO_PHY0_P1_BASE + 0x40)
#define REG_COMBO_PHY0_P1_20_H       (REG_COMBO_PHY0_P1_BASE + 0x41)
#define REG_COMBO_PHY0_P1_21_L       (REG_COMBO_PHY0_P1_BASE + 0x42)
#define REG_COMBO_PHY0_P1_21_H       (REG_COMBO_PHY0_P1_BASE + 0x43)
#define REG_COMBO_PHY0_P1_22_L       (REG_COMBO_PHY0_P1_BASE + 0x44)
#define REG_COMBO_PHY0_P1_22_H       (REG_COMBO_PHY0_P1_BASE + 0x45)
#define REG_COMBO_PHY0_P1_23_L       (REG_COMBO_PHY0_P1_BASE + 0x46)
#define REG_COMBO_PHY0_P1_23_H       (REG_COMBO_PHY0_P1_BASE + 0x47)
#define REG_COMBO_PHY0_P1_24_L       (REG_COMBO_PHY0_P1_BASE + 0x48)
#define REG_COMBO_PHY0_P1_24_H       (REG_COMBO_PHY0_P1_BASE + 0x49)
#define REG_COMBO_PHY0_P1_25_L       (REG_COMBO_PHY0_P1_BASE + 0x4A)
#define REG_COMBO_PHY0_P1_25_H       (REG_COMBO_PHY0_P1_BASE + 0x4B)
#define REG_COMBO_PHY0_P1_26_L       (REG_COMBO_PHY0_P1_BASE + 0x4C)
#define REG_COMBO_PHY0_P1_26_H       (REG_COMBO_PHY0_P1_BASE + 0x4D)
#define REG_COMBO_PHY0_P1_27_L       (REG_COMBO_PHY0_P1_BASE + 0x4E)
#define REG_COMBO_PHY0_P1_27_H       (REG_COMBO_PHY0_P1_BASE + 0x4F)
#define REG_COMBO_PHY0_P1_28_L       (REG_COMBO_PHY0_P1_BASE + 0x50)
#define REG_COMBO_PHY0_P1_28_H       (REG_COMBO_PHY0_P1_BASE + 0x51)
#define REG_COMBO_PHY0_P1_29_L       (REG_COMBO_PHY0_P1_BASE + 0x52)
#define REG_COMBO_PHY0_P1_29_H       (REG_COMBO_PHY0_P1_BASE + 0x53)
#define REG_COMBO_PHY0_P1_2A_L       (REG_COMBO_PHY0_P1_BASE + 0x54)
#define REG_COMBO_PHY0_P1_2A_H       (REG_COMBO_PHY0_P1_BASE + 0x55)
#define REG_COMBO_PHY0_P1_2B_L       (REG_COMBO_PHY0_P1_BASE + 0x56)
#define REG_COMBO_PHY0_P1_2B_H       (REG_COMBO_PHY0_P1_BASE + 0x57)
#define REG_COMBO_PHY0_P1_2C_L       (REG_COMBO_PHY0_P1_BASE + 0x58)
#define REG_COMBO_PHY0_P1_2C_H       (REG_COMBO_PHY0_P1_BASE + 0x59)
#define REG_COMBO_PHY0_P1_2D_L       (REG_COMBO_PHY0_P1_BASE + 0x5A)
#define REG_COMBO_PHY0_P1_2D_H       (REG_COMBO_PHY0_P1_BASE + 0x5B)
#define REG_COMBO_PHY0_P1_2E_L       (REG_COMBO_PHY0_P1_BASE + 0x5C)
#define REG_COMBO_PHY0_P1_2E_H       (REG_COMBO_PHY0_P1_BASE + 0x5D)
#define REG_COMBO_PHY0_P1_2F_L       (REG_COMBO_PHY0_P1_BASE + 0x5E)
#define REG_COMBO_PHY0_P1_2F_H       (REG_COMBO_PHY0_P1_BASE + 0x5F)
#define REG_COMBO_PHY0_P1_30_L       (REG_COMBO_PHY0_P1_BASE + 0x60)
#define REG_COMBO_PHY0_P1_30_H       (REG_COMBO_PHY0_P1_BASE + 0x61)
#define REG_COMBO_PHY0_P1_31_L       (REG_COMBO_PHY0_P1_BASE + 0x62)
#define REG_COMBO_PHY0_P1_31_H       (REG_COMBO_PHY0_P1_BASE + 0x63)
#define REG_COMBO_PHY0_P1_32_L       (REG_COMBO_PHY0_P1_BASE + 0x64)
#define REG_COMBO_PHY0_P1_32_H       (REG_COMBO_PHY0_P1_BASE + 0x65)
#define REG_COMBO_PHY0_P1_33_L       (REG_COMBO_PHY0_P1_BASE + 0x66)
#define REG_COMBO_PHY0_P1_33_H       (REG_COMBO_PHY0_P1_BASE + 0x67)
#define REG_COMBO_PHY0_P1_34_L       (REG_COMBO_PHY0_P1_BASE + 0x68)
#define REG_COMBO_PHY0_P1_34_H       (REG_COMBO_PHY0_P1_BASE + 0x69)
#define REG_COMBO_PHY0_P1_35_L       (REG_COMBO_PHY0_P1_BASE + 0x6A)
#define REG_COMBO_PHY0_P1_35_H       (REG_COMBO_PHY0_P1_BASE + 0x6B)
#define REG_COMBO_PHY0_P1_36_L       (REG_COMBO_PHY0_P1_BASE + 0x6C)
#define REG_COMBO_PHY0_P1_36_H       (REG_COMBO_PHY0_P1_BASE + 0x6D)
#define REG_COMBO_PHY0_P1_37_L       (REG_COMBO_PHY0_P1_BASE + 0x6E)
#define REG_COMBO_PHY0_P1_37_H       (REG_COMBO_PHY0_P1_BASE + 0x6F)
#define REG_COMBO_PHY0_P1_38_L       (REG_COMBO_PHY0_P1_BASE + 0x70)
#define REG_COMBO_PHY0_P1_38_H       (REG_COMBO_PHY0_P1_BASE + 0x71)
#define REG_COMBO_PHY0_P1_39_L       (REG_COMBO_PHY0_P1_BASE + 0x72)
#define REG_COMBO_PHY0_P1_39_H       (REG_COMBO_PHY0_P1_BASE + 0x73)
#define REG_COMBO_PHY0_P1_3A_L       (REG_COMBO_PHY0_P1_BASE + 0x74)
#define REG_COMBO_PHY0_P1_3A_H       (REG_COMBO_PHY0_P1_BASE + 0x75)
#define REG_COMBO_PHY0_P1_3B_L       (REG_COMBO_PHY0_P1_BASE + 0x76)
#define REG_COMBO_PHY0_P1_3B_H       (REG_COMBO_PHY0_P1_BASE + 0x77)
#define REG_COMBO_PHY0_P1_3C_L       (REG_COMBO_PHY0_P1_BASE + 0x78)
#define REG_COMBO_PHY0_P1_3C_H       (REG_COMBO_PHY0_P1_BASE + 0x79)
#define REG_COMBO_PHY0_P1_3D_L       (REG_COMBO_PHY0_P1_BASE + 0x7A)
#define REG_COMBO_PHY0_P1_3D_H       (REG_COMBO_PHY0_P1_BASE + 0x7B)
#define REG_COMBO_PHY0_P1_3E_L       (REG_COMBO_PHY0_P1_BASE + 0x7C)
#define REG_COMBO_PHY0_P1_3E_H       (REG_COMBO_PHY0_P1_BASE + 0x7D)
#define REG_COMBO_PHY0_P1_3F_L       (REG_COMBO_PHY0_P1_BASE + 0x7E)
#define REG_COMBO_PHY0_P1_3F_H       (REG_COMBO_PHY0_P1_BASE + 0x7F)
#define REG_COMBO_PHY0_P1_40_L       (REG_COMBO_PHY0_P1_BASE + 0x80)
#define REG_COMBO_PHY0_P1_40_H       (REG_COMBO_PHY0_P1_BASE + 0x81)
#define REG_COMBO_PHY0_P1_41_L       (REG_COMBO_PHY0_P1_BASE + 0x82)
#define REG_COMBO_PHY0_P1_41_H       (REG_COMBO_PHY0_P1_BASE + 0x83)
#define REG_COMBO_PHY0_P1_42_L       (REG_COMBO_PHY0_P1_BASE + 0x84)
#define REG_COMBO_PHY0_P1_42_H       (REG_COMBO_PHY0_P1_BASE + 0x85)
#define REG_COMBO_PHY0_P1_43_L       (REG_COMBO_PHY0_P1_BASE + 0x86)
#define REG_COMBO_PHY0_P1_43_H       (REG_COMBO_PHY0_P1_BASE + 0x87)
#define REG_COMBO_PHY0_P1_44_L       (REG_COMBO_PHY0_P1_BASE + 0x88)
#define REG_COMBO_PHY0_P1_44_H       (REG_COMBO_PHY0_P1_BASE + 0x89)
#define REG_COMBO_PHY0_P1_45_L       (REG_COMBO_PHY0_P1_BASE + 0x8A)
#define REG_COMBO_PHY0_P1_45_H       (REG_COMBO_PHY0_P1_BASE + 0x8B)
#define REG_COMBO_PHY0_P1_46_L       (REG_COMBO_PHY0_P1_BASE + 0x8C)
#define REG_COMBO_PHY0_P1_46_H       (REG_COMBO_PHY0_P1_BASE + 0x8D)
#define REG_COMBO_PHY0_P1_47_L       (REG_COMBO_PHY0_P1_BASE + 0x8E)
#define REG_COMBO_PHY0_P1_47_H       (REG_COMBO_PHY0_P1_BASE + 0x8F)
#define REG_COMBO_PHY0_P1_48_L       (REG_COMBO_PHY0_P1_BASE + 0x90)
#define REG_COMBO_PHY0_P1_48_H       (REG_COMBO_PHY0_P1_BASE + 0x91)
#define REG_COMBO_PHY0_P1_49_L       (REG_COMBO_PHY0_P1_BASE + 0x92)
#define REG_COMBO_PHY0_P1_49_H       (REG_COMBO_PHY0_P1_BASE + 0x93)
#define REG_COMBO_PHY0_P1_4A_L       (REG_COMBO_PHY0_P1_BASE + 0x94)
#define REG_COMBO_PHY0_P1_4A_H       (REG_COMBO_PHY0_P1_BASE + 0x95)
#define REG_COMBO_PHY0_P1_4B_L       (REG_COMBO_PHY0_P1_BASE + 0x96)
#define REG_COMBO_PHY0_P1_4B_H       (REG_COMBO_PHY0_P1_BASE + 0x97)
#define REG_COMBO_PHY0_P1_4C_L       (REG_COMBO_PHY0_P1_BASE + 0x98)
#define REG_COMBO_PHY0_P1_4C_H       (REG_COMBO_PHY0_P1_BASE + 0x99)
#define REG_COMBO_PHY0_P1_4D_L       (REG_COMBO_PHY0_P1_BASE + 0x9A)
#define REG_COMBO_PHY0_P1_4D_H       (REG_COMBO_PHY0_P1_BASE + 0x9B)
#define REG_COMBO_PHY0_P1_4E_L       (REG_COMBO_PHY0_P1_BASE + 0x9C)
#define REG_COMBO_PHY0_P1_4E_H       (REG_COMBO_PHY0_P1_BASE + 0x9D)
#define REG_COMBO_PHY0_P1_4F_L       (REG_COMBO_PHY0_P1_BASE + 0x9E)
#define REG_COMBO_PHY0_P1_4F_H       (REG_COMBO_PHY0_P1_BASE + 0x9F)
#define REG_COMBO_PHY0_P1_50_L       (REG_COMBO_PHY0_P1_BASE + 0xA0)
#define REG_COMBO_PHY0_P1_50_H       (REG_COMBO_PHY0_P1_BASE + 0xA1)
#define REG_COMBO_PHY0_P1_51_L       (REG_COMBO_PHY0_P1_BASE + 0xA2)
#define REG_COMBO_PHY0_P1_51_H       (REG_COMBO_PHY0_P1_BASE + 0xA3)
#define REG_COMBO_PHY0_P1_52_L       (REG_COMBO_PHY0_P1_BASE + 0xA4)
#define REG_COMBO_PHY0_P1_52_H       (REG_COMBO_PHY0_P1_BASE + 0xA5)
#define REG_COMBO_PHY0_P1_53_L       (REG_COMBO_PHY0_P1_BASE + 0xA6)
#define REG_COMBO_PHY0_P1_53_H       (REG_COMBO_PHY0_P1_BASE + 0xA7)
#define REG_COMBO_PHY0_P1_54_L       (REG_COMBO_PHY0_P1_BASE + 0xA8)
#define REG_COMBO_PHY0_P1_54_H       (REG_COMBO_PHY0_P1_BASE + 0xA9)
#define REG_COMBO_PHY0_P1_55_L       (REG_COMBO_PHY0_P1_BASE + 0xAA)
#define REG_COMBO_PHY0_P1_55_H       (REG_COMBO_PHY0_P1_BASE + 0xAB)
#define REG_COMBO_PHY0_P1_56_L       (REG_COMBO_PHY0_P1_BASE + 0xAC)
#define REG_COMBO_PHY0_P1_56_H       (REG_COMBO_PHY0_P1_BASE + 0xAD)
#define REG_COMBO_PHY0_P1_57_L       (REG_COMBO_PHY0_P1_BASE + 0xAE)
#define REG_COMBO_PHY0_P1_57_H       (REG_COMBO_PHY0_P1_BASE + 0xAF)
#define REG_COMBO_PHY0_P1_58_L       (REG_COMBO_PHY0_P1_BASE + 0xB0)
#define REG_COMBO_PHY0_P1_58_H       (REG_COMBO_PHY0_P1_BASE + 0xB1)
#define REG_COMBO_PHY0_P1_59_L       (REG_COMBO_PHY0_P1_BASE + 0xB2)
#define REG_COMBO_PHY0_P1_59_H       (REG_COMBO_PHY0_P1_BASE + 0xB3)
#define REG_COMBO_PHY0_P1_5A_L       (REG_COMBO_PHY0_P1_BASE + 0xB4)
#define REG_COMBO_PHY0_P1_5A_H       (REG_COMBO_PHY0_P1_BASE + 0xB5)
#define REG_COMBO_PHY0_P1_5B_L       (REG_COMBO_PHY0_P1_BASE + 0xB6)
#define REG_COMBO_PHY0_P1_5B_H       (REG_COMBO_PHY0_P1_BASE + 0xB7)
#define REG_COMBO_PHY0_P1_5C_L       (REG_COMBO_PHY0_P1_BASE + 0xB8)
#define REG_COMBO_PHY0_P1_5C_H       (REG_COMBO_PHY0_P1_BASE + 0xB9)
#define REG_COMBO_PHY0_P1_5D_L       (REG_COMBO_PHY0_P1_BASE + 0xBA)
#define REG_COMBO_PHY0_P1_5D_H       (REG_COMBO_PHY0_P1_BASE + 0xBB)
#define REG_COMBO_PHY0_P1_5E_L       (REG_COMBO_PHY0_P1_BASE + 0xBC)
#define REG_COMBO_PHY0_P1_5E_H       (REG_COMBO_PHY0_P1_BASE + 0xBD)
#define REG_COMBO_PHY0_P1_5F_L       (REG_COMBO_PHY0_P1_BASE + 0xBE)
#define REG_COMBO_PHY0_P1_5F_H       (REG_COMBO_PHY0_P1_BASE + 0xBF)
#define REG_COMBO_PHY0_P1_60_L       (REG_COMBO_PHY0_P1_BASE + 0xC0)
#define REG_COMBO_PHY0_P1_60_H       (REG_COMBO_PHY0_P1_BASE + 0xC1)
#define REG_COMBO_PHY0_P1_61_L       (REG_COMBO_PHY0_P1_BASE + 0xC2)
#define REG_COMBO_PHY0_P1_61_H       (REG_COMBO_PHY0_P1_BASE + 0xC3)
#define REG_COMBO_PHY0_P1_62_L       (REG_COMBO_PHY0_P1_BASE + 0xC4)
#define REG_COMBO_PHY0_P1_62_H       (REG_COMBO_PHY0_P1_BASE + 0xC5)
#define REG_COMBO_PHY0_P1_63_L       (REG_COMBO_PHY0_P1_BASE + 0xC6)
#define REG_COMBO_PHY0_P1_63_H       (REG_COMBO_PHY0_P1_BASE + 0xC7)
#define REG_COMBO_PHY0_P1_64_L       (REG_COMBO_PHY0_P1_BASE + 0xC8)
#define REG_COMBO_PHY0_P1_64_H       (REG_COMBO_PHY0_P1_BASE + 0xC9)
#define REG_COMBO_PHY0_P1_65_L       (REG_COMBO_PHY0_P1_BASE + 0xCA)
#define REG_COMBO_PHY0_P1_65_H       (REG_COMBO_PHY0_P1_BASE + 0xCB)
#define REG_COMBO_PHY0_P1_66_L       (REG_COMBO_PHY0_P1_BASE + 0xCC)
#define REG_COMBO_PHY0_P1_66_H       (REG_COMBO_PHY0_P1_BASE + 0xCD)
#define REG_COMBO_PHY0_P1_67_L       (REG_COMBO_PHY0_P1_BASE + 0xCE)
#define REG_COMBO_PHY0_P1_67_H       (REG_COMBO_PHY0_P1_BASE + 0xCF)
#define REG_COMBO_PHY0_P1_68_L       (REG_COMBO_PHY0_P1_BASE + 0xD0)
#define REG_COMBO_PHY0_P1_68_H       (REG_COMBO_PHY0_P1_BASE + 0xD1)
#define REG_COMBO_PHY0_P1_69_L       (REG_COMBO_PHY0_P1_BASE + 0xD2)
#define REG_COMBO_PHY0_P1_69_H       (REG_COMBO_PHY0_P1_BASE + 0xD3)
#define REG_COMBO_PHY0_P1_6A_L       (REG_COMBO_PHY0_P1_BASE + 0xD4)
#define REG_COMBO_PHY0_P1_6A_H       (REG_COMBO_PHY0_P1_BASE + 0xD5)
#define REG_COMBO_PHY0_P1_6B_L       (REG_COMBO_PHY0_P1_BASE + 0xD6)
#define REG_COMBO_PHY0_P1_6B_H       (REG_COMBO_PHY0_P1_BASE + 0xD7)
#define REG_COMBO_PHY0_P1_6C_L       (REG_COMBO_PHY0_P1_BASE + 0xD8)
#define REG_COMBO_PHY0_P1_6C_H       (REG_COMBO_PHY0_P1_BASE + 0xD9)
#define REG_COMBO_PHY0_P1_6D_L       (REG_COMBO_PHY0_P1_BASE + 0xDA)
#define REG_COMBO_PHY0_P1_6D_H       (REG_COMBO_PHY0_P1_BASE + 0xDB)
#define REG_COMBO_PHY0_P1_6E_L       (REG_COMBO_PHY0_P1_BASE + 0xDC)
#define REG_COMBO_PHY0_P1_6E_H       (REG_COMBO_PHY0_P1_BASE + 0xDD)
#define REG_COMBO_PHY0_P1_6F_L       (REG_COMBO_PHY0_P1_BASE + 0xDE)
#define REG_COMBO_PHY0_P1_6F_H       (REG_COMBO_PHY0_P1_BASE + 0xDF)
#define REG_COMBO_PHY0_P1_70_L       (REG_COMBO_PHY0_P1_BASE + 0xE0)
#define REG_COMBO_PHY0_P1_70_H       (REG_COMBO_PHY0_P1_BASE + 0xE1)
#define REG_COMBO_PHY0_P1_71_L       (REG_COMBO_PHY0_P1_BASE + 0xE2)
#define REG_COMBO_PHY0_P1_71_H       (REG_COMBO_PHY0_P1_BASE + 0xE3)
#define REG_COMBO_PHY0_P1_72_L       (REG_COMBO_PHY0_P1_BASE + 0xE4)
#define REG_COMBO_PHY0_P1_72_H       (REG_COMBO_PHY0_P1_BASE + 0xE5)
#define REG_COMBO_PHY0_P1_73_L       (REG_COMBO_PHY0_P1_BASE + 0xE6)
#define REG_COMBO_PHY0_P1_73_H       (REG_COMBO_PHY0_P1_BASE + 0xE7)
#define REG_COMBO_PHY0_P1_74_L       (REG_COMBO_PHY0_P1_BASE + 0xE8)
#define REG_COMBO_PHY0_P1_74_H       (REG_COMBO_PHY0_P1_BASE + 0xE9)
#define REG_COMBO_PHY0_P1_75_L       (REG_COMBO_PHY0_P1_BASE + 0xEA)
#define REG_COMBO_PHY0_P1_75_H       (REG_COMBO_PHY0_P1_BASE + 0xEB)
#define REG_COMBO_PHY0_P1_76_L       (REG_COMBO_PHY0_P1_BASE + 0xEC)
#define REG_COMBO_PHY0_P1_76_H       (REG_COMBO_PHY0_P1_BASE + 0xED)
#define REG_COMBO_PHY0_P1_77_L       (REG_COMBO_PHY0_P1_BASE + 0xEE)
#define REG_COMBO_PHY0_P1_77_H       (REG_COMBO_PHY0_P1_BASE + 0xEF)
#define REG_COMBO_PHY0_P1_78_L       (REG_COMBO_PHY0_P1_BASE + 0xF0)
#define REG_COMBO_PHY0_P1_78_H       (REG_COMBO_PHY0_P1_BASE + 0xF1)
#define REG_COMBO_PHY0_P1_79_L       (REG_COMBO_PHY0_P1_BASE + 0xF2)
#define REG_COMBO_PHY0_P1_79_H       (REG_COMBO_PHY0_P1_BASE + 0xF3)
#define REG_COMBO_PHY0_P1_7A_L       (REG_COMBO_PHY0_P1_BASE + 0xF4)
#define REG_COMBO_PHY0_P1_7A_H       (REG_COMBO_PHY0_P1_BASE + 0xF5)
#define REG_COMBO_PHY0_P1_7B_L       (REG_COMBO_PHY0_P1_BASE + 0xF6)
#define REG_COMBO_PHY0_P1_7B_H       (REG_COMBO_PHY0_P1_BASE + 0xF7)
#define REG_COMBO_PHY0_P1_7C_L       (REG_COMBO_PHY0_P1_BASE + 0xF8)
#define REG_COMBO_PHY0_P1_7C_H       (REG_COMBO_PHY0_P1_BASE + 0xF9)
#define REG_COMBO_PHY0_P1_7D_L       (REG_COMBO_PHY0_P1_BASE + 0xFA)
#define REG_COMBO_PHY0_P1_7D_H       (REG_COMBO_PHY0_P1_BASE + 0xFB)
#define REG_COMBO_PHY0_P1_7E_L       (REG_COMBO_PHY0_P1_BASE + 0xFC)
#define REG_COMBO_PHY0_P1_7E_H       (REG_COMBO_PHY0_P1_BASE + 0xFD)
#define REG_COMBO_PHY0_P1_7F_L       (REG_COMBO_PHY0_P1_BASE + 0xFE)
#define REG_COMBO_PHY0_P1_7F_H       (REG_COMBO_PHY0_P1_BASE + 0xFF)

// COMBO_PHY1_P1
#define REG_COMBO_PHY1_P1_00_L       (REG_COMBO_PHY1_P1_BASE + 0x00)
#define REG_COMBO_PHY1_P1_00_H       (REG_COMBO_PHY1_P1_BASE + 0x01)
#define REG_COMBO_PHY1_P1_01_L       (REG_COMBO_PHY1_P1_BASE + 0x02)
#define REG_COMBO_PHY1_P1_01_H       (REG_COMBO_PHY1_P1_BASE + 0x03)
#define REG_COMBO_PHY1_P1_02_L       (REG_COMBO_PHY1_P1_BASE + 0x04)
#define REG_COMBO_PHY1_P1_02_H       (REG_COMBO_PHY1_P1_BASE + 0x05)
#define REG_COMBO_PHY1_P1_03_L       (REG_COMBO_PHY1_P1_BASE + 0x06)
#define REG_COMBO_PHY1_P1_03_H       (REG_COMBO_PHY1_P1_BASE + 0x07)
#define REG_COMBO_PHY1_P1_04_L       (REG_COMBO_PHY1_P1_BASE + 0x08)
#define REG_COMBO_PHY1_P1_04_H       (REG_COMBO_PHY1_P1_BASE + 0x09)
#define REG_COMBO_PHY1_P1_05_L       (REG_COMBO_PHY1_P1_BASE + 0x0A)
#define REG_COMBO_PHY1_P1_05_H       (REG_COMBO_PHY1_P1_BASE + 0x0B)
#define REG_COMBO_PHY1_P1_06_L       (REG_COMBO_PHY1_P1_BASE + 0x0C)
#define REG_COMBO_PHY1_P1_06_H       (REG_COMBO_PHY1_P1_BASE + 0x0D)
#define REG_COMBO_PHY1_P1_07_L       (REG_COMBO_PHY1_P1_BASE + 0x0E)
#define REG_COMBO_PHY1_P1_07_H       (REG_COMBO_PHY1_P1_BASE + 0x0F)
#define REG_COMBO_PHY1_P1_08_L       (REG_COMBO_PHY1_P1_BASE + 0x10)
#define REG_COMBO_PHY1_P1_08_H       (REG_COMBO_PHY1_P1_BASE + 0x11)
#define REG_COMBO_PHY1_P1_09_L       (REG_COMBO_PHY1_P1_BASE + 0x12)
#define REG_COMBO_PHY1_P1_09_H       (REG_COMBO_PHY1_P1_BASE + 0x13)
#define REG_COMBO_PHY1_P1_0A_L       (REG_COMBO_PHY1_P1_BASE + 0x14)
#define REG_COMBO_PHY1_P1_0A_H       (REG_COMBO_PHY1_P1_BASE + 0x15)
#define REG_COMBO_PHY1_P1_0B_L       (REG_COMBO_PHY1_P1_BASE + 0x16)
#define REG_COMBO_PHY1_P1_0B_H       (REG_COMBO_PHY1_P1_BASE + 0x17)
#define REG_COMBO_PHY1_P1_0C_L       (REG_COMBO_PHY1_P1_BASE + 0x18)
#define REG_COMBO_PHY1_P1_0C_H       (REG_COMBO_PHY1_P1_BASE + 0x19)
#define REG_COMBO_PHY1_P1_0D_L       (REG_COMBO_PHY1_P1_BASE + 0x1A)
#define REG_COMBO_PHY1_P1_0D_H       (REG_COMBO_PHY1_P1_BASE + 0x1B)
#define REG_COMBO_PHY1_P1_0E_L       (REG_COMBO_PHY1_P1_BASE + 0x1C)
#define REG_COMBO_PHY1_P1_0E_H       (REG_COMBO_PHY1_P1_BASE + 0x1D)
#define REG_COMBO_PHY1_P1_0F_L       (REG_COMBO_PHY1_P1_BASE + 0x1E)
#define REG_COMBO_PHY1_P1_0F_H       (REG_COMBO_PHY1_P1_BASE + 0x1F)
#define REG_COMBO_PHY1_P1_10_L       (REG_COMBO_PHY1_P1_BASE + 0x20)
#define REG_COMBO_PHY1_P1_10_H       (REG_COMBO_PHY1_P1_BASE + 0x21)
#define REG_COMBO_PHY1_P1_11_L       (REG_COMBO_PHY1_P1_BASE + 0x22)
#define REG_COMBO_PHY1_P1_11_H       (REG_COMBO_PHY1_P1_BASE + 0x23)
#define REG_COMBO_PHY1_P1_12_L       (REG_COMBO_PHY1_P1_BASE + 0x24)
#define REG_COMBO_PHY1_P1_12_H       (REG_COMBO_PHY1_P1_BASE + 0x25)
#define REG_COMBO_PHY1_P1_13_L       (REG_COMBO_PHY1_P1_BASE + 0x26)
#define REG_COMBO_PHY1_P1_13_H       (REG_COMBO_PHY1_P1_BASE + 0x27)
#define REG_COMBO_PHY1_P1_14_L       (REG_COMBO_PHY1_P1_BASE + 0x28)
#define REG_COMBO_PHY1_P1_14_H       (REG_COMBO_PHY1_P1_BASE + 0x29)
#define REG_COMBO_PHY1_P1_15_L       (REG_COMBO_PHY1_P1_BASE + 0x2A)
#define REG_COMBO_PHY1_P1_15_H       (REG_COMBO_PHY1_P1_BASE + 0x2B)
#define REG_COMBO_PHY1_P1_16_L       (REG_COMBO_PHY1_P1_BASE + 0x2C)
#define REG_COMBO_PHY1_P1_16_H       (REG_COMBO_PHY1_P1_BASE + 0x2D)
#define REG_COMBO_PHY1_P1_17_L       (REG_COMBO_PHY1_P1_BASE + 0x2E)
#define REG_COMBO_PHY1_P1_17_H       (REG_COMBO_PHY1_P1_BASE + 0x2F)
#define REG_COMBO_PHY1_P1_18_L       (REG_COMBO_PHY1_P1_BASE + 0x30)
#define REG_COMBO_PHY1_P1_18_H       (REG_COMBO_PHY1_P1_BASE + 0x31)
#define REG_COMBO_PHY1_P1_19_L       (REG_COMBO_PHY1_P1_BASE + 0x32)
#define REG_COMBO_PHY1_P1_19_H       (REG_COMBO_PHY1_P1_BASE + 0x33)
#define REG_COMBO_PHY1_P1_1A_L       (REG_COMBO_PHY1_P1_BASE + 0x34)
#define REG_COMBO_PHY1_P1_1A_H       (REG_COMBO_PHY1_P1_BASE + 0x35)
#define REG_COMBO_PHY1_P1_1B_L       (REG_COMBO_PHY1_P1_BASE + 0x36)
#define REG_COMBO_PHY1_P1_1B_H       (REG_COMBO_PHY1_P1_BASE + 0x37)
#define REG_COMBO_PHY1_P1_1C_L       (REG_COMBO_PHY1_P1_BASE + 0x38)
#define REG_COMBO_PHY1_P1_1C_H       (REG_COMBO_PHY1_P1_BASE + 0x39)
#define REG_COMBO_PHY1_P1_1D_L       (REG_COMBO_PHY1_P1_BASE + 0x3A)
#define REG_COMBO_PHY1_P1_1D_H       (REG_COMBO_PHY1_P1_BASE + 0x3B)
#define REG_COMBO_PHY1_P1_1E_L       (REG_COMBO_PHY1_P1_BASE + 0x3C)
#define REG_COMBO_PHY1_P1_1E_H       (REG_COMBO_PHY1_P1_BASE + 0x3D)
#define REG_COMBO_PHY1_P1_1F_L       (REG_COMBO_PHY1_P1_BASE + 0x3E)
#define REG_COMBO_PHY1_P1_1F_H       (REG_COMBO_PHY1_P1_BASE + 0x3F)
#define REG_COMBO_PHY1_P1_20_L       (REG_COMBO_PHY1_P1_BASE + 0x40)
#define REG_COMBO_PHY1_P1_20_H       (REG_COMBO_PHY1_P1_BASE + 0x41)
#define REG_COMBO_PHY1_P1_21_L       (REG_COMBO_PHY1_P1_BASE + 0x42)
#define REG_COMBO_PHY1_P1_21_H       (REG_COMBO_PHY1_P1_BASE + 0x43)
#define REG_COMBO_PHY1_P1_22_L       (REG_COMBO_PHY1_P1_BASE + 0x44)
#define REG_COMBO_PHY1_P1_22_H       (REG_COMBO_PHY1_P1_BASE + 0x45)
#define REG_COMBO_PHY1_P1_23_L       (REG_COMBO_PHY1_P1_BASE + 0x46)
#define REG_COMBO_PHY1_P1_23_H       (REG_COMBO_PHY1_P1_BASE + 0x47)
#define REG_COMBO_PHY1_P1_24_L       (REG_COMBO_PHY1_P1_BASE + 0x48)
#define REG_COMBO_PHY1_P1_24_H       (REG_COMBO_PHY1_P1_BASE + 0x49)
#define REG_COMBO_PHY1_P1_25_L       (REG_COMBO_PHY1_P1_BASE + 0x4A)
#define REG_COMBO_PHY1_P1_25_H       (REG_COMBO_PHY1_P1_BASE + 0x4B)
#define REG_COMBO_PHY1_P1_26_L       (REG_COMBO_PHY1_P1_BASE + 0x4C)
#define REG_COMBO_PHY1_P1_26_H       (REG_COMBO_PHY1_P1_BASE + 0x4D)
#define REG_COMBO_PHY1_P1_27_L       (REG_COMBO_PHY1_P1_BASE + 0x4E)
#define REG_COMBO_PHY1_P1_27_H       (REG_COMBO_PHY1_P1_BASE + 0x4F)
#define REG_COMBO_PHY1_P1_28_L       (REG_COMBO_PHY1_P1_BASE + 0x50)
#define REG_COMBO_PHY1_P1_28_H       (REG_COMBO_PHY1_P1_BASE + 0x51)
#define REG_COMBO_PHY1_P1_29_L       (REG_COMBO_PHY1_P1_BASE + 0x52)
#define REG_COMBO_PHY1_P1_29_H       (REG_COMBO_PHY1_P1_BASE + 0x53)
#define REG_COMBO_PHY1_P1_2A_L       (REG_COMBO_PHY1_P1_BASE + 0x54)
#define REG_COMBO_PHY1_P1_2A_H       (REG_COMBO_PHY1_P1_BASE + 0x55)
#define REG_COMBO_PHY1_P1_2B_L       (REG_COMBO_PHY1_P1_BASE + 0x56)
#define REG_COMBO_PHY1_P1_2B_H       (REG_COMBO_PHY1_P1_BASE + 0x57)
#define REG_COMBO_PHY1_P1_2C_L       (REG_COMBO_PHY1_P1_BASE + 0x58)
#define REG_COMBO_PHY1_P1_2C_H       (REG_COMBO_PHY1_P1_BASE + 0x59)
#define REG_COMBO_PHY1_P1_2D_L       (REG_COMBO_PHY1_P1_BASE + 0x5A)
#define REG_COMBO_PHY1_P1_2D_H       (REG_COMBO_PHY1_P1_BASE + 0x5B)
#define REG_COMBO_PHY1_P1_2E_L       (REG_COMBO_PHY1_P1_BASE + 0x5C)
#define REG_COMBO_PHY1_P1_2E_H       (REG_COMBO_PHY1_P1_BASE + 0x5D)
#define REG_COMBO_PHY1_P1_2F_L       (REG_COMBO_PHY1_P1_BASE + 0x5E)
#define REG_COMBO_PHY1_P1_2F_H       (REG_COMBO_PHY1_P1_BASE + 0x5F)
#define REG_COMBO_PHY1_P1_30_L       (REG_COMBO_PHY1_P1_BASE + 0x60)
#define REG_COMBO_PHY1_P1_30_H       (REG_COMBO_PHY1_P1_BASE + 0x61)
#define REG_COMBO_PHY1_P1_31_L       (REG_COMBO_PHY1_P1_BASE + 0x62)
#define REG_COMBO_PHY1_P1_31_H       (REG_COMBO_PHY1_P1_BASE + 0x63)
#define REG_COMBO_PHY1_P1_32_L       (REG_COMBO_PHY1_P1_BASE + 0x64)
#define REG_COMBO_PHY1_P1_32_H       (REG_COMBO_PHY1_P1_BASE + 0x65)
#define REG_COMBO_PHY1_P1_33_L       (REG_COMBO_PHY1_P1_BASE + 0x66)
#define REG_COMBO_PHY1_P1_33_H       (REG_COMBO_PHY1_P1_BASE + 0x67)
#define REG_COMBO_PHY1_P1_34_L       (REG_COMBO_PHY1_P1_BASE + 0x68)
#define REG_COMBO_PHY1_P1_34_H       (REG_COMBO_PHY1_P1_BASE + 0x69)
#define REG_COMBO_PHY1_P1_35_L       (REG_COMBO_PHY1_P1_BASE + 0x6A)
#define REG_COMBO_PHY1_P1_35_H       (REG_COMBO_PHY1_P1_BASE + 0x6B)
#define REG_COMBO_PHY1_P1_36_L       (REG_COMBO_PHY1_P1_BASE + 0x6C)
#define REG_COMBO_PHY1_P1_36_H       (REG_COMBO_PHY1_P1_BASE + 0x6D)
#define REG_COMBO_PHY1_P1_37_L       (REG_COMBO_PHY1_P1_BASE + 0x6E)
#define REG_COMBO_PHY1_P1_37_H       (REG_COMBO_PHY1_P1_BASE + 0x6F)
#define REG_COMBO_PHY1_P1_38_L       (REG_COMBO_PHY1_P1_BASE + 0x70)
#define REG_COMBO_PHY1_P1_38_H       (REG_COMBO_PHY1_P1_BASE + 0x71)
#define REG_COMBO_PHY1_P1_39_L       (REG_COMBO_PHY1_P1_BASE + 0x72)
#define REG_COMBO_PHY1_P1_39_H       (REG_COMBO_PHY1_P1_BASE + 0x73)
#define REG_COMBO_PHY1_P1_3A_L       (REG_COMBO_PHY1_P1_BASE + 0x74)
#define REG_COMBO_PHY1_P1_3A_H       (REG_COMBO_PHY1_P1_BASE + 0x75)
#define REG_COMBO_PHY1_P1_3B_L       (REG_COMBO_PHY1_P1_BASE + 0x76)
#define REG_COMBO_PHY1_P1_3B_H       (REG_COMBO_PHY1_P1_BASE + 0x77)
#define REG_COMBO_PHY1_P1_3C_L       (REG_COMBO_PHY1_P1_BASE + 0x78)
#define REG_COMBO_PHY1_P1_3C_H       (REG_COMBO_PHY1_P1_BASE + 0x79)
#define REG_COMBO_PHY1_P1_3D_L       (REG_COMBO_PHY1_P1_BASE + 0x7A)
#define REG_COMBO_PHY1_P1_3D_H       (REG_COMBO_PHY1_P1_BASE + 0x7B)
#define REG_COMBO_PHY1_P1_3E_L       (REG_COMBO_PHY1_P1_BASE + 0x7C)
#define REG_COMBO_PHY1_P1_3E_H       (REG_COMBO_PHY1_P1_BASE + 0x7D)
#define REG_COMBO_PHY1_P1_3F_L       (REG_COMBO_PHY1_P1_BASE + 0x7E)
#define REG_COMBO_PHY1_P1_3F_H       (REG_COMBO_PHY1_P1_BASE + 0x7F)
#define REG_COMBO_PHY1_P1_40_L       (REG_COMBO_PHY1_P1_BASE + 0x80)
#define REG_COMBO_PHY1_P1_40_H       (REG_COMBO_PHY1_P1_BASE + 0x81)
#define REG_COMBO_PHY1_P1_41_L       (REG_COMBO_PHY1_P1_BASE + 0x82)
#define REG_COMBO_PHY1_P1_41_H       (REG_COMBO_PHY1_P1_BASE + 0x83)
#define REG_COMBO_PHY1_P1_42_L       (REG_COMBO_PHY1_P1_BASE + 0x84)
#define REG_COMBO_PHY1_P1_42_H       (REG_COMBO_PHY1_P1_BASE + 0x85)
#define REG_COMBO_PHY1_P1_43_L       (REG_COMBO_PHY1_P1_BASE + 0x86)
#define REG_COMBO_PHY1_P1_43_H       (REG_COMBO_PHY1_P1_BASE + 0x87)
#define REG_COMBO_PHY1_P1_44_L       (REG_COMBO_PHY1_P1_BASE + 0x88)
#define REG_COMBO_PHY1_P1_44_H       (REG_COMBO_PHY1_P1_BASE + 0x89)
#define REG_COMBO_PHY1_P1_45_L       (REG_COMBO_PHY1_P1_BASE + 0x8A)
#define REG_COMBO_PHY1_P1_45_H       (REG_COMBO_PHY1_P1_BASE + 0x8B)
#define REG_COMBO_PHY1_P1_46_L       (REG_COMBO_PHY1_P1_BASE + 0x8C)
#define REG_COMBO_PHY1_P1_46_H       (REG_COMBO_PHY1_P1_BASE + 0x8D)
#define REG_COMBO_PHY1_P1_47_L       (REG_COMBO_PHY1_P1_BASE + 0x8E)
#define REG_COMBO_PHY1_P1_47_H       (REG_COMBO_PHY1_P1_BASE + 0x8F)
#define REG_COMBO_PHY1_P1_48_L       (REG_COMBO_PHY1_P1_BASE + 0x90)
#define REG_COMBO_PHY1_P1_48_H       (REG_COMBO_PHY1_P1_BASE + 0x91)
#define REG_COMBO_PHY1_P1_49_L       (REG_COMBO_PHY1_P1_BASE + 0x92)
#define REG_COMBO_PHY1_P1_49_H       (REG_COMBO_PHY1_P1_BASE + 0x93)
#define REG_COMBO_PHY1_P1_4A_L       (REG_COMBO_PHY1_P1_BASE + 0x94)
#define REG_COMBO_PHY1_P1_4A_H       (REG_COMBO_PHY1_P1_BASE + 0x95)
#define REG_COMBO_PHY1_P1_4B_L       (REG_COMBO_PHY1_P1_BASE + 0x96)
#define REG_COMBO_PHY1_P1_4B_H       (REG_COMBO_PHY1_P1_BASE + 0x97)
#define REG_COMBO_PHY1_P1_4C_L       (REG_COMBO_PHY1_P1_BASE + 0x98)
#define REG_COMBO_PHY1_P1_4C_H       (REG_COMBO_PHY1_P1_BASE + 0x99)
#define REG_COMBO_PHY1_P1_4D_L       (REG_COMBO_PHY1_P1_BASE + 0x9A)
#define REG_COMBO_PHY1_P1_4D_H       (REG_COMBO_PHY1_P1_BASE + 0x9B)
#define REG_COMBO_PHY1_P1_4E_L       (REG_COMBO_PHY1_P1_BASE + 0x9C)
#define REG_COMBO_PHY1_P1_4E_H       (REG_COMBO_PHY1_P1_BASE + 0x9D)
#define REG_COMBO_PHY1_P1_4F_L       (REG_COMBO_PHY1_P1_BASE + 0x9E)
#define REG_COMBO_PHY1_P1_4F_H       (REG_COMBO_PHY1_P1_BASE + 0x9F)
#define REG_COMBO_PHY1_P1_50_L       (REG_COMBO_PHY1_P1_BASE + 0xA0)
#define REG_COMBO_PHY1_P1_50_H       (REG_COMBO_PHY1_P1_BASE + 0xA1)
#define REG_COMBO_PHY1_P1_51_L       (REG_COMBO_PHY1_P1_BASE + 0xA2)
#define REG_COMBO_PHY1_P1_51_H       (REG_COMBO_PHY1_P1_BASE + 0xA3)
#define REG_COMBO_PHY1_P1_52_L       (REG_COMBO_PHY1_P1_BASE + 0xA4)
#define REG_COMBO_PHY1_P1_52_H       (REG_COMBO_PHY1_P1_BASE + 0xA5)
#define REG_COMBO_PHY1_P1_53_L       (REG_COMBO_PHY1_P1_BASE + 0xA6)
#define REG_COMBO_PHY1_P1_53_H       (REG_COMBO_PHY1_P1_BASE + 0xA7)
#define REG_COMBO_PHY1_P1_54_L       (REG_COMBO_PHY1_P1_BASE + 0xA8)
#define REG_COMBO_PHY1_P1_54_H       (REG_COMBO_PHY1_P1_BASE + 0xA9)
#define REG_COMBO_PHY1_P1_55_L       (REG_COMBO_PHY1_P1_BASE + 0xAA)
#define REG_COMBO_PHY1_P1_55_H       (REG_COMBO_PHY1_P1_BASE + 0xAB)
#define REG_COMBO_PHY1_P1_56_L       (REG_COMBO_PHY1_P1_BASE + 0xAC)
#define REG_COMBO_PHY1_P1_56_H       (REG_COMBO_PHY1_P1_BASE + 0xAD)
#define REG_COMBO_PHY1_P1_57_L       (REG_COMBO_PHY1_P1_BASE + 0xAE)
#define REG_COMBO_PHY1_P1_57_H       (REG_COMBO_PHY1_P1_BASE + 0xAF)
#define REG_COMBO_PHY1_P1_58_L       (REG_COMBO_PHY1_P1_BASE + 0xB0)
#define REG_COMBO_PHY1_P1_58_H       (REG_COMBO_PHY1_P1_BASE + 0xB1)
#define REG_COMBO_PHY1_P1_59_L       (REG_COMBO_PHY1_P1_BASE + 0xB2)
#define REG_COMBO_PHY1_P1_59_H       (REG_COMBO_PHY1_P1_BASE + 0xB3)
#define REG_COMBO_PHY1_P1_5A_L       (REG_COMBO_PHY1_P1_BASE + 0xB4)
#define REG_COMBO_PHY1_P1_5A_H       (REG_COMBO_PHY1_P1_BASE + 0xB5)
#define REG_COMBO_PHY1_P1_5B_L       (REG_COMBO_PHY1_P1_BASE + 0xB6)
#define REG_COMBO_PHY1_P1_5B_H       (REG_COMBO_PHY1_P1_BASE + 0xB7)
#define REG_COMBO_PHY1_P1_5C_L       (REG_COMBO_PHY1_P1_BASE + 0xB8)
#define REG_COMBO_PHY1_P1_5C_H       (REG_COMBO_PHY1_P1_BASE + 0xB9)
#define REG_COMBO_PHY1_P1_5D_L       (REG_COMBO_PHY1_P1_BASE + 0xBA)
#define REG_COMBO_PHY1_P1_5D_H       (REG_COMBO_PHY1_P1_BASE + 0xBB)
#define REG_COMBO_PHY1_P1_5E_L       (REG_COMBO_PHY1_P1_BASE + 0xBC)
#define REG_COMBO_PHY1_P1_5E_H       (REG_COMBO_PHY1_P1_BASE + 0xBD)
#define REG_COMBO_PHY1_P1_5F_L       (REG_COMBO_PHY1_P1_BASE + 0xBE)
#define REG_COMBO_PHY1_P1_5F_H       (REG_COMBO_PHY1_P1_BASE + 0xBF)
#define REG_COMBO_PHY1_P1_60_L       (REG_COMBO_PHY1_P1_BASE + 0xC0)
#define REG_COMBO_PHY1_P1_60_H       (REG_COMBO_PHY1_P1_BASE + 0xC1)
#define REG_COMBO_PHY1_P1_61_L       (REG_COMBO_PHY1_P1_BASE + 0xC2)
#define REG_COMBO_PHY1_P1_61_H       (REG_COMBO_PHY1_P1_BASE + 0xC3)
#define REG_COMBO_PHY1_P1_62_L       (REG_COMBO_PHY1_P1_BASE + 0xC4)
#define REG_COMBO_PHY1_P1_62_H       (REG_COMBO_PHY1_P1_BASE + 0xC5)
#define REG_COMBO_PHY1_P1_63_L       (REG_COMBO_PHY1_P1_BASE + 0xC6)
#define REG_COMBO_PHY1_P1_63_H       (REG_COMBO_PHY1_P1_BASE + 0xC7)
#define REG_COMBO_PHY1_P1_64_L       (REG_COMBO_PHY1_P1_BASE + 0xC8)
#define REG_COMBO_PHY1_P1_64_H       (REG_COMBO_PHY1_P1_BASE + 0xC9)
#define REG_COMBO_PHY1_P1_65_L       (REG_COMBO_PHY1_P1_BASE + 0xCA)
#define REG_COMBO_PHY1_P1_65_H       (REG_COMBO_PHY1_P1_BASE + 0xCB)
#define REG_COMBO_PHY1_P1_66_L       (REG_COMBO_PHY1_P1_BASE + 0xCC)
#define REG_COMBO_PHY1_P1_66_H       (REG_COMBO_PHY1_P1_BASE + 0xCD)
#define REG_COMBO_PHY1_P1_67_L       (REG_COMBO_PHY1_P1_BASE + 0xCE)
#define REG_COMBO_PHY1_P1_67_H       (REG_COMBO_PHY1_P1_BASE + 0xCF)
#define REG_COMBO_PHY1_P1_68_L       (REG_COMBO_PHY1_P1_BASE + 0xD0)
#define REG_COMBO_PHY1_P1_68_H       (REG_COMBO_PHY1_P1_BASE + 0xD1)
#define REG_COMBO_PHY1_P1_69_L       (REG_COMBO_PHY1_P1_BASE + 0xD2)
#define REG_COMBO_PHY1_P1_69_H       (REG_COMBO_PHY1_P1_BASE + 0xD3)
#define REG_COMBO_PHY1_P1_6A_L       (REG_COMBO_PHY1_P1_BASE + 0xD4)
#define REG_COMBO_PHY1_P1_6A_H       (REG_COMBO_PHY1_P1_BASE + 0xD5)
#define REG_COMBO_PHY1_P1_6B_L       (REG_COMBO_PHY1_P1_BASE + 0xD6)
#define REG_COMBO_PHY1_P1_6B_H       (REG_COMBO_PHY1_P1_BASE + 0xD7)
#define REG_COMBO_PHY1_P1_6C_L       (REG_COMBO_PHY1_P1_BASE + 0xD8)
#define REG_COMBO_PHY1_P1_6C_H       (REG_COMBO_PHY1_P1_BASE + 0xD9)
#define REG_COMBO_PHY1_P1_6D_L       (REG_COMBO_PHY1_P1_BASE + 0xDA)
#define REG_COMBO_PHY1_P1_6D_H       (REG_COMBO_PHY1_P1_BASE + 0xDB)
#define REG_COMBO_PHY1_P1_6E_L       (REG_COMBO_PHY1_P1_BASE + 0xDC)
#define REG_COMBO_PHY1_P1_6E_H       (REG_COMBO_PHY1_P1_BASE + 0xDD)
#define REG_COMBO_PHY1_P1_6F_L       (REG_COMBO_PHY1_P1_BASE + 0xDE)
#define REG_COMBO_PHY1_P1_6F_H       (REG_COMBO_PHY1_P1_BASE + 0xDF)
#define REG_COMBO_PHY1_P1_70_L       (REG_COMBO_PHY1_P1_BASE + 0xE0)
#define REG_COMBO_PHY1_P1_70_H       (REG_COMBO_PHY1_P1_BASE + 0xE1)
#define REG_COMBO_PHY1_P1_71_L       (REG_COMBO_PHY1_P1_BASE + 0xE2)
#define REG_COMBO_PHY1_P1_71_H       (REG_COMBO_PHY1_P1_BASE + 0xE3)
#define REG_COMBO_PHY1_P1_72_L       (REG_COMBO_PHY1_P1_BASE + 0xE4)
#define REG_COMBO_PHY1_P1_72_H       (REG_COMBO_PHY1_P1_BASE + 0xE5)
#define REG_COMBO_PHY1_P1_73_L       (REG_COMBO_PHY1_P1_BASE + 0xE6)
#define REG_COMBO_PHY1_P1_73_H       (REG_COMBO_PHY1_P1_BASE + 0xE7)
#define REG_COMBO_PHY1_P1_74_L       (REG_COMBO_PHY1_P1_BASE + 0xE8)
#define REG_COMBO_PHY1_P1_74_H       (REG_COMBO_PHY1_P1_BASE + 0xE9)
#define REG_COMBO_PHY1_P1_75_L       (REG_COMBO_PHY1_P1_BASE + 0xEA)
#define REG_COMBO_PHY1_P1_75_H       (REG_COMBO_PHY1_P1_BASE + 0xEB)
#define REG_COMBO_PHY1_P1_76_L       (REG_COMBO_PHY1_P1_BASE + 0xEC)
#define REG_COMBO_PHY1_P1_76_H       (REG_COMBO_PHY1_P1_BASE + 0xED)
#define REG_COMBO_PHY1_P1_77_L       (REG_COMBO_PHY1_P1_BASE + 0xEE)
#define REG_COMBO_PHY1_P1_77_H       (REG_COMBO_PHY1_P1_BASE + 0xEF)
#define REG_COMBO_PHY1_P1_78_L       (REG_COMBO_PHY1_P1_BASE + 0xF0)
#define REG_COMBO_PHY1_P1_78_H       (REG_COMBO_PHY1_P1_BASE + 0xF1)
#define REG_COMBO_PHY1_P1_79_L       (REG_COMBO_PHY1_P1_BASE + 0xF2)
#define REG_COMBO_PHY1_P1_79_H       (REG_COMBO_PHY1_P1_BASE + 0xF3)
#define REG_COMBO_PHY1_P1_7A_L       (REG_COMBO_PHY1_P1_BASE + 0xF4)
#define REG_COMBO_PHY1_P1_7A_H       (REG_COMBO_PHY1_P1_BASE + 0xF5)
#define REG_COMBO_PHY1_P1_7B_L       (REG_COMBO_PHY1_P1_BASE + 0xF6)
#define REG_COMBO_PHY1_P1_7B_H       (REG_COMBO_PHY1_P1_BASE + 0xF7)
#define REG_COMBO_PHY1_P1_7C_L       (REG_COMBO_PHY1_P1_BASE + 0xF8)
#define REG_COMBO_PHY1_P1_7C_H       (REG_COMBO_PHY1_P1_BASE + 0xF9)
#define REG_COMBO_PHY1_P1_7D_L       (REG_COMBO_PHY1_P1_BASE + 0xFA)
#define REG_COMBO_PHY1_P1_7D_H       (REG_COMBO_PHY1_P1_BASE + 0xFB)
#define REG_COMBO_PHY1_P1_7E_L       (REG_COMBO_PHY1_P1_BASE + 0xFC)
#define REG_COMBO_PHY1_P1_7E_H       (REG_COMBO_PHY1_P1_BASE + 0xFD)
#define REG_COMBO_PHY1_P1_7F_L       (REG_COMBO_PHY1_P1_BASE + 0xFE)
#define REG_COMBO_PHY1_P1_7F_H       (REG_COMBO_PHY1_P1_BASE + 0xFF)

// COMBO_PHY0_P2
#define REG_COMBO_PHY0_P2_00_L       (REG_COMBO_PHY0_P2_BASE + 0x00)
#define REG_COMBO_PHY0_P2_00_H       (REG_COMBO_PHY0_P2_BASE + 0x01)
#define REG_COMBO_PHY0_P2_01_L       (REG_COMBO_PHY0_P2_BASE + 0x02)
#define REG_COMBO_PHY0_P2_01_H       (REG_COMBO_PHY0_P2_BASE + 0x03)
#define REG_COMBO_PHY0_P2_02_L       (REG_COMBO_PHY0_P2_BASE + 0x04)
#define REG_COMBO_PHY0_P2_02_H       (REG_COMBO_PHY0_P2_BASE + 0x05)
#define REG_COMBO_PHY0_P2_03_L       (REG_COMBO_PHY0_P2_BASE + 0x06)
#define REG_COMBO_PHY0_P2_03_H       (REG_COMBO_PHY0_P2_BASE + 0x07)
#define REG_COMBO_PHY0_P2_04_L       (REG_COMBO_PHY0_P2_BASE + 0x08)
#define REG_COMBO_PHY0_P2_04_H       (REG_COMBO_PHY0_P2_BASE + 0x09)
#define REG_COMBO_PHY0_P2_05_L       (REG_COMBO_PHY0_P2_BASE + 0x0A)
#define REG_COMBO_PHY0_P2_05_H       (REG_COMBO_PHY0_P2_BASE + 0x0B)
#define REG_COMBO_PHY0_P2_06_L       (REG_COMBO_PHY0_P2_BASE + 0x0C)
#define REG_COMBO_PHY0_P2_06_H       (REG_COMBO_PHY0_P2_BASE + 0x0D)
#define REG_COMBO_PHY0_P2_07_L       (REG_COMBO_PHY0_P2_BASE + 0x0E)
#define REG_COMBO_PHY0_P2_07_H       (REG_COMBO_PHY0_P2_BASE + 0x0F)
#define REG_COMBO_PHY0_P2_08_L       (REG_COMBO_PHY0_P2_BASE + 0x10)
#define REG_COMBO_PHY0_P2_08_H       (REG_COMBO_PHY0_P2_BASE + 0x11)
#define REG_COMBO_PHY0_P2_09_L       (REG_COMBO_PHY0_P2_BASE + 0x12)
#define REG_COMBO_PHY0_P2_09_H       (REG_COMBO_PHY0_P2_BASE + 0x13)
#define REG_COMBO_PHY0_P2_0A_L       (REG_COMBO_PHY0_P2_BASE + 0x14)
#define REG_COMBO_PHY0_P2_0A_H       (REG_COMBO_PHY0_P2_BASE + 0x15)
#define REG_COMBO_PHY0_P2_0B_L       (REG_COMBO_PHY0_P2_BASE + 0x16)
#define REG_COMBO_PHY0_P2_0B_H       (REG_COMBO_PHY0_P2_BASE + 0x17)
#define REG_COMBO_PHY0_P2_0C_L       (REG_COMBO_PHY0_P2_BASE + 0x18)
#define REG_COMBO_PHY0_P2_0C_H       (REG_COMBO_PHY0_P2_BASE + 0x19)
#define REG_COMBO_PHY0_P2_0D_L       (REG_COMBO_PHY0_P2_BASE + 0x1A)
#define REG_COMBO_PHY0_P2_0D_H       (REG_COMBO_PHY0_P2_BASE + 0x1B)
#define REG_COMBO_PHY0_P2_0E_L       (REG_COMBO_PHY0_P2_BASE + 0x1C)
#define REG_COMBO_PHY0_P2_0E_H       (REG_COMBO_PHY0_P2_BASE + 0x1D)
#define REG_COMBO_PHY0_P2_0F_L       (REG_COMBO_PHY0_P2_BASE + 0x1E)
#define REG_COMBO_PHY0_P2_0F_H       (REG_COMBO_PHY0_P2_BASE + 0x1F)
#define REG_COMBO_PHY0_P2_10_L       (REG_COMBO_PHY0_P2_BASE + 0x20)
#define REG_COMBO_PHY0_P2_10_H       (REG_COMBO_PHY0_P2_BASE + 0x21)
#define REG_COMBO_PHY0_P2_11_L       (REG_COMBO_PHY0_P2_BASE + 0x22)
#define REG_COMBO_PHY0_P2_11_H       (REG_COMBO_PHY0_P2_BASE + 0x23)
#define REG_COMBO_PHY0_P2_12_L       (REG_COMBO_PHY0_P2_BASE + 0x24)
#define REG_COMBO_PHY0_P2_12_H       (REG_COMBO_PHY0_P2_BASE + 0x25)
#define REG_COMBO_PHY0_P2_13_L       (REG_COMBO_PHY0_P2_BASE + 0x26)
#define REG_COMBO_PHY0_P2_13_H       (REG_COMBO_PHY0_P2_BASE + 0x27)
#define REG_COMBO_PHY0_P2_14_L       (REG_COMBO_PHY0_P2_BASE + 0x28)
#define REG_COMBO_PHY0_P2_14_H       (REG_COMBO_PHY0_P2_BASE + 0x29)
#define REG_COMBO_PHY0_P2_15_L       (REG_COMBO_PHY0_P2_BASE + 0x2A)
#define REG_COMBO_PHY0_P2_15_H       (REG_COMBO_PHY0_P2_BASE + 0x2B)
#define REG_COMBO_PHY0_P2_16_L       (REG_COMBO_PHY0_P2_BASE + 0x2C)
#define REG_COMBO_PHY0_P2_16_H       (REG_COMBO_PHY0_P2_BASE + 0x2D)
#define REG_COMBO_PHY0_P2_17_L       (REG_COMBO_PHY0_P2_BASE + 0x2E)
#define REG_COMBO_PHY0_P2_17_H       (REG_COMBO_PHY0_P2_BASE + 0x2F)
#define REG_COMBO_PHY0_P2_18_L       (REG_COMBO_PHY0_P2_BASE + 0x30)
#define REG_COMBO_PHY0_P2_18_H       (REG_COMBO_PHY0_P2_BASE + 0x31)
#define REG_COMBO_PHY0_P2_19_L       (REG_COMBO_PHY0_P2_BASE + 0x32)
#define REG_COMBO_PHY0_P2_19_H       (REG_COMBO_PHY0_P2_BASE + 0x33)
#define REG_COMBO_PHY0_P2_1A_L       (REG_COMBO_PHY0_P2_BASE + 0x34)
#define REG_COMBO_PHY0_P2_1A_H       (REG_COMBO_PHY0_P2_BASE + 0x35)
#define REG_COMBO_PHY0_P2_1B_L       (REG_COMBO_PHY0_P2_BASE + 0x36)
#define REG_COMBO_PHY0_P2_1B_H       (REG_COMBO_PHY0_P2_BASE + 0x37)
#define REG_COMBO_PHY0_P2_1C_L       (REG_COMBO_PHY0_P2_BASE + 0x38)
#define REG_COMBO_PHY0_P2_1C_H       (REG_COMBO_PHY0_P2_BASE + 0x39)
#define REG_COMBO_PHY0_P2_1D_L       (REG_COMBO_PHY0_P2_BASE + 0x3A)
#define REG_COMBO_PHY0_P2_1D_H       (REG_COMBO_PHY0_P2_BASE + 0x3B)
#define REG_COMBO_PHY0_P2_1E_L       (REG_COMBO_PHY0_P2_BASE + 0x3C)
#define REG_COMBO_PHY0_P2_1E_H       (REG_COMBO_PHY0_P2_BASE + 0x3D)
#define REG_COMBO_PHY0_P2_1F_L       (REG_COMBO_PHY0_P2_BASE + 0x3E)
#define REG_COMBO_PHY0_P2_1F_H       (REG_COMBO_PHY0_P2_BASE + 0x3F)
#define REG_COMBO_PHY0_P2_20_L       (REG_COMBO_PHY0_P2_BASE + 0x40)
#define REG_COMBO_PHY0_P2_20_H       (REG_COMBO_PHY0_P2_BASE + 0x41)
#define REG_COMBO_PHY0_P2_21_L       (REG_COMBO_PHY0_P2_BASE + 0x42)
#define REG_COMBO_PHY0_P2_21_H       (REG_COMBO_PHY0_P2_BASE + 0x43)
#define REG_COMBO_PHY0_P2_22_L       (REG_COMBO_PHY0_P2_BASE + 0x44)
#define REG_COMBO_PHY0_P2_22_H       (REG_COMBO_PHY0_P2_BASE + 0x45)
#define REG_COMBO_PHY0_P2_23_L       (REG_COMBO_PHY0_P2_BASE + 0x46)
#define REG_COMBO_PHY0_P2_23_H       (REG_COMBO_PHY0_P2_BASE + 0x47)
#define REG_COMBO_PHY0_P2_24_L       (REG_COMBO_PHY0_P2_BASE + 0x48)
#define REG_COMBO_PHY0_P2_24_H       (REG_COMBO_PHY0_P2_BASE + 0x49)
#define REG_COMBO_PHY0_P2_25_L       (REG_COMBO_PHY0_P2_BASE + 0x4A)
#define REG_COMBO_PHY0_P2_25_H       (REG_COMBO_PHY0_P2_BASE + 0x4B)
#define REG_COMBO_PHY0_P2_26_L       (REG_COMBO_PHY0_P2_BASE + 0x4C)
#define REG_COMBO_PHY0_P2_26_H       (REG_COMBO_PHY0_P2_BASE + 0x4D)
#define REG_COMBO_PHY0_P2_27_L       (REG_COMBO_PHY0_P2_BASE + 0x4E)
#define REG_COMBO_PHY0_P2_27_H       (REG_COMBO_PHY0_P2_BASE + 0x4F)
#define REG_COMBO_PHY0_P2_28_L       (REG_COMBO_PHY0_P2_BASE + 0x50)
#define REG_COMBO_PHY0_P2_28_H       (REG_COMBO_PHY0_P2_BASE + 0x51)
#define REG_COMBO_PHY0_P2_29_L       (REG_COMBO_PHY0_P2_BASE + 0x52)
#define REG_COMBO_PHY0_P2_29_H       (REG_COMBO_PHY0_P2_BASE + 0x53)
#define REG_COMBO_PHY0_P2_2A_L       (REG_COMBO_PHY0_P2_BASE + 0x54)
#define REG_COMBO_PHY0_P2_2A_H       (REG_COMBO_PHY0_P2_BASE + 0x55)
#define REG_COMBO_PHY0_P2_2B_L       (REG_COMBO_PHY0_P2_BASE + 0x56)
#define REG_COMBO_PHY0_P2_2B_H       (REG_COMBO_PHY0_P2_BASE + 0x57)
#define REG_COMBO_PHY0_P2_2C_L       (REG_COMBO_PHY0_P2_BASE + 0x58)
#define REG_COMBO_PHY0_P2_2C_H       (REG_COMBO_PHY0_P2_BASE + 0x59)
#define REG_COMBO_PHY0_P2_2D_L       (REG_COMBO_PHY0_P2_BASE + 0x5A)
#define REG_COMBO_PHY0_P2_2D_H       (REG_COMBO_PHY0_P2_BASE + 0x5B)
#define REG_COMBO_PHY0_P2_2E_L       (REG_COMBO_PHY0_P2_BASE + 0x5C)
#define REG_COMBO_PHY0_P2_2E_H       (REG_COMBO_PHY0_P2_BASE + 0x5D)
#define REG_COMBO_PHY0_P2_2F_L       (REG_COMBO_PHY0_P2_BASE + 0x5E)
#define REG_COMBO_PHY0_P2_2F_H       (REG_COMBO_PHY0_P2_BASE + 0x5F)
#define REG_COMBO_PHY0_P2_30_L       (REG_COMBO_PHY0_P2_BASE + 0x60)
#define REG_COMBO_PHY0_P2_30_H       (REG_COMBO_PHY0_P2_BASE + 0x61)
#define REG_COMBO_PHY0_P2_31_L       (REG_COMBO_PHY0_P2_BASE + 0x62)
#define REG_COMBO_PHY0_P2_31_H       (REG_COMBO_PHY0_P2_BASE + 0x63)
#define REG_COMBO_PHY0_P2_32_L       (REG_COMBO_PHY0_P2_BASE + 0x64)
#define REG_COMBO_PHY0_P2_32_H       (REG_COMBO_PHY0_P2_BASE + 0x65)
#define REG_COMBO_PHY0_P2_33_L       (REG_COMBO_PHY0_P2_BASE + 0x66)
#define REG_COMBO_PHY0_P2_33_H       (REG_COMBO_PHY0_P2_BASE + 0x67)
#define REG_COMBO_PHY0_P2_34_L       (REG_COMBO_PHY0_P2_BASE + 0x68)
#define REG_COMBO_PHY0_P2_34_H       (REG_COMBO_PHY0_P2_BASE + 0x69)
#define REG_COMBO_PHY0_P2_35_L       (REG_COMBO_PHY0_P2_BASE + 0x6A)
#define REG_COMBO_PHY0_P2_35_H       (REG_COMBO_PHY0_P2_BASE + 0x6B)
#define REG_COMBO_PHY0_P2_36_L       (REG_COMBO_PHY0_P2_BASE + 0x6C)
#define REG_COMBO_PHY0_P2_36_H       (REG_COMBO_PHY0_P2_BASE + 0x6D)
#define REG_COMBO_PHY0_P2_37_L       (REG_COMBO_PHY0_P2_BASE + 0x6E)
#define REG_COMBO_PHY0_P2_37_H       (REG_COMBO_PHY0_P2_BASE + 0x6F)
#define REG_COMBO_PHY0_P2_38_L       (REG_COMBO_PHY0_P2_BASE + 0x70)
#define REG_COMBO_PHY0_P2_38_H       (REG_COMBO_PHY0_P2_BASE + 0x71)
#define REG_COMBO_PHY0_P2_39_L       (REG_COMBO_PHY0_P2_BASE + 0x72)
#define REG_COMBO_PHY0_P2_39_H       (REG_COMBO_PHY0_P2_BASE + 0x73)
#define REG_COMBO_PHY0_P2_3A_L       (REG_COMBO_PHY0_P2_BASE + 0x74)
#define REG_COMBO_PHY0_P2_3A_H       (REG_COMBO_PHY0_P2_BASE + 0x75)
#define REG_COMBO_PHY0_P2_3B_L       (REG_COMBO_PHY0_P2_BASE + 0x76)
#define REG_COMBO_PHY0_P2_3B_H       (REG_COMBO_PHY0_P2_BASE + 0x77)
#define REG_COMBO_PHY0_P2_3C_L       (REG_COMBO_PHY0_P2_BASE + 0x78)
#define REG_COMBO_PHY0_P2_3C_H       (REG_COMBO_PHY0_P2_BASE + 0x79)
#define REG_COMBO_PHY0_P2_3D_L       (REG_COMBO_PHY0_P2_BASE + 0x7A)
#define REG_COMBO_PHY0_P2_3D_H       (REG_COMBO_PHY0_P2_BASE + 0x7B)
#define REG_COMBO_PHY0_P2_3E_L       (REG_COMBO_PHY0_P2_BASE + 0x7C)
#define REG_COMBO_PHY0_P2_3E_H       (REG_COMBO_PHY0_P2_BASE + 0x7D)
#define REG_COMBO_PHY0_P2_3F_L       (REG_COMBO_PHY0_P2_BASE + 0x7E)
#define REG_COMBO_PHY0_P2_3F_H       (REG_COMBO_PHY0_P2_BASE + 0x7F)
#define REG_COMBO_PHY0_P2_40_L       (REG_COMBO_PHY0_P2_BASE + 0x80)
#define REG_COMBO_PHY0_P2_40_H       (REG_COMBO_PHY0_P2_BASE + 0x81)
#define REG_COMBO_PHY0_P2_41_L       (REG_COMBO_PHY0_P2_BASE + 0x82)
#define REG_COMBO_PHY0_P2_41_H       (REG_COMBO_PHY0_P2_BASE + 0x83)
#define REG_COMBO_PHY0_P2_42_L       (REG_COMBO_PHY0_P2_BASE + 0x84)
#define REG_COMBO_PHY0_P2_42_H       (REG_COMBO_PHY0_P2_BASE + 0x85)
#define REG_COMBO_PHY0_P2_43_L       (REG_COMBO_PHY0_P2_BASE + 0x86)
#define REG_COMBO_PHY0_P2_43_H       (REG_COMBO_PHY0_P2_BASE + 0x87)
#define REG_COMBO_PHY0_P2_44_L       (REG_COMBO_PHY0_P2_BASE + 0x88)
#define REG_COMBO_PHY0_P2_44_H       (REG_COMBO_PHY0_P2_BASE + 0x89)
#define REG_COMBO_PHY0_P2_45_L       (REG_COMBO_PHY0_P2_BASE + 0x8A)
#define REG_COMBO_PHY0_P2_45_H       (REG_COMBO_PHY0_P2_BASE + 0x8B)
#define REG_COMBO_PHY0_P2_46_L       (REG_COMBO_PHY0_P2_BASE + 0x8C)
#define REG_COMBO_PHY0_P2_46_H       (REG_COMBO_PHY0_P2_BASE + 0x8D)
#define REG_COMBO_PHY0_P2_47_L       (REG_COMBO_PHY0_P2_BASE + 0x8E)
#define REG_COMBO_PHY0_P2_47_H       (REG_COMBO_PHY0_P2_BASE + 0x8F)
#define REG_COMBO_PHY0_P2_48_L       (REG_COMBO_PHY0_P2_BASE + 0x90)
#define REG_COMBO_PHY0_P2_48_H       (REG_COMBO_PHY0_P2_BASE + 0x91)
#define REG_COMBO_PHY0_P2_49_L       (REG_COMBO_PHY0_P2_BASE + 0x92)
#define REG_COMBO_PHY0_P2_49_H       (REG_COMBO_PHY0_P2_BASE + 0x93)
#define REG_COMBO_PHY0_P2_4A_L       (REG_COMBO_PHY0_P2_BASE + 0x94)
#define REG_COMBO_PHY0_P2_4A_H       (REG_COMBO_PHY0_P2_BASE + 0x95)
#define REG_COMBO_PHY0_P2_4B_L       (REG_COMBO_PHY0_P2_BASE + 0x96)
#define REG_COMBO_PHY0_P2_4B_H       (REG_COMBO_PHY0_P2_BASE + 0x97)
#define REG_COMBO_PHY0_P2_4C_L       (REG_COMBO_PHY0_P2_BASE + 0x98)
#define REG_COMBO_PHY0_P2_4C_H       (REG_COMBO_PHY0_P2_BASE + 0x99)
#define REG_COMBO_PHY0_P2_4D_L       (REG_COMBO_PHY0_P2_BASE + 0x9A)
#define REG_COMBO_PHY0_P2_4D_H       (REG_COMBO_PHY0_P2_BASE + 0x9B)
#define REG_COMBO_PHY0_P2_4E_L       (REG_COMBO_PHY0_P2_BASE + 0x9C)
#define REG_COMBO_PHY0_P2_4E_H       (REG_COMBO_PHY0_P2_BASE + 0x9D)
#define REG_COMBO_PHY0_P2_4F_L       (REG_COMBO_PHY0_P2_BASE + 0x9E)
#define REG_COMBO_PHY0_P2_4F_H       (REG_COMBO_PHY0_P2_BASE + 0x9F)
#define REG_COMBO_PHY0_P2_50_L       (REG_COMBO_PHY0_P2_BASE + 0xA0)
#define REG_COMBO_PHY0_P2_50_H       (REG_COMBO_PHY0_P2_BASE + 0xA1)
#define REG_COMBO_PHY0_P2_51_L       (REG_COMBO_PHY0_P2_BASE + 0xA2)
#define REG_COMBO_PHY0_P2_51_H       (REG_COMBO_PHY0_P2_BASE + 0xA3)
#define REG_COMBO_PHY0_P2_52_L       (REG_COMBO_PHY0_P2_BASE + 0xA4)
#define REG_COMBO_PHY0_P2_52_H       (REG_COMBO_PHY0_P2_BASE + 0xA5)
#define REG_COMBO_PHY0_P2_53_L       (REG_COMBO_PHY0_P2_BASE + 0xA6)
#define REG_COMBO_PHY0_P2_53_H       (REG_COMBO_PHY0_P2_BASE + 0xA7)
#define REG_COMBO_PHY0_P2_54_L       (REG_COMBO_PHY0_P2_BASE + 0xA8)
#define REG_COMBO_PHY0_P2_54_H       (REG_COMBO_PHY0_P2_BASE + 0xA9)
#define REG_COMBO_PHY0_P2_55_L       (REG_COMBO_PHY0_P2_BASE + 0xAA)
#define REG_COMBO_PHY0_P2_55_H       (REG_COMBO_PHY0_P2_BASE + 0xAB)
#define REG_COMBO_PHY0_P2_56_L       (REG_COMBO_PHY0_P2_BASE + 0xAC)
#define REG_COMBO_PHY0_P2_56_H       (REG_COMBO_PHY0_P2_BASE + 0xAD)
#define REG_COMBO_PHY0_P2_57_L       (REG_COMBO_PHY0_P2_BASE + 0xAE)
#define REG_COMBO_PHY0_P2_57_H       (REG_COMBO_PHY0_P2_BASE + 0xAF)
#define REG_COMBO_PHY0_P2_58_L       (REG_COMBO_PHY0_P2_BASE + 0xB0)
#define REG_COMBO_PHY0_P2_58_H       (REG_COMBO_PHY0_P2_BASE + 0xB1)
#define REG_COMBO_PHY0_P2_59_L       (REG_COMBO_PHY0_P2_BASE + 0xB2)
#define REG_COMBO_PHY0_P2_59_H       (REG_COMBO_PHY0_P2_BASE + 0xB3)
#define REG_COMBO_PHY0_P2_5A_L       (REG_COMBO_PHY0_P2_BASE + 0xB4)
#define REG_COMBO_PHY0_P2_5A_H       (REG_COMBO_PHY0_P2_BASE + 0xB5)
#define REG_COMBO_PHY0_P2_5B_L       (REG_COMBO_PHY0_P2_BASE + 0xB6)
#define REG_COMBO_PHY0_P2_5B_H       (REG_COMBO_PHY0_P2_BASE + 0xB7)
#define REG_COMBO_PHY0_P2_5C_L       (REG_COMBO_PHY0_P2_BASE + 0xB8)
#define REG_COMBO_PHY0_P2_5C_H       (REG_COMBO_PHY0_P2_BASE + 0xB9)
#define REG_COMBO_PHY0_P2_5D_L       (REG_COMBO_PHY0_P2_BASE + 0xBA)
#define REG_COMBO_PHY0_P2_5D_H       (REG_COMBO_PHY0_P2_BASE + 0xBB)
#define REG_COMBO_PHY0_P2_5E_L       (REG_COMBO_PHY0_P2_BASE + 0xBC)
#define REG_COMBO_PHY0_P2_5E_H       (REG_COMBO_PHY0_P2_BASE + 0xBD)
#define REG_COMBO_PHY0_P2_5F_L       (REG_COMBO_PHY0_P2_BASE + 0xBE)
#define REG_COMBO_PHY0_P2_5F_H       (REG_COMBO_PHY0_P2_BASE + 0xBF)
#define REG_COMBO_PHY0_P2_60_L       (REG_COMBO_PHY0_P2_BASE + 0xC0)
#define REG_COMBO_PHY0_P2_60_H       (REG_COMBO_PHY0_P2_BASE + 0xC1)
#define REG_COMBO_PHY0_P2_61_L       (REG_COMBO_PHY0_P2_BASE + 0xC2)
#define REG_COMBO_PHY0_P2_61_H       (REG_COMBO_PHY0_P2_BASE + 0xC3)
#define REG_COMBO_PHY0_P2_62_L       (REG_COMBO_PHY0_P2_BASE + 0xC4)
#define REG_COMBO_PHY0_P2_62_H       (REG_COMBO_PHY0_P2_BASE + 0xC5)
#define REG_COMBO_PHY0_P2_63_L       (REG_COMBO_PHY0_P2_BASE + 0xC6)
#define REG_COMBO_PHY0_P2_63_H       (REG_COMBO_PHY0_P2_BASE + 0xC7)
#define REG_COMBO_PHY0_P2_64_L       (REG_COMBO_PHY0_P2_BASE + 0xC8)
#define REG_COMBO_PHY0_P2_64_H       (REG_COMBO_PHY0_P2_BASE + 0xC9)
#define REG_COMBO_PHY0_P2_65_L       (REG_COMBO_PHY0_P2_BASE + 0xCA)
#define REG_COMBO_PHY0_P2_65_H       (REG_COMBO_PHY0_P2_BASE + 0xCB)
#define REG_COMBO_PHY0_P2_66_L       (REG_COMBO_PHY0_P2_BASE + 0xCC)
#define REG_COMBO_PHY0_P2_66_H       (REG_COMBO_PHY0_P2_BASE + 0xCD)
#define REG_COMBO_PHY0_P2_67_L       (REG_COMBO_PHY0_P2_BASE + 0xCE)
#define REG_COMBO_PHY0_P2_67_H       (REG_COMBO_PHY0_P2_BASE + 0xCF)
#define REG_COMBO_PHY0_P2_68_L       (REG_COMBO_PHY0_P2_BASE + 0xD0)
#define REG_COMBO_PHY0_P2_68_H       (REG_COMBO_PHY0_P2_BASE + 0xD1)
#define REG_COMBO_PHY0_P2_69_L       (REG_COMBO_PHY0_P2_BASE + 0xD2)
#define REG_COMBO_PHY0_P2_69_H       (REG_COMBO_PHY0_P2_BASE + 0xD3)
#define REG_COMBO_PHY0_P2_6A_L       (REG_COMBO_PHY0_P2_BASE + 0xD4)
#define REG_COMBO_PHY0_P2_6A_H       (REG_COMBO_PHY0_P2_BASE + 0xD5)
#define REG_COMBO_PHY0_P2_6B_L       (REG_COMBO_PHY0_P2_BASE + 0xD6)
#define REG_COMBO_PHY0_P2_6B_H       (REG_COMBO_PHY0_P2_BASE + 0xD7)
#define REG_COMBO_PHY0_P2_6C_L       (REG_COMBO_PHY0_P2_BASE + 0xD8)
#define REG_COMBO_PHY0_P2_6C_H       (REG_COMBO_PHY0_P2_BASE + 0xD9)
#define REG_COMBO_PHY0_P2_6D_L       (REG_COMBO_PHY0_P2_BASE + 0xDA)
#define REG_COMBO_PHY0_P2_6D_H       (REG_COMBO_PHY0_P2_BASE + 0xDB)
#define REG_COMBO_PHY0_P2_6E_L       (REG_COMBO_PHY0_P2_BASE + 0xDC)
#define REG_COMBO_PHY0_P2_6E_H       (REG_COMBO_PHY0_P2_BASE + 0xDD)
#define REG_COMBO_PHY0_P2_6F_L       (REG_COMBO_PHY0_P2_BASE + 0xDE)
#define REG_COMBO_PHY0_P2_6F_H       (REG_COMBO_PHY0_P2_BASE + 0xDF)
#define REG_COMBO_PHY0_P2_70_L       (REG_COMBO_PHY0_P2_BASE + 0xE0)
#define REG_COMBO_PHY0_P2_70_H       (REG_COMBO_PHY0_P2_BASE + 0xE1)
#define REG_COMBO_PHY0_P2_71_L       (REG_COMBO_PHY0_P2_BASE + 0xE2)
#define REG_COMBO_PHY0_P2_71_H       (REG_COMBO_PHY0_P2_BASE + 0xE3)
#define REG_COMBO_PHY0_P2_72_L       (REG_COMBO_PHY0_P2_BASE + 0xE4)
#define REG_COMBO_PHY0_P2_72_H       (REG_COMBO_PHY0_P2_BASE + 0xE5)
#define REG_COMBO_PHY0_P2_73_L       (REG_COMBO_PHY0_P2_BASE + 0xE6)
#define REG_COMBO_PHY0_P2_73_H       (REG_COMBO_PHY0_P2_BASE + 0xE7)
#define REG_COMBO_PHY0_P2_74_L       (REG_COMBO_PHY0_P2_BASE + 0xE8)
#define REG_COMBO_PHY0_P2_74_H       (REG_COMBO_PHY0_P2_BASE + 0xE9)
#define REG_COMBO_PHY0_P2_75_L       (REG_COMBO_PHY0_P2_BASE + 0xEA)
#define REG_COMBO_PHY0_P2_75_H       (REG_COMBO_PHY0_P2_BASE + 0xEB)
#define REG_COMBO_PHY0_P2_76_L       (REG_COMBO_PHY0_P2_BASE + 0xEC)
#define REG_COMBO_PHY0_P2_76_H       (REG_COMBO_PHY0_P2_BASE + 0xED)
#define REG_COMBO_PHY0_P2_77_L       (REG_COMBO_PHY0_P2_BASE + 0xEE)
#define REG_COMBO_PHY0_P2_77_H       (REG_COMBO_PHY0_P2_BASE + 0xEF)
#define REG_COMBO_PHY0_P2_78_L       (REG_COMBO_PHY0_P2_BASE + 0xF0)
#define REG_COMBO_PHY0_P2_78_H       (REG_COMBO_PHY0_P2_BASE + 0xF1)
#define REG_COMBO_PHY0_P2_79_L       (REG_COMBO_PHY0_P2_BASE + 0xF2)
#define REG_COMBO_PHY0_P2_79_H       (REG_COMBO_PHY0_P2_BASE + 0xF3)
#define REG_COMBO_PHY0_P2_7A_L       (REG_COMBO_PHY0_P2_BASE + 0xF4)
#define REG_COMBO_PHY0_P2_7A_H       (REG_COMBO_PHY0_P2_BASE + 0xF5)
#define REG_COMBO_PHY0_P2_7B_L       (REG_COMBO_PHY0_P2_BASE + 0xF6)
#define REG_COMBO_PHY0_P2_7B_H       (REG_COMBO_PHY0_P2_BASE + 0xF7)
#define REG_COMBO_PHY0_P2_7C_L       (REG_COMBO_PHY0_P2_BASE + 0xF8)
#define REG_COMBO_PHY0_P2_7C_H       (REG_COMBO_PHY0_P2_BASE + 0xF9)
#define REG_COMBO_PHY0_P2_7D_L       (REG_COMBO_PHY0_P2_BASE + 0xFA)
#define REG_COMBO_PHY0_P2_7D_H       (REG_COMBO_PHY0_P2_BASE + 0xFB)
#define REG_COMBO_PHY0_P2_7E_L       (REG_COMBO_PHY0_P2_BASE + 0xFC)
#define REG_COMBO_PHY0_P2_7E_H       (REG_COMBO_PHY0_P2_BASE + 0xFD)
#define REG_COMBO_PHY0_P2_7F_L       (REG_COMBO_PHY0_P2_BASE + 0xFE)
#define REG_COMBO_PHY0_P2_7F_H       (REG_COMBO_PHY0_P2_BASE + 0xFF)

// COMBO_PHY1_P2
#define REG_COMBO_PHY1_P2_00_L       (REG_COMBO_PHY1_P2_BASE + 0x00)
#define REG_COMBO_PHY1_P2_00_H       (REG_COMBO_PHY1_P2_BASE + 0x01)
#define REG_COMBO_PHY1_P2_01_L       (REG_COMBO_PHY1_P2_BASE + 0x02)
#define REG_COMBO_PHY1_P2_01_H       (REG_COMBO_PHY1_P2_BASE + 0x03)
#define REG_COMBO_PHY1_P2_02_L       (REG_COMBO_PHY1_P2_BASE + 0x04)
#define REG_COMBO_PHY1_P2_02_H       (REG_COMBO_PHY1_P2_BASE + 0x05)
#define REG_COMBO_PHY1_P2_03_L       (REG_COMBO_PHY1_P2_BASE + 0x06)
#define REG_COMBO_PHY1_P2_03_H       (REG_COMBO_PHY1_P2_BASE + 0x07)
#define REG_COMBO_PHY1_P2_04_L       (REG_COMBO_PHY1_P2_BASE + 0x08)
#define REG_COMBO_PHY1_P2_04_H       (REG_COMBO_PHY1_P2_BASE + 0x09)
#define REG_COMBO_PHY1_P2_05_L       (REG_COMBO_PHY1_P2_BASE + 0x0A)
#define REG_COMBO_PHY1_P2_05_H       (REG_COMBO_PHY1_P2_BASE + 0x0B)
#define REG_COMBO_PHY1_P2_06_L       (REG_COMBO_PHY1_P2_BASE + 0x0C)
#define REG_COMBO_PHY1_P2_06_H       (REG_COMBO_PHY1_P2_BASE + 0x0D)
#define REG_COMBO_PHY1_P2_07_L       (REG_COMBO_PHY1_P2_BASE + 0x0E)
#define REG_COMBO_PHY1_P2_07_H       (REG_COMBO_PHY1_P2_BASE + 0x0F)
#define REG_COMBO_PHY1_P2_08_L       (REG_COMBO_PHY1_P2_BASE + 0x10)
#define REG_COMBO_PHY1_P2_08_H       (REG_COMBO_PHY1_P2_BASE + 0x11)
#define REG_COMBO_PHY1_P2_09_L       (REG_COMBO_PHY1_P2_BASE + 0x12)
#define REG_COMBO_PHY1_P2_09_H       (REG_COMBO_PHY1_P2_BASE + 0x13)
#define REG_COMBO_PHY1_P2_0A_L       (REG_COMBO_PHY1_P2_BASE + 0x14)
#define REG_COMBO_PHY1_P2_0A_H       (REG_COMBO_PHY1_P2_BASE + 0x15)
#define REG_COMBO_PHY1_P2_0B_L       (REG_COMBO_PHY1_P2_BASE + 0x16)
#define REG_COMBO_PHY1_P2_0B_H       (REG_COMBO_PHY1_P2_BASE + 0x17)
#define REG_COMBO_PHY1_P2_0C_L       (REG_COMBO_PHY1_P2_BASE + 0x18)
#define REG_COMBO_PHY1_P2_0C_H       (REG_COMBO_PHY1_P2_BASE + 0x19)
#define REG_COMBO_PHY1_P2_0D_L       (REG_COMBO_PHY1_P2_BASE + 0x1A)
#define REG_COMBO_PHY1_P2_0D_H       (REG_COMBO_PHY1_P2_BASE + 0x1B)
#define REG_COMBO_PHY1_P2_0E_L       (REG_COMBO_PHY1_P2_BASE + 0x1C)
#define REG_COMBO_PHY1_P2_0E_H       (REG_COMBO_PHY1_P2_BASE + 0x1D)
#define REG_COMBO_PHY1_P2_0F_L       (REG_COMBO_PHY1_P2_BASE + 0x1E)
#define REG_COMBO_PHY1_P2_0F_H       (REG_COMBO_PHY1_P2_BASE + 0x1F)
#define REG_COMBO_PHY1_P2_10_L       (REG_COMBO_PHY1_P2_BASE + 0x20)
#define REG_COMBO_PHY1_P2_10_H       (REG_COMBO_PHY1_P2_BASE + 0x21)
#define REG_COMBO_PHY1_P2_11_L       (REG_COMBO_PHY1_P2_BASE + 0x22)
#define REG_COMBO_PHY1_P2_11_H       (REG_COMBO_PHY1_P2_BASE + 0x23)
#define REG_COMBO_PHY1_P2_12_L       (REG_COMBO_PHY1_P2_BASE + 0x24)
#define REG_COMBO_PHY1_P2_12_H       (REG_COMBO_PHY1_P2_BASE + 0x25)
#define REG_COMBO_PHY1_P2_13_L       (REG_COMBO_PHY1_P2_BASE + 0x26)
#define REG_COMBO_PHY1_P2_13_H       (REG_COMBO_PHY1_P2_BASE + 0x27)
#define REG_COMBO_PHY1_P2_14_L       (REG_COMBO_PHY1_P2_BASE + 0x28)
#define REG_COMBO_PHY1_P2_14_H       (REG_COMBO_PHY1_P2_BASE + 0x29)
#define REG_COMBO_PHY1_P2_15_L       (REG_COMBO_PHY1_P2_BASE + 0x2A)
#define REG_COMBO_PHY1_P2_15_H       (REG_COMBO_PHY1_P2_BASE + 0x2B)
#define REG_COMBO_PHY1_P2_16_L       (REG_COMBO_PHY1_P2_BASE + 0x2C)
#define REG_COMBO_PHY1_P2_16_H       (REG_COMBO_PHY1_P2_BASE + 0x2D)
#define REG_COMBO_PHY1_P2_17_L       (REG_COMBO_PHY1_P2_BASE + 0x2E)
#define REG_COMBO_PHY1_P2_17_H       (REG_COMBO_PHY1_P2_BASE + 0x2F)
#define REG_COMBO_PHY1_P2_18_L       (REG_COMBO_PHY1_P2_BASE + 0x30)
#define REG_COMBO_PHY1_P2_18_H       (REG_COMBO_PHY1_P2_BASE + 0x31)
#define REG_COMBO_PHY1_P2_19_L       (REG_COMBO_PHY1_P2_BASE + 0x32)
#define REG_COMBO_PHY1_P2_19_H       (REG_COMBO_PHY1_P2_BASE + 0x33)
#define REG_COMBO_PHY1_P2_1A_L       (REG_COMBO_PHY1_P2_BASE + 0x34)
#define REG_COMBO_PHY1_P2_1A_H       (REG_COMBO_PHY1_P2_BASE + 0x35)
#define REG_COMBO_PHY1_P2_1B_L       (REG_COMBO_PHY1_P2_BASE + 0x36)
#define REG_COMBO_PHY1_P2_1B_H       (REG_COMBO_PHY1_P2_BASE + 0x37)
#define REG_COMBO_PHY1_P2_1C_L       (REG_COMBO_PHY1_P2_BASE + 0x38)
#define REG_COMBO_PHY1_P2_1C_H       (REG_COMBO_PHY1_P2_BASE + 0x39)
#define REG_COMBO_PHY1_P2_1D_L       (REG_COMBO_PHY1_P2_BASE + 0x3A)
#define REG_COMBO_PHY1_P2_1D_H       (REG_COMBO_PHY1_P2_BASE + 0x3B)
#define REG_COMBO_PHY1_P2_1E_L       (REG_COMBO_PHY1_P2_BASE + 0x3C)
#define REG_COMBO_PHY1_P2_1E_H       (REG_COMBO_PHY1_P2_BASE + 0x3D)
#define REG_COMBO_PHY1_P2_1F_L       (REG_COMBO_PHY1_P2_BASE + 0x3E)
#define REG_COMBO_PHY1_P2_1F_H       (REG_COMBO_PHY1_P2_BASE + 0x3F)
#define REG_COMBO_PHY1_P2_20_L       (REG_COMBO_PHY1_P2_BASE + 0x40)
#define REG_COMBO_PHY1_P2_20_H       (REG_COMBO_PHY1_P2_BASE + 0x41)
#define REG_COMBO_PHY1_P2_21_L       (REG_COMBO_PHY1_P2_BASE + 0x42)
#define REG_COMBO_PHY1_P2_21_H       (REG_COMBO_PHY1_P2_BASE + 0x43)
#define REG_COMBO_PHY1_P2_22_L       (REG_COMBO_PHY1_P2_BASE + 0x44)
#define REG_COMBO_PHY1_P2_22_H       (REG_COMBO_PHY1_P2_BASE + 0x45)
#define REG_COMBO_PHY1_P2_23_L       (REG_COMBO_PHY1_P2_BASE + 0x46)
#define REG_COMBO_PHY1_P2_23_H       (REG_COMBO_PHY1_P2_BASE + 0x47)
#define REG_COMBO_PHY1_P2_24_L       (REG_COMBO_PHY1_P2_BASE + 0x48)
#define REG_COMBO_PHY1_P2_24_H       (REG_COMBO_PHY1_P2_BASE + 0x49)
#define REG_COMBO_PHY1_P2_25_L       (REG_COMBO_PHY1_P2_BASE + 0x4A)
#define REG_COMBO_PHY1_P2_25_H       (REG_COMBO_PHY1_P2_BASE + 0x4B)
#define REG_COMBO_PHY1_P2_26_L       (REG_COMBO_PHY1_P2_BASE + 0x4C)
#define REG_COMBO_PHY1_P2_26_H       (REG_COMBO_PHY1_P2_BASE + 0x4D)
#define REG_COMBO_PHY1_P2_27_L       (REG_COMBO_PHY1_P2_BASE + 0x4E)
#define REG_COMBO_PHY1_P2_27_H       (REG_COMBO_PHY1_P2_BASE + 0x4F)
#define REG_COMBO_PHY1_P2_28_L       (REG_COMBO_PHY1_P2_BASE + 0x50)
#define REG_COMBO_PHY1_P2_28_H       (REG_COMBO_PHY1_P2_BASE + 0x51)
#define REG_COMBO_PHY1_P2_29_L       (REG_COMBO_PHY1_P2_BASE + 0x52)
#define REG_COMBO_PHY1_P2_29_H       (REG_COMBO_PHY1_P2_BASE + 0x53)
#define REG_COMBO_PHY1_P2_2A_L       (REG_COMBO_PHY1_P2_BASE + 0x54)
#define REG_COMBO_PHY1_P2_2A_H       (REG_COMBO_PHY1_P2_BASE + 0x55)
#define REG_COMBO_PHY1_P2_2B_L       (REG_COMBO_PHY1_P2_BASE + 0x56)
#define REG_COMBO_PHY1_P2_2B_H       (REG_COMBO_PHY1_P2_BASE + 0x57)
#define REG_COMBO_PHY1_P2_2C_L       (REG_COMBO_PHY1_P2_BASE + 0x58)
#define REG_COMBO_PHY1_P2_2C_H       (REG_COMBO_PHY1_P2_BASE + 0x59)
#define REG_COMBO_PHY1_P2_2D_L       (REG_COMBO_PHY1_P2_BASE + 0x5A)
#define REG_COMBO_PHY1_P2_2D_H       (REG_COMBO_PHY1_P2_BASE + 0x5B)
#define REG_COMBO_PHY1_P2_2E_L       (REG_COMBO_PHY1_P2_BASE + 0x5C)
#define REG_COMBO_PHY1_P2_2E_H       (REG_COMBO_PHY1_P2_BASE + 0x5D)
#define REG_COMBO_PHY1_P2_2F_L       (REG_COMBO_PHY1_P2_BASE + 0x5E)
#define REG_COMBO_PHY1_P2_2F_H       (REG_COMBO_PHY1_P2_BASE + 0x5F)
#define REG_COMBO_PHY1_P2_30_L       (REG_COMBO_PHY1_P2_BASE + 0x60)
#define REG_COMBO_PHY1_P2_30_H       (REG_COMBO_PHY1_P2_BASE + 0x61)
#define REG_COMBO_PHY1_P2_31_L       (REG_COMBO_PHY1_P2_BASE + 0x62)
#define REG_COMBO_PHY1_P2_31_H       (REG_COMBO_PHY1_P2_BASE + 0x63)
#define REG_COMBO_PHY1_P2_32_L       (REG_COMBO_PHY1_P2_BASE + 0x64)
#define REG_COMBO_PHY1_P2_32_H       (REG_COMBO_PHY1_P2_BASE + 0x65)
#define REG_COMBO_PHY1_P2_33_L       (REG_COMBO_PHY1_P2_BASE + 0x66)
#define REG_COMBO_PHY1_P2_33_H       (REG_COMBO_PHY1_P2_BASE + 0x67)
#define REG_COMBO_PHY1_P2_34_L       (REG_COMBO_PHY1_P2_BASE + 0x68)
#define REG_COMBO_PHY1_P2_34_H       (REG_COMBO_PHY1_P2_BASE + 0x69)
#define REG_COMBO_PHY1_P2_35_L       (REG_COMBO_PHY1_P2_BASE + 0x6A)
#define REG_COMBO_PHY1_P2_35_H       (REG_COMBO_PHY1_P2_BASE + 0x6B)
#define REG_COMBO_PHY1_P2_36_L       (REG_COMBO_PHY1_P2_BASE + 0x6C)
#define REG_COMBO_PHY1_P2_36_H       (REG_COMBO_PHY1_P2_BASE + 0x6D)
#define REG_COMBO_PHY1_P2_37_L       (REG_COMBO_PHY1_P2_BASE + 0x6E)
#define REG_COMBO_PHY1_P2_37_H       (REG_COMBO_PHY1_P2_BASE + 0x6F)
#define REG_COMBO_PHY1_P2_38_L       (REG_COMBO_PHY1_P2_BASE + 0x70)
#define REG_COMBO_PHY1_P2_38_H       (REG_COMBO_PHY1_P2_BASE + 0x71)
#define REG_COMBO_PHY1_P2_39_L       (REG_COMBO_PHY1_P2_BASE + 0x72)
#define REG_COMBO_PHY1_P2_39_H       (REG_COMBO_PHY1_P2_BASE + 0x73)
#define REG_COMBO_PHY1_P2_3A_L       (REG_COMBO_PHY1_P2_BASE + 0x74)
#define REG_COMBO_PHY1_P2_3A_H       (REG_COMBO_PHY1_P2_BASE + 0x75)
#define REG_COMBO_PHY1_P2_3B_L       (REG_COMBO_PHY1_P2_BASE + 0x76)
#define REG_COMBO_PHY1_P2_3B_H       (REG_COMBO_PHY1_P2_BASE + 0x77)
#define REG_COMBO_PHY1_P2_3C_L       (REG_COMBO_PHY1_P2_BASE + 0x78)
#define REG_COMBO_PHY1_P2_3C_H       (REG_COMBO_PHY1_P2_BASE + 0x79)
#define REG_COMBO_PHY1_P2_3D_L       (REG_COMBO_PHY1_P2_BASE + 0x7A)
#define REG_COMBO_PHY1_P2_3D_H       (REG_COMBO_PHY1_P2_BASE + 0x7B)
#define REG_COMBO_PHY1_P2_3E_L       (REG_COMBO_PHY1_P2_BASE + 0x7C)
#define REG_COMBO_PHY1_P2_3E_H       (REG_COMBO_PHY1_P2_BASE + 0x7D)
#define REG_COMBO_PHY1_P2_3F_L       (REG_COMBO_PHY1_P2_BASE + 0x7E)
#define REG_COMBO_PHY1_P2_3F_H       (REG_COMBO_PHY1_P2_BASE + 0x7F)
#define REG_COMBO_PHY1_P2_40_L       (REG_COMBO_PHY1_P2_BASE + 0x80)
#define REG_COMBO_PHY1_P2_40_H       (REG_COMBO_PHY1_P2_BASE + 0x81)
#define REG_COMBO_PHY1_P2_41_L       (REG_COMBO_PHY1_P2_BASE + 0x82)
#define REG_COMBO_PHY1_P2_41_H       (REG_COMBO_PHY1_P2_BASE + 0x83)
#define REG_COMBO_PHY1_P2_42_L       (REG_COMBO_PHY1_P2_BASE + 0x84)
#define REG_COMBO_PHY1_P2_42_H       (REG_COMBO_PHY1_P2_BASE + 0x85)
#define REG_COMBO_PHY1_P2_43_L       (REG_COMBO_PHY1_P2_BASE + 0x86)
#define REG_COMBO_PHY1_P2_43_H       (REG_COMBO_PHY1_P2_BASE + 0x87)
#define REG_COMBO_PHY1_P2_44_L       (REG_COMBO_PHY1_P2_BASE + 0x88)
#define REG_COMBO_PHY1_P2_44_H       (REG_COMBO_PHY1_P2_BASE + 0x89)
#define REG_COMBO_PHY1_P2_45_L       (REG_COMBO_PHY1_P2_BASE + 0x8A)
#define REG_COMBO_PHY1_P2_45_H       (REG_COMBO_PHY1_P2_BASE + 0x8B)
#define REG_COMBO_PHY1_P2_46_L       (REG_COMBO_PHY1_P2_BASE + 0x8C)
#define REG_COMBO_PHY1_P2_46_H       (REG_COMBO_PHY1_P2_BASE + 0x8D)
#define REG_COMBO_PHY1_P2_47_L       (REG_COMBO_PHY1_P2_BASE + 0x8E)
#define REG_COMBO_PHY1_P2_47_H       (REG_COMBO_PHY1_P2_BASE + 0x8F)
#define REG_COMBO_PHY1_P2_48_L       (REG_COMBO_PHY1_P2_BASE + 0x90)
#define REG_COMBO_PHY1_P2_48_H       (REG_COMBO_PHY1_P2_BASE + 0x91)
#define REG_COMBO_PHY1_P2_49_L       (REG_COMBO_PHY1_P2_BASE + 0x92)
#define REG_COMBO_PHY1_P2_49_H       (REG_COMBO_PHY1_P2_BASE + 0x93)
#define REG_COMBO_PHY1_P2_4A_L       (REG_COMBO_PHY1_P2_BASE + 0x94)
#define REG_COMBO_PHY1_P2_4A_H       (REG_COMBO_PHY1_P2_BASE + 0x95)
#define REG_COMBO_PHY1_P2_4B_L       (REG_COMBO_PHY1_P2_BASE + 0x96)
#define REG_COMBO_PHY1_P2_4B_H       (REG_COMBO_PHY1_P2_BASE + 0x97)
#define REG_COMBO_PHY1_P2_4C_L       (REG_COMBO_PHY1_P2_BASE + 0x98)
#define REG_COMBO_PHY1_P2_4C_H       (REG_COMBO_PHY1_P2_BASE + 0x99)
#define REG_COMBO_PHY1_P2_4D_L       (REG_COMBO_PHY1_P2_BASE + 0x9A)
#define REG_COMBO_PHY1_P2_4D_H       (REG_COMBO_PHY1_P2_BASE + 0x9B)
#define REG_COMBO_PHY1_P2_4E_L       (REG_COMBO_PHY1_P2_BASE + 0x9C)
#define REG_COMBO_PHY1_P2_4E_H       (REG_COMBO_PHY1_P2_BASE + 0x9D)
#define REG_COMBO_PHY1_P2_4F_L       (REG_COMBO_PHY1_P2_BASE + 0x9E)
#define REG_COMBO_PHY1_P2_4F_H       (REG_COMBO_PHY1_P2_BASE + 0x9F)
#define REG_COMBO_PHY1_P2_50_L       (REG_COMBO_PHY1_P2_BASE + 0xA0)
#define REG_COMBO_PHY1_P2_50_H       (REG_COMBO_PHY1_P2_BASE + 0xA1)
#define REG_COMBO_PHY1_P2_51_L       (REG_COMBO_PHY1_P2_BASE + 0xA2)
#define REG_COMBO_PHY1_P2_51_H       (REG_COMBO_PHY1_P2_BASE + 0xA3)
#define REG_COMBO_PHY1_P2_52_L       (REG_COMBO_PHY1_P2_BASE + 0xA4)
#define REG_COMBO_PHY1_P2_52_H       (REG_COMBO_PHY1_P2_BASE + 0xA5)
#define REG_COMBO_PHY1_P2_53_L       (REG_COMBO_PHY1_P2_BASE + 0xA6)
#define REG_COMBO_PHY1_P2_53_H       (REG_COMBO_PHY1_P2_BASE + 0xA7)
#define REG_COMBO_PHY1_P2_54_L       (REG_COMBO_PHY1_P2_BASE + 0xA8)
#define REG_COMBO_PHY1_P2_54_H       (REG_COMBO_PHY1_P2_BASE + 0xA9)
#define REG_COMBO_PHY1_P2_55_L       (REG_COMBO_PHY1_P2_BASE + 0xAA)
#define REG_COMBO_PHY1_P2_55_H       (REG_COMBO_PHY1_P2_BASE + 0xAB)
#define REG_COMBO_PHY1_P2_56_L       (REG_COMBO_PHY1_P2_BASE + 0xAC)
#define REG_COMBO_PHY1_P2_56_H       (REG_COMBO_PHY1_P2_BASE + 0xAD)
#define REG_COMBO_PHY1_P2_57_L       (REG_COMBO_PHY1_P2_BASE + 0xAE)
#define REG_COMBO_PHY1_P2_57_H       (REG_COMBO_PHY1_P2_BASE + 0xAF)
#define REG_COMBO_PHY1_P2_58_L       (REG_COMBO_PHY1_P2_BASE + 0xB0)
#define REG_COMBO_PHY1_P2_58_H       (REG_COMBO_PHY1_P2_BASE + 0xB1)
#define REG_COMBO_PHY1_P2_59_L       (REG_COMBO_PHY1_P2_BASE + 0xB2)
#define REG_COMBO_PHY1_P2_59_H       (REG_COMBO_PHY1_P2_BASE + 0xB3)
#define REG_COMBO_PHY1_P2_5A_L       (REG_COMBO_PHY1_P2_BASE + 0xB4)
#define REG_COMBO_PHY1_P2_5A_H       (REG_COMBO_PHY1_P2_BASE + 0xB5)
#define REG_COMBO_PHY1_P2_5B_L       (REG_COMBO_PHY1_P2_BASE + 0xB6)
#define REG_COMBO_PHY1_P2_5B_H       (REG_COMBO_PHY1_P2_BASE + 0xB7)
#define REG_COMBO_PHY1_P2_5C_L       (REG_COMBO_PHY1_P2_BASE + 0xB8)
#define REG_COMBO_PHY1_P2_5C_H       (REG_COMBO_PHY1_P2_BASE + 0xB9)
#define REG_COMBO_PHY1_P2_5D_L       (REG_COMBO_PHY1_P2_BASE + 0xBA)
#define REG_COMBO_PHY1_P2_5D_H       (REG_COMBO_PHY1_P2_BASE + 0xBB)
#define REG_COMBO_PHY1_P2_5E_L       (REG_COMBO_PHY1_P2_BASE + 0xBC)
#define REG_COMBO_PHY1_P2_5E_H       (REG_COMBO_PHY1_P2_BASE + 0xBD)
#define REG_COMBO_PHY1_P2_5F_L       (REG_COMBO_PHY1_P2_BASE + 0xBE)
#define REG_COMBO_PHY1_P2_5F_H       (REG_COMBO_PHY1_P2_BASE + 0xBF)
#define REG_COMBO_PHY1_P2_60_L       (REG_COMBO_PHY1_P2_BASE + 0xC0)
#define REG_COMBO_PHY1_P2_60_H       (REG_COMBO_PHY1_P2_BASE + 0xC1)
#define REG_COMBO_PHY1_P2_61_L       (REG_COMBO_PHY1_P2_BASE + 0xC2)
#define REG_COMBO_PHY1_P2_61_H       (REG_COMBO_PHY1_P2_BASE + 0xC3)
#define REG_COMBO_PHY1_P2_62_L       (REG_COMBO_PHY1_P2_BASE + 0xC4)
#define REG_COMBO_PHY1_P2_62_H       (REG_COMBO_PHY1_P2_BASE + 0xC5)
#define REG_COMBO_PHY1_P2_63_L       (REG_COMBO_PHY1_P2_BASE + 0xC6)
#define REG_COMBO_PHY1_P2_63_H       (REG_COMBO_PHY1_P2_BASE + 0xC7)
#define REG_COMBO_PHY1_P2_64_L       (REG_COMBO_PHY1_P2_BASE + 0xC8)
#define REG_COMBO_PHY1_P2_64_H       (REG_COMBO_PHY1_P2_BASE + 0xC9)
#define REG_COMBO_PHY1_P2_65_L       (REG_COMBO_PHY1_P2_BASE + 0xCA)
#define REG_COMBO_PHY1_P2_65_H       (REG_COMBO_PHY1_P2_BASE + 0xCB)
#define REG_COMBO_PHY1_P2_66_L       (REG_COMBO_PHY1_P2_BASE + 0xCC)
#define REG_COMBO_PHY1_P2_66_H       (REG_COMBO_PHY1_P2_BASE + 0xCD)
#define REG_COMBO_PHY1_P2_67_L       (REG_COMBO_PHY1_P2_BASE + 0xCE)
#define REG_COMBO_PHY1_P2_67_H       (REG_COMBO_PHY1_P2_BASE + 0xCF)
#define REG_COMBO_PHY1_P2_68_L       (REG_COMBO_PHY1_P2_BASE + 0xD0)
#define REG_COMBO_PHY1_P2_68_H       (REG_COMBO_PHY1_P2_BASE + 0xD1)
#define REG_COMBO_PHY1_P2_69_L       (REG_COMBO_PHY1_P2_BASE + 0xD2)
#define REG_COMBO_PHY1_P2_69_H       (REG_COMBO_PHY1_P2_BASE + 0xD3)
#define REG_COMBO_PHY1_P2_6A_L       (REG_COMBO_PHY1_P2_BASE + 0xD4)
#define REG_COMBO_PHY1_P2_6A_H       (REG_COMBO_PHY1_P2_BASE + 0xD5)
#define REG_COMBO_PHY1_P2_6B_L       (REG_COMBO_PHY1_P2_BASE + 0xD6)
#define REG_COMBO_PHY1_P2_6B_H       (REG_COMBO_PHY1_P2_BASE + 0xD7)
#define REG_COMBO_PHY1_P2_6C_L       (REG_COMBO_PHY1_P2_BASE + 0xD8)
#define REG_COMBO_PHY1_P2_6C_H       (REG_COMBO_PHY1_P2_BASE + 0xD9)
#define REG_COMBO_PHY1_P2_6D_L       (REG_COMBO_PHY1_P2_BASE + 0xDA)
#define REG_COMBO_PHY1_P2_6D_H       (REG_COMBO_PHY1_P2_BASE + 0xDB)
#define REG_COMBO_PHY1_P2_6E_L       (REG_COMBO_PHY1_P2_BASE + 0xDC)
#define REG_COMBO_PHY1_P2_6E_H       (REG_COMBO_PHY1_P2_BASE + 0xDD)
#define REG_COMBO_PHY1_P2_6F_L       (REG_COMBO_PHY1_P2_BASE + 0xDE)
#define REG_COMBO_PHY1_P2_6F_H       (REG_COMBO_PHY1_P2_BASE + 0xDF)
#define REG_COMBO_PHY1_P2_70_L       (REG_COMBO_PHY1_P2_BASE + 0xE0)
#define REG_COMBO_PHY1_P2_70_H       (REG_COMBO_PHY1_P2_BASE + 0xE1)
#define REG_COMBO_PHY1_P2_71_L       (REG_COMBO_PHY1_P2_BASE + 0xE2)
#define REG_COMBO_PHY1_P2_71_H       (REG_COMBO_PHY1_P2_BASE + 0xE3)
#define REG_COMBO_PHY1_P2_72_L       (REG_COMBO_PHY1_P2_BASE + 0xE4)
#define REG_COMBO_PHY1_P2_72_H       (REG_COMBO_PHY1_P2_BASE + 0xE5)
#define REG_COMBO_PHY1_P2_73_L       (REG_COMBO_PHY1_P2_BASE + 0xE6)
#define REG_COMBO_PHY1_P2_73_H       (REG_COMBO_PHY1_P2_BASE + 0xE7)
#define REG_COMBO_PHY1_P2_74_L       (REG_COMBO_PHY1_P2_BASE + 0xE8)
#define REG_COMBO_PHY1_P2_74_H       (REG_COMBO_PHY1_P2_BASE + 0xE9)
#define REG_COMBO_PHY1_P2_75_L       (REG_COMBO_PHY1_P2_BASE + 0xEA)
#define REG_COMBO_PHY1_P2_75_H       (REG_COMBO_PHY1_P2_BASE + 0xEB)
#define REG_COMBO_PHY1_P2_76_L       (REG_COMBO_PHY1_P2_BASE + 0xEC)
#define REG_COMBO_PHY1_P2_76_H       (REG_COMBO_PHY1_P2_BASE + 0xED)
#define REG_COMBO_PHY1_P2_77_L       (REG_COMBO_PHY1_P2_BASE + 0xEE)
#define REG_COMBO_PHY1_P2_77_H       (REG_COMBO_PHY1_P2_BASE + 0xEF)
#define REG_COMBO_PHY1_P2_78_L       (REG_COMBO_PHY1_P2_BASE + 0xF0)
#define REG_COMBO_PHY1_P2_78_H       (REG_COMBO_PHY1_P2_BASE + 0xF1)
#define REG_COMBO_PHY1_P2_79_L       (REG_COMBO_PHY1_P2_BASE + 0xF2)
#define REG_COMBO_PHY1_P2_79_H       (REG_COMBO_PHY1_P2_BASE + 0xF3)
#define REG_COMBO_PHY1_P2_7A_L       (REG_COMBO_PHY1_P2_BASE + 0xF4)
#define REG_COMBO_PHY1_P2_7A_H       (REG_COMBO_PHY1_P2_BASE + 0xF5)
#define REG_COMBO_PHY1_P2_7B_L       (REG_COMBO_PHY1_P2_BASE + 0xF6)
#define REG_COMBO_PHY1_P2_7B_H       (REG_COMBO_PHY1_P2_BASE + 0xF7)
#define REG_COMBO_PHY1_P2_7C_L       (REG_COMBO_PHY1_P2_BASE + 0xF8)
#define REG_COMBO_PHY1_P2_7C_H       (REG_COMBO_PHY1_P2_BASE + 0xF9)
#define REG_COMBO_PHY1_P2_7D_L       (REG_COMBO_PHY1_P2_BASE + 0xFA)
#define REG_COMBO_PHY1_P2_7D_H       (REG_COMBO_PHY1_P2_BASE + 0xFB)
#define REG_COMBO_PHY1_P2_7E_L       (REG_COMBO_PHY1_P2_BASE + 0xFC)
#define REG_COMBO_PHY1_P2_7E_H       (REG_COMBO_PHY1_P2_BASE + 0xFD)
#define REG_COMBO_PHY1_P2_7F_L       (REG_COMBO_PHY1_P2_BASE + 0xFE)
#define REG_COMBO_PHY1_P2_7F_H       (REG_COMBO_PHY1_P2_BASE + 0xFF)

// COMBO_PHY0_P3
#define REG_COMBO_PHY0_P3_00_L       (REG_COMBO_PHY0_P3_BASE + 0x00)
#define REG_COMBO_PHY0_P3_00_H       (REG_COMBO_PHY0_P3_BASE + 0x01)
#define REG_COMBO_PHY0_P3_01_L       (REG_COMBO_PHY0_P3_BASE + 0x02)
#define REG_COMBO_PHY0_P3_01_H       (REG_COMBO_PHY0_P3_BASE + 0x03)
#define REG_COMBO_PHY0_P3_02_L       (REG_COMBO_PHY0_P3_BASE + 0x04)
#define REG_COMBO_PHY0_P3_02_H       (REG_COMBO_PHY0_P3_BASE + 0x05)
#define REG_COMBO_PHY0_P3_03_L       (REG_COMBO_PHY0_P3_BASE + 0x06)
#define REG_COMBO_PHY0_P3_03_H       (REG_COMBO_PHY0_P3_BASE + 0x07)
#define REG_COMBO_PHY0_P3_04_L       (REG_COMBO_PHY0_P3_BASE + 0x08)
#define REG_COMBO_PHY0_P3_04_H       (REG_COMBO_PHY0_P3_BASE + 0x09)
#define REG_COMBO_PHY0_P3_05_L       (REG_COMBO_PHY0_P3_BASE + 0x0A)
#define REG_COMBO_PHY0_P3_05_H       (REG_COMBO_PHY0_P3_BASE + 0x0B)
#define REG_COMBO_PHY0_P3_06_L       (REG_COMBO_PHY0_P3_BASE + 0x0C)
#define REG_COMBO_PHY0_P3_06_H       (REG_COMBO_PHY0_P3_BASE + 0x0D)
#define REG_COMBO_PHY0_P3_07_L       (REG_COMBO_PHY0_P3_BASE + 0x0E)
#define REG_COMBO_PHY0_P3_07_H       (REG_COMBO_PHY0_P3_BASE + 0x0F)
#define REG_COMBO_PHY0_P3_08_L       (REG_COMBO_PHY0_P3_BASE + 0x10)
#define REG_COMBO_PHY0_P3_08_H       (REG_COMBO_PHY0_P3_BASE + 0x11)
#define REG_COMBO_PHY0_P3_09_L       (REG_COMBO_PHY0_P3_BASE + 0x12)
#define REG_COMBO_PHY0_P3_09_H       (REG_COMBO_PHY0_P3_BASE + 0x13)
#define REG_COMBO_PHY0_P3_0A_L       (REG_COMBO_PHY0_P3_BASE + 0x14)
#define REG_COMBO_PHY0_P3_0A_H       (REG_COMBO_PHY0_P3_BASE + 0x15)
#define REG_COMBO_PHY0_P3_0B_L       (REG_COMBO_PHY0_P3_BASE + 0x16)
#define REG_COMBO_PHY0_P3_0B_H       (REG_COMBO_PHY0_P3_BASE + 0x17)
#define REG_COMBO_PHY0_P3_0C_L       (REG_COMBO_PHY0_P3_BASE + 0x18)
#define REG_COMBO_PHY0_P3_0C_H       (REG_COMBO_PHY0_P3_BASE + 0x19)
#define REG_COMBO_PHY0_P3_0D_L       (REG_COMBO_PHY0_P3_BASE + 0x1A)
#define REG_COMBO_PHY0_P3_0D_H       (REG_COMBO_PHY0_P3_BASE + 0x1B)
#define REG_COMBO_PHY0_P3_0E_L       (REG_COMBO_PHY0_P3_BASE + 0x1C)
#define REG_COMBO_PHY0_P3_0E_H       (REG_COMBO_PHY0_P3_BASE + 0x1D)
#define REG_COMBO_PHY0_P3_0F_L       (REG_COMBO_PHY0_P3_BASE + 0x1E)
#define REG_COMBO_PHY0_P3_0F_H       (REG_COMBO_PHY0_P3_BASE + 0x1F)
#define REG_COMBO_PHY0_P3_10_L       (REG_COMBO_PHY0_P3_BASE + 0x20)
#define REG_COMBO_PHY0_P3_10_H       (REG_COMBO_PHY0_P3_BASE + 0x21)
#define REG_COMBO_PHY0_P3_11_L       (REG_COMBO_PHY0_P3_BASE + 0x22)
#define REG_COMBO_PHY0_P3_11_H       (REG_COMBO_PHY0_P3_BASE + 0x23)
#define REG_COMBO_PHY0_P3_12_L       (REG_COMBO_PHY0_P3_BASE + 0x24)
#define REG_COMBO_PHY0_P3_12_H       (REG_COMBO_PHY0_P3_BASE + 0x25)
#define REG_COMBO_PHY0_P3_13_L       (REG_COMBO_PHY0_P3_BASE + 0x26)
#define REG_COMBO_PHY0_P3_13_H       (REG_COMBO_PHY0_P3_BASE + 0x27)
#define REG_COMBO_PHY0_P3_14_L       (REG_COMBO_PHY0_P3_BASE + 0x28)
#define REG_COMBO_PHY0_P3_14_H       (REG_COMBO_PHY0_P3_BASE + 0x29)
#define REG_COMBO_PHY0_P3_15_L       (REG_COMBO_PHY0_P3_BASE + 0x2A)
#define REG_COMBO_PHY0_P3_15_H       (REG_COMBO_PHY0_P3_BASE + 0x2B)
#define REG_COMBO_PHY0_P3_16_L       (REG_COMBO_PHY0_P3_BASE + 0x2C)
#define REG_COMBO_PHY0_P3_16_H       (REG_COMBO_PHY0_P3_BASE + 0x2D)
#define REG_COMBO_PHY0_P3_17_L       (REG_COMBO_PHY0_P3_BASE + 0x2E)
#define REG_COMBO_PHY0_P3_17_H       (REG_COMBO_PHY0_P3_BASE + 0x2F)
#define REG_COMBO_PHY0_P3_18_L       (REG_COMBO_PHY0_P3_BASE + 0x30)
#define REG_COMBO_PHY0_P3_18_H       (REG_COMBO_PHY0_P3_BASE + 0x31)
#define REG_COMBO_PHY0_P3_19_L       (REG_COMBO_PHY0_P3_BASE + 0x32)
#define REG_COMBO_PHY0_P3_19_H       (REG_COMBO_PHY0_P3_BASE + 0x33)
#define REG_COMBO_PHY0_P3_1A_L       (REG_COMBO_PHY0_P3_BASE + 0x34)
#define REG_COMBO_PHY0_P3_1A_H       (REG_COMBO_PHY0_P3_BASE + 0x35)
#define REG_COMBO_PHY0_P3_1B_L       (REG_COMBO_PHY0_P3_BASE + 0x36)
#define REG_COMBO_PHY0_P3_1B_H       (REG_COMBO_PHY0_P3_BASE + 0x37)
#define REG_COMBO_PHY0_P3_1C_L       (REG_COMBO_PHY0_P3_BASE + 0x38)
#define REG_COMBO_PHY0_P3_1C_H       (REG_COMBO_PHY0_P3_BASE + 0x39)
#define REG_COMBO_PHY0_P3_1D_L       (REG_COMBO_PHY0_P3_BASE + 0x3A)
#define REG_COMBO_PHY0_P3_1D_H       (REG_COMBO_PHY0_P3_BASE + 0x3B)
#define REG_COMBO_PHY0_P3_1E_L       (REG_COMBO_PHY0_P3_BASE + 0x3C)
#define REG_COMBO_PHY0_P3_1E_H       (REG_COMBO_PHY0_P3_BASE + 0x3D)
#define REG_COMBO_PHY0_P3_1F_L       (REG_COMBO_PHY0_P3_BASE + 0x3E)
#define REG_COMBO_PHY0_P3_1F_H       (REG_COMBO_PHY0_P3_BASE + 0x3F)
#define REG_COMBO_PHY0_P3_20_L       (REG_COMBO_PHY0_P3_BASE + 0x40)
#define REG_COMBO_PHY0_P3_20_H       (REG_COMBO_PHY0_P3_BASE + 0x41)
#define REG_COMBO_PHY0_P3_21_L       (REG_COMBO_PHY0_P3_BASE + 0x42)
#define REG_COMBO_PHY0_P3_21_H       (REG_COMBO_PHY0_P3_BASE + 0x43)
#define REG_COMBO_PHY0_P3_22_L       (REG_COMBO_PHY0_P3_BASE + 0x44)
#define REG_COMBO_PHY0_P3_22_H       (REG_COMBO_PHY0_P3_BASE + 0x45)
#define REG_COMBO_PHY0_P3_23_L       (REG_COMBO_PHY0_P3_BASE + 0x46)
#define REG_COMBO_PHY0_P3_23_H       (REG_COMBO_PHY0_P3_BASE + 0x47)
#define REG_COMBO_PHY0_P3_24_L       (REG_COMBO_PHY0_P3_BASE + 0x48)
#define REG_COMBO_PHY0_P3_24_H       (REG_COMBO_PHY0_P3_BASE + 0x49)
#define REG_COMBO_PHY0_P3_25_L       (REG_COMBO_PHY0_P3_BASE + 0x4A)
#define REG_COMBO_PHY0_P3_25_H       (REG_COMBO_PHY0_P3_BASE + 0x4B)
#define REG_COMBO_PHY0_P3_26_L       (REG_COMBO_PHY0_P3_BASE + 0x4C)
#define REG_COMBO_PHY0_P3_26_H       (REG_COMBO_PHY0_P3_BASE + 0x4D)
#define REG_COMBO_PHY0_P3_27_L       (REG_COMBO_PHY0_P3_BASE + 0x4E)
#define REG_COMBO_PHY0_P3_27_H       (REG_COMBO_PHY0_P3_BASE + 0x4F)
#define REG_COMBO_PHY0_P3_28_L       (REG_COMBO_PHY0_P3_BASE + 0x50)
#define REG_COMBO_PHY0_P3_28_H       (REG_COMBO_PHY0_P3_BASE + 0x51)
#define REG_COMBO_PHY0_P3_29_L       (REG_COMBO_PHY0_P3_BASE + 0x52)
#define REG_COMBO_PHY0_P3_29_H       (REG_COMBO_PHY0_P3_BASE + 0x53)
#define REG_COMBO_PHY0_P3_2A_L       (REG_COMBO_PHY0_P3_BASE + 0x54)
#define REG_COMBO_PHY0_P3_2A_H       (REG_COMBO_PHY0_P3_BASE + 0x55)
#define REG_COMBO_PHY0_P3_2B_L       (REG_COMBO_PHY0_P3_BASE + 0x56)
#define REG_COMBO_PHY0_P3_2B_H       (REG_COMBO_PHY0_P3_BASE + 0x57)
#define REG_COMBO_PHY0_P3_2C_L       (REG_COMBO_PHY0_P3_BASE + 0x58)
#define REG_COMBO_PHY0_P3_2C_H       (REG_COMBO_PHY0_P3_BASE + 0x59)
#define REG_COMBO_PHY0_P3_2D_L       (REG_COMBO_PHY0_P3_BASE + 0x5A)
#define REG_COMBO_PHY0_P3_2D_H       (REG_COMBO_PHY0_P3_BASE + 0x5B)
#define REG_COMBO_PHY0_P3_2E_L       (REG_COMBO_PHY0_P3_BASE + 0x5C)
#define REG_COMBO_PHY0_P3_2E_H       (REG_COMBO_PHY0_P3_BASE + 0x5D)
#define REG_COMBO_PHY0_P3_2F_L       (REG_COMBO_PHY0_P3_BASE + 0x5E)
#define REG_COMBO_PHY0_P3_2F_H       (REG_COMBO_PHY0_P3_BASE + 0x5F)
#define REG_COMBO_PHY0_P3_30_L       (REG_COMBO_PHY0_P3_BASE + 0x60)
#define REG_COMBO_PHY0_P3_30_H       (REG_COMBO_PHY0_P3_BASE + 0x61)
#define REG_COMBO_PHY0_P3_31_L       (REG_COMBO_PHY0_P3_BASE + 0x62)
#define REG_COMBO_PHY0_P3_31_H       (REG_COMBO_PHY0_P3_BASE + 0x63)
#define REG_COMBO_PHY0_P3_32_L       (REG_COMBO_PHY0_P3_BASE + 0x64)
#define REG_COMBO_PHY0_P3_32_H       (REG_COMBO_PHY0_P3_BASE + 0x65)
#define REG_COMBO_PHY0_P3_33_L       (REG_COMBO_PHY0_P3_BASE + 0x66)
#define REG_COMBO_PHY0_P3_33_H       (REG_COMBO_PHY0_P3_BASE + 0x67)
#define REG_COMBO_PHY0_P3_34_L       (REG_COMBO_PHY0_P3_BASE + 0x68)
#define REG_COMBO_PHY0_P3_34_H       (REG_COMBO_PHY0_P3_BASE + 0x69)
#define REG_COMBO_PHY0_P3_35_L       (REG_COMBO_PHY0_P3_BASE + 0x6A)
#define REG_COMBO_PHY0_P3_35_H       (REG_COMBO_PHY0_P3_BASE + 0x6B)
#define REG_COMBO_PHY0_P3_36_L       (REG_COMBO_PHY0_P3_BASE + 0x6C)
#define REG_COMBO_PHY0_P3_36_H       (REG_COMBO_PHY0_P3_BASE + 0x6D)
#define REG_COMBO_PHY0_P3_37_L       (REG_COMBO_PHY0_P3_BASE + 0x6E)
#define REG_COMBO_PHY0_P3_37_H       (REG_COMBO_PHY0_P3_BASE + 0x6F)
#define REG_COMBO_PHY0_P3_38_L       (REG_COMBO_PHY0_P3_BASE + 0x70)
#define REG_COMBO_PHY0_P3_38_H       (REG_COMBO_PHY0_P3_BASE + 0x71)
#define REG_COMBO_PHY0_P3_39_L       (REG_COMBO_PHY0_P3_BASE + 0x72)
#define REG_COMBO_PHY0_P3_39_H       (REG_COMBO_PHY0_P3_BASE + 0x73)
#define REG_COMBO_PHY0_P3_3A_L       (REG_COMBO_PHY0_P3_BASE + 0x74)
#define REG_COMBO_PHY0_P3_3A_H       (REG_COMBO_PHY0_P3_BASE + 0x75)
#define REG_COMBO_PHY0_P3_3B_L       (REG_COMBO_PHY0_P3_BASE + 0x76)
#define REG_COMBO_PHY0_P3_3B_H       (REG_COMBO_PHY0_P3_BASE + 0x77)
#define REG_COMBO_PHY0_P3_3C_L       (REG_COMBO_PHY0_P3_BASE + 0x78)
#define REG_COMBO_PHY0_P3_3C_H       (REG_COMBO_PHY0_P3_BASE + 0x79)
#define REG_COMBO_PHY0_P3_3D_L       (REG_COMBO_PHY0_P3_BASE + 0x7A)
#define REG_COMBO_PHY0_P3_3D_H       (REG_COMBO_PHY0_P3_BASE + 0x7B)
#define REG_COMBO_PHY0_P3_3E_L       (REG_COMBO_PHY0_P3_BASE + 0x7C)
#define REG_COMBO_PHY0_P3_3E_H       (REG_COMBO_PHY0_P3_BASE + 0x7D)
#define REG_COMBO_PHY0_P3_3F_L       (REG_COMBO_PHY0_P3_BASE + 0x7E)
#define REG_COMBO_PHY0_P3_3F_H       (REG_COMBO_PHY0_P3_BASE + 0x7F)
#define REG_COMBO_PHY0_P3_40_L       (REG_COMBO_PHY0_P3_BASE + 0x80)
#define REG_COMBO_PHY0_P3_40_H       (REG_COMBO_PHY0_P3_BASE + 0x81)
#define REG_COMBO_PHY0_P3_41_L       (REG_COMBO_PHY0_P3_BASE + 0x82)
#define REG_COMBO_PHY0_P3_41_H       (REG_COMBO_PHY0_P3_BASE + 0x83)
#define REG_COMBO_PHY0_P3_42_L       (REG_COMBO_PHY0_P3_BASE + 0x84)
#define REG_COMBO_PHY0_P3_42_H       (REG_COMBO_PHY0_P3_BASE + 0x85)
#define REG_COMBO_PHY0_P3_43_L       (REG_COMBO_PHY0_P3_BASE + 0x86)
#define REG_COMBO_PHY0_P3_43_H       (REG_COMBO_PHY0_P3_BASE + 0x87)
#define REG_COMBO_PHY0_P3_44_L       (REG_COMBO_PHY0_P3_BASE + 0x88)
#define REG_COMBO_PHY0_P3_44_H       (REG_COMBO_PHY0_P3_BASE + 0x89)
#define REG_COMBO_PHY0_P3_45_L       (REG_COMBO_PHY0_P3_BASE + 0x8A)
#define REG_COMBO_PHY0_P3_45_H       (REG_COMBO_PHY0_P3_BASE + 0x8B)
#define REG_COMBO_PHY0_P3_46_L       (REG_COMBO_PHY0_P3_BASE + 0x8C)
#define REG_COMBO_PHY0_P3_46_H       (REG_COMBO_PHY0_P3_BASE + 0x8D)
#define REG_COMBO_PHY0_P3_47_L       (REG_COMBO_PHY0_P3_BASE + 0x8E)
#define REG_COMBO_PHY0_P3_47_H       (REG_COMBO_PHY0_P3_BASE + 0x8F)
#define REG_COMBO_PHY0_P3_48_L       (REG_COMBO_PHY0_P3_BASE + 0x90)
#define REG_COMBO_PHY0_P3_48_H       (REG_COMBO_PHY0_P3_BASE + 0x91)
#define REG_COMBO_PHY0_P3_49_L       (REG_COMBO_PHY0_P3_BASE + 0x92)
#define REG_COMBO_PHY0_P3_49_H       (REG_COMBO_PHY0_P3_BASE + 0x93)
#define REG_COMBO_PHY0_P3_4A_L       (REG_COMBO_PHY0_P3_BASE + 0x94)
#define REG_COMBO_PHY0_P3_4A_H       (REG_COMBO_PHY0_P3_BASE + 0x95)
#define REG_COMBO_PHY0_P3_4B_L       (REG_COMBO_PHY0_P3_BASE + 0x96)
#define REG_COMBO_PHY0_P3_4B_H       (REG_COMBO_PHY0_P3_BASE + 0x97)
#define REG_COMBO_PHY0_P3_4C_L       (REG_COMBO_PHY0_P3_BASE + 0x98)
#define REG_COMBO_PHY0_P3_4C_H       (REG_COMBO_PHY0_P3_BASE + 0x99)
#define REG_COMBO_PHY0_P3_4D_L       (REG_COMBO_PHY0_P3_BASE + 0x9A)
#define REG_COMBO_PHY0_P3_4D_H       (REG_COMBO_PHY0_P3_BASE + 0x9B)
#define REG_COMBO_PHY0_P3_4E_L       (REG_COMBO_PHY0_P3_BASE + 0x9C)
#define REG_COMBO_PHY0_P3_4E_H       (REG_COMBO_PHY0_P3_BASE + 0x9D)
#define REG_COMBO_PHY0_P3_4F_L       (REG_COMBO_PHY0_P3_BASE + 0x9E)
#define REG_COMBO_PHY0_P3_4F_H       (REG_COMBO_PHY0_P3_BASE + 0x9F)
#define REG_COMBO_PHY0_P3_50_L       (REG_COMBO_PHY0_P3_BASE + 0xA0)
#define REG_COMBO_PHY0_P3_50_H       (REG_COMBO_PHY0_P3_BASE + 0xA1)
#define REG_COMBO_PHY0_P3_51_L       (REG_COMBO_PHY0_P3_BASE + 0xA2)
#define REG_COMBO_PHY0_P3_51_H       (REG_COMBO_PHY0_P3_BASE + 0xA3)
#define REG_COMBO_PHY0_P3_52_L       (REG_COMBO_PHY0_P3_BASE + 0xA4)
#define REG_COMBO_PHY0_P3_52_H       (REG_COMBO_PHY0_P3_BASE + 0xA5)
#define REG_COMBO_PHY0_P3_53_L       (REG_COMBO_PHY0_P3_BASE + 0xA6)
#define REG_COMBO_PHY0_P3_53_H       (REG_COMBO_PHY0_P3_BASE + 0xA7)
#define REG_COMBO_PHY0_P3_54_L       (REG_COMBO_PHY0_P3_BASE + 0xA8)
#define REG_COMBO_PHY0_P3_54_H       (REG_COMBO_PHY0_P3_BASE + 0xA9)
#define REG_COMBO_PHY0_P3_55_L       (REG_COMBO_PHY0_P3_BASE + 0xAA)
#define REG_COMBO_PHY0_P3_55_H       (REG_COMBO_PHY0_P3_BASE + 0xAB)
#define REG_COMBO_PHY0_P3_56_L       (REG_COMBO_PHY0_P3_BASE + 0xAC)
#define REG_COMBO_PHY0_P3_56_H       (REG_COMBO_PHY0_P3_BASE + 0xAD)
#define REG_COMBO_PHY0_P3_57_L       (REG_COMBO_PHY0_P3_BASE + 0xAE)
#define REG_COMBO_PHY0_P3_57_H       (REG_COMBO_PHY0_P3_BASE + 0xAF)
#define REG_COMBO_PHY0_P3_58_L       (REG_COMBO_PHY0_P3_BASE + 0xB0)
#define REG_COMBO_PHY0_P3_58_H       (REG_COMBO_PHY0_P3_BASE + 0xB1)
#define REG_COMBO_PHY0_P3_59_L       (REG_COMBO_PHY0_P3_BASE + 0xB2)
#define REG_COMBO_PHY0_P3_59_H       (REG_COMBO_PHY0_P3_BASE + 0xB3)
#define REG_COMBO_PHY0_P3_5A_L       (REG_COMBO_PHY0_P3_BASE + 0xB4)
#define REG_COMBO_PHY0_P3_5A_H       (REG_COMBO_PHY0_P3_BASE + 0xB5)
#define REG_COMBO_PHY0_P3_5B_L       (REG_COMBO_PHY0_P3_BASE + 0xB6)
#define REG_COMBO_PHY0_P3_5B_H       (REG_COMBO_PHY0_P3_BASE + 0xB7)
#define REG_COMBO_PHY0_P3_5C_L       (REG_COMBO_PHY0_P3_BASE + 0xB8)
#define REG_COMBO_PHY0_P3_5C_H       (REG_COMBO_PHY0_P3_BASE + 0xB9)
#define REG_COMBO_PHY0_P3_5D_L       (REG_COMBO_PHY0_P3_BASE + 0xBA)
#define REG_COMBO_PHY0_P3_5D_H       (REG_COMBO_PHY0_P3_BASE + 0xBB)
#define REG_COMBO_PHY0_P3_5E_L       (REG_COMBO_PHY0_P3_BASE + 0xBC)
#define REG_COMBO_PHY0_P3_5E_H       (REG_COMBO_PHY0_P3_BASE + 0xBD)
#define REG_COMBO_PHY0_P3_5F_L       (REG_COMBO_PHY0_P3_BASE + 0xBE)
#define REG_COMBO_PHY0_P3_5F_H       (REG_COMBO_PHY0_P3_BASE + 0xBF)
#define REG_COMBO_PHY0_P3_60_L       (REG_COMBO_PHY0_P3_BASE + 0xC0)
#define REG_COMBO_PHY0_P3_60_H       (REG_COMBO_PHY0_P3_BASE + 0xC1)
#define REG_COMBO_PHY0_P3_61_L       (REG_COMBO_PHY0_P3_BASE + 0xC2)
#define REG_COMBO_PHY0_P3_61_H       (REG_COMBO_PHY0_P3_BASE + 0xC3)
#define REG_COMBO_PHY0_P3_62_L       (REG_COMBO_PHY0_P3_BASE + 0xC4)
#define REG_COMBO_PHY0_P3_62_H       (REG_COMBO_PHY0_P3_BASE + 0xC5)
#define REG_COMBO_PHY0_P3_63_L       (REG_COMBO_PHY0_P3_BASE + 0xC6)
#define REG_COMBO_PHY0_P3_63_H       (REG_COMBO_PHY0_P3_BASE + 0xC7)
#define REG_COMBO_PHY0_P3_64_L       (REG_COMBO_PHY0_P3_BASE + 0xC8)
#define REG_COMBO_PHY0_P3_64_H       (REG_COMBO_PHY0_P3_BASE + 0xC9)
#define REG_COMBO_PHY0_P3_65_L       (REG_COMBO_PHY0_P3_BASE + 0xCA)
#define REG_COMBO_PHY0_P3_65_H       (REG_COMBO_PHY0_P3_BASE + 0xCB)
#define REG_COMBO_PHY0_P3_66_L       (REG_COMBO_PHY0_P3_BASE + 0xCC)
#define REG_COMBO_PHY0_P3_66_H       (REG_COMBO_PHY0_P3_BASE + 0xCD)
#define REG_COMBO_PHY0_P3_67_L       (REG_COMBO_PHY0_P3_BASE + 0xCE)
#define REG_COMBO_PHY0_P3_67_H       (REG_COMBO_PHY0_P3_BASE + 0xCF)
#define REG_COMBO_PHY0_P3_68_L       (REG_COMBO_PHY0_P3_BASE + 0xD0)
#define REG_COMBO_PHY0_P3_68_H       (REG_COMBO_PHY0_P3_BASE + 0xD1)
#define REG_COMBO_PHY0_P3_69_L       (REG_COMBO_PHY0_P3_BASE + 0xD2)
#define REG_COMBO_PHY0_P3_69_H       (REG_COMBO_PHY0_P3_BASE + 0xD3)
#define REG_COMBO_PHY0_P3_6A_L       (REG_COMBO_PHY0_P3_BASE + 0xD4)
#define REG_COMBO_PHY0_P3_6A_H       (REG_COMBO_PHY0_P3_BASE + 0xD5)
#define REG_COMBO_PHY0_P3_6B_L       (REG_COMBO_PHY0_P3_BASE + 0xD6)
#define REG_COMBO_PHY0_P3_6B_H       (REG_COMBO_PHY0_P3_BASE + 0xD7)
#define REG_COMBO_PHY0_P3_6C_L       (REG_COMBO_PHY0_P3_BASE + 0xD8)
#define REG_COMBO_PHY0_P3_6C_H       (REG_COMBO_PHY0_P3_BASE + 0xD9)
#define REG_COMBO_PHY0_P3_6D_L       (REG_COMBO_PHY0_P3_BASE + 0xDA)
#define REG_COMBO_PHY0_P3_6D_H       (REG_COMBO_PHY0_P3_BASE + 0xDB)
#define REG_COMBO_PHY0_P3_6E_L       (REG_COMBO_PHY0_P3_BASE + 0xDC)
#define REG_COMBO_PHY0_P3_6E_H       (REG_COMBO_PHY0_P3_BASE + 0xDD)
#define REG_COMBO_PHY0_P3_6F_L       (REG_COMBO_PHY0_P3_BASE + 0xDE)
#define REG_COMBO_PHY0_P3_6F_H       (REG_COMBO_PHY0_P3_BASE + 0xDF)
#define REG_COMBO_PHY0_P3_70_L       (REG_COMBO_PHY0_P3_BASE + 0xE0)
#define REG_COMBO_PHY0_P3_70_H       (REG_COMBO_PHY0_P3_BASE + 0xE1)
#define REG_COMBO_PHY0_P3_71_L       (REG_COMBO_PHY0_P3_BASE + 0xE2)
#define REG_COMBO_PHY0_P3_71_H       (REG_COMBO_PHY0_P3_BASE + 0xE3)
#define REG_COMBO_PHY0_P3_72_L       (REG_COMBO_PHY0_P3_BASE + 0xE4)
#define REG_COMBO_PHY0_P3_72_H       (REG_COMBO_PHY0_P3_BASE + 0xE5)
#define REG_COMBO_PHY0_P3_73_L       (REG_COMBO_PHY0_P3_BASE + 0xE6)
#define REG_COMBO_PHY0_P3_73_H       (REG_COMBO_PHY0_P3_BASE + 0xE7)
#define REG_COMBO_PHY0_P3_74_L       (REG_COMBO_PHY0_P3_BASE + 0xE8)
#define REG_COMBO_PHY0_P3_74_H       (REG_COMBO_PHY0_P3_BASE + 0xE9)
#define REG_COMBO_PHY0_P3_75_L       (REG_COMBO_PHY0_P3_BASE + 0xEA)
#define REG_COMBO_PHY0_P3_75_H       (REG_COMBO_PHY0_P3_BASE + 0xEB)
#define REG_COMBO_PHY0_P3_76_L       (REG_COMBO_PHY0_P3_BASE + 0xEC)
#define REG_COMBO_PHY0_P3_76_H       (REG_COMBO_PHY0_P3_BASE + 0xED)
#define REG_COMBO_PHY0_P3_77_L       (REG_COMBO_PHY0_P3_BASE + 0xEE)
#define REG_COMBO_PHY0_P3_77_H       (REG_COMBO_PHY0_P3_BASE + 0xEF)
#define REG_COMBO_PHY0_P3_78_L       (REG_COMBO_PHY0_P3_BASE + 0xF0)
#define REG_COMBO_PHY0_P3_78_H       (REG_COMBO_PHY0_P3_BASE + 0xF1)
#define REG_COMBO_PHY0_P3_79_L       (REG_COMBO_PHY0_P3_BASE + 0xF2)
#define REG_COMBO_PHY0_P3_79_H       (REG_COMBO_PHY0_P3_BASE + 0xF3)
#define REG_COMBO_PHY0_P3_7A_L       (REG_COMBO_PHY0_P3_BASE + 0xF4)
#define REG_COMBO_PHY0_P3_7A_H       (REG_COMBO_PHY0_P3_BASE + 0xF5)
#define REG_COMBO_PHY0_P3_7B_L       (REG_COMBO_PHY0_P3_BASE + 0xF6)
#define REG_COMBO_PHY0_P3_7B_H       (REG_COMBO_PHY0_P3_BASE + 0xF7)
#define REG_COMBO_PHY0_P3_7C_L       (REG_COMBO_PHY0_P3_BASE + 0xF8)
#define REG_COMBO_PHY0_P3_7C_H       (REG_COMBO_PHY0_P3_BASE + 0xF9)
#define REG_COMBO_PHY0_P3_7D_L       (REG_COMBO_PHY0_P3_BASE + 0xFA)
#define REG_COMBO_PHY0_P3_7D_H       (REG_COMBO_PHY0_P3_BASE + 0xFB)
#define REG_COMBO_PHY0_P3_7E_L       (REG_COMBO_PHY0_P3_BASE + 0xFC)
#define REG_COMBO_PHY0_P3_7E_H       (REG_COMBO_PHY0_P3_BASE + 0xFD)
#define REG_COMBO_PHY0_P3_7F_L       (REG_COMBO_PHY0_P3_BASE + 0xFE)
#define REG_COMBO_PHY0_P3_7F_H       (REG_COMBO_PHY0_P3_BASE + 0xFF)

// COMBO_PHY1_P3
#define REG_COMBO_PHY1_P3_00_L       (REG_COMBO_PHY1_P3_BASE + 0x00)
#define REG_COMBO_PHY1_P3_00_H       (REG_COMBO_PHY1_P3_BASE + 0x01)
#define REG_COMBO_PHY1_P3_01_L       (REG_COMBO_PHY1_P3_BASE + 0x02)
#define REG_COMBO_PHY1_P3_01_H       (REG_COMBO_PHY1_P3_BASE + 0x03)
#define REG_COMBO_PHY1_P3_02_L       (REG_COMBO_PHY1_P3_BASE + 0x04)
#define REG_COMBO_PHY1_P3_02_H       (REG_COMBO_PHY1_P3_BASE + 0x05)
#define REG_COMBO_PHY1_P3_03_L       (REG_COMBO_PHY1_P3_BASE + 0x06)
#define REG_COMBO_PHY1_P3_03_H       (REG_COMBO_PHY1_P3_BASE + 0x07)
#define REG_COMBO_PHY1_P3_04_L       (REG_COMBO_PHY1_P3_BASE + 0x08)
#define REG_COMBO_PHY1_P3_04_H       (REG_COMBO_PHY1_P3_BASE + 0x09)
#define REG_COMBO_PHY1_P3_05_L       (REG_COMBO_PHY1_P3_BASE + 0x0A)
#define REG_COMBO_PHY1_P3_05_H       (REG_COMBO_PHY1_P3_BASE + 0x0B)
#define REG_COMBO_PHY1_P3_06_L       (REG_COMBO_PHY1_P3_BASE + 0x0C)
#define REG_COMBO_PHY1_P3_06_H       (REG_COMBO_PHY1_P3_BASE + 0x0D)
#define REG_COMBO_PHY1_P3_07_L       (REG_COMBO_PHY1_P3_BASE + 0x0E)
#define REG_COMBO_PHY1_P3_07_H       (REG_COMBO_PHY1_P3_BASE + 0x0F)
#define REG_COMBO_PHY1_P3_08_L       (REG_COMBO_PHY1_P3_BASE + 0x10)
#define REG_COMBO_PHY1_P3_08_H       (REG_COMBO_PHY1_P3_BASE + 0x11)
#define REG_COMBO_PHY1_P3_09_L       (REG_COMBO_PHY1_P3_BASE + 0x12)
#define REG_COMBO_PHY1_P3_09_H       (REG_COMBO_PHY1_P3_BASE + 0x13)
#define REG_COMBO_PHY1_P3_0A_L       (REG_COMBO_PHY1_P3_BASE + 0x14)
#define REG_COMBO_PHY1_P3_0A_H       (REG_COMBO_PHY1_P3_BASE + 0x15)
#define REG_COMBO_PHY1_P3_0B_L       (REG_COMBO_PHY1_P3_BASE + 0x16)
#define REG_COMBO_PHY1_P3_0B_H       (REG_COMBO_PHY1_P3_BASE + 0x17)
#define REG_COMBO_PHY1_P3_0C_L       (REG_COMBO_PHY1_P3_BASE + 0x18)
#define REG_COMBO_PHY1_P3_0C_H       (REG_COMBO_PHY1_P3_BASE + 0x19)
#define REG_COMBO_PHY1_P3_0D_L       (REG_COMBO_PHY1_P3_BASE + 0x1A)
#define REG_COMBO_PHY1_P3_0D_H       (REG_COMBO_PHY1_P3_BASE + 0x1B)
#define REG_COMBO_PHY1_P3_0E_L       (REG_COMBO_PHY1_P3_BASE + 0x1C)
#define REG_COMBO_PHY1_P3_0E_H       (REG_COMBO_PHY1_P3_BASE + 0x1D)
#define REG_COMBO_PHY1_P3_0F_L       (REG_COMBO_PHY1_P3_BASE + 0x1E)
#define REG_COMBO_PHY1_P3_0F_H       (REG_COMBO_PHY1_P3_BASE + 0x1F)
#define REG_COMBO_PHY1_P3_10_L       (REG_COMBO_PHY1_P3_BASE + 0x20)
#define REG_COMBO_PHY1_P3_10_H       (REG_COMBO_PHY1_P3_BASE + 0x21)
#define REG_COMBO_PHY1_P3_11_L       (REG_COMBO_PHY1_P3_BASE + 0x22)
#define REG_COMBO_PHY1_P3_11_H       (REG_COMBO_PHY1_P3_BASE + 0x23)
#define REG_COMBO_PHY1_P3_12_L       (REG_COMBO_PHY1_P3_BASE + 0x24)
#define REG_COMBO_PHY1_P3_12_H       (REG_COMBO_PHY1_P3_BASE + 0x25)
#define REG_COMBO_PHY1_P3_13_L       (REG_COMBO_PHY1_P3_BASE + 0x26)
#define REG_COMBO_PHY1_P3_13_H       (REG_COMBO_PHY1_P3_BASE + 0x27)
#define REG_COMBO_PHY1_P3_14_L       (REG_COMBO_PHY1_P3_BASE + 0x28)
#define REG_COMBO_PHY1_P3_14_H       (REG_COMBO_PHY1_P3_BASE + 0x29)
#define REG_COMBO_PHY1_P3_15_L       (REG_COMBO_PHY1_P3_BASE + 0x2A)
#define REG_COMBO_PHY1_P3_15_H       (REG_COMBO_PHY1_P3_BASE + 0x2B)
#define REG_COMBO_PHY1_P3_16_L       (REG_COMBO_PHY1_P3_BASE + 0x2C)
#define REG_COMBO_PHY1_P3_16_H       (REG_COMBO_PHY1_P3_BASE + 0x2D)
#define REG_COMBO_PHY1_P3_17_L       (REG_COMBO_PHY1_P3_BASE + 0x2E)
#define REG_COMBO_PHY1_P3_17_H       (REG_COMBO_PHY1_P3_BASE + 0x2F)
#define REG_COMBO_PHY1_P3_18_L       (REG_COMBO_PHY1_P3_BASE + 0x30)
#define REG_COMBO_PHY1_P3_18_H       (REG_COMBO_PHY1_P3_BASE + 0x31)
#define REG_COMBO_PHY1_P3_19_L       (REG_COMBO_PHY1_P3_BASE + 0x32)
#define REG_COMBO_PHY1_P3_19_H       (REG_COMBO_PHY1_P3_BASE + 0x33)
#define REG_COMBO_PHY1_P3_1A_L       (REG_COMBO_PHY1_P3_BASE + 0x34)
#define REG_COMBO_PHY1_P3_1A_H       (REG_COMBO_PHY1_P3_BASE + 0x35)
#define REG_COMBO_PHY1_P3_1B_L       (REG_COMBO_PHY1_P3_BASE + 0x36)
#define REG_COMBO_PHY1_P3_1B_H       (REG_COMBO_PHY1_P3_BASE + 0x37)
#define REG_COMBO_PHY1_P3_1C_L       (REG_COMBO_PHY1_P3_BASE + 0x38)
#define REG_COMBO_PHY1_P3_1C_H       (REG_COMBO_PHY1_P3_BASE + 0x39)
#define REG_COMBO_PHY1_P3_1D_L       (REG_COMBO_PHY1_P3_BASE + 0x3A)
#define REG_COMBO_PHY1_P3_1D_H       (REG_COMBO_PHY1_P3_BASE + 0x3B)
#define REG_COMBO_PHY1_P3_1E_L       (REG_COMBO_PHY1_P3_BASE + 0x3C)
#define REG_COMBO_PHY1_P3_1E_H       (REG_COMBO_PHY1_P3_BASE + 0x3D)
#define REG_COMBO_PHY1_P3_1F_L       (REG_COMBO_PHY1_P3_BASE + 0x3E)
#define REG_COMBO_PHY1_P3_1F_H       (REG_COMBO_PHY1_P3_BASE + 0x3F)
#define REG_COMBO_PHY1_P3_20_L       (REG_COMBO_PHY1_P3_BASE + 0x40)
#define REG_COMBO_PHY1_P3_20_H       (REG_COMBO_PHY1_P3_BASE + 0x41)
#define REG_COMBO_PHY1_P3_21_L       (REG_COMBO_PHY1_P3_BASE + 0x42)
#define REG_COMBO_PHY1_P3_21_H       (REG_COMBO_PHY1_P3_BASE + 0x43)
#define REG_COMBO_PHY1_P3_22_L       (REG_COMBO_PHY1_P3_BASE + 0x44)
#define REG_COMBO_PHY1_P3_22_H       (REG_COMBO_PHY1_P3_BASE + 0x45)
#define REG_COMBO_PHY1_P3_23_L       (REG_COMBO_PHY1_P3_BASE + 0x46)
#define REG_COMBO_PHY1_P3_23_H       (REG_COMBO_PHY1_P3_BASE + 0x47)
#define REG_COMBO_PHY1_P3_24_L       (REG_COMBO_PHY1_P3_BASE + 0x48)
#define REG_COMBO_PHY1_P3_24_H       (REG_COMBO_PHY1_P3_BASE + 0x49)
#define REG_COMBO_PHY1_P3_25_L       (REG_COMBO_PHY1_P3_BASE + 0x4A)
#define REG_COMBO_PHY1_P3_25_H       (REG_COMBO_PHY1_P3_BASE + 0x4B)
#define REG_COMBO_PHY1_P3_26_L       (REG_COMBO_PHY1_P3_BASE + 0x4C)
#define REG_COMBO_PHY1_P3_26_H       (REG_COMBO_PHY1_P3_BASE + 0x4D)
#define REG_COMBO_PHY1_P3_27_L       (REG_COMBO_PHY1_P3_BASE + 0x4E)
#define REG_COMBO_PHY1_P3_27_H       (REG_COMBO_PHY1_P3_BASE + 0x4F)
#define REG_COMBO_PHY1_P3_28_L       (REG_COMBO_PHY1_P3_BASE + 0x50)
#define REG_COMBO_PHY1_P3_28_H       (REG_COMBO_PHY1_P3_BASE + 0x51)
#define REG_COMBO_PHY1_P3_29_L       (REG_COMBO_PHY1_P3_BASE + 0x52)
#define REG_COMBO_PHY1_P3_29_H       (REG_COMBO_PHY1_P3_BASE + 0x53)
#define REG_COMBO_PHY1_P3_2A_L       (REG_COMBO_PHY1_P3_BASE + 0x54)
#define REG_COMBO_PHY1_P3_2A_H       (REG_COMBO_PHY1_P3_BASE + 0x55)
#define REG_COMBO_PHY1_P3_2B_L       (REG_COMBO_PHY1_P3_BASE + 0x56)
#define REG_COMBO_PHY1_P3_2B_H       (REG_COMBO_PHY1_P3_BASE + 0x57)
#define REG_COMBO_PHY1_P3_2C_L       (REG_COMBO_PHY1_P3_BASE + 0x58)
#define REG_COMBO_PHY1_P3_2C_H       (REG_COMBO_PHY1_P3_BASE + 0x59)
#define REG_COMBO_PHY1_P3_2D_L       (REG_COMBO_PHY1_P3_BASE + 0x5A)
#define REG_COMBO_PHY1_P3_2D_H       (REG_COMBO_PHY1_P3_BASE + 0x5B)
#define REG_COMBO_PHY1_P3_2E_L       (REG_COMBO_PHY1_P3_BASE + 0x5C)
#define REG_COMBO_PHY1_P3_2E_H       (REG_COMBO_PHY1_P3_BASE + 0x5D)
#define REG_COMBO_PHY1_P3_2F_L       (REG_COMBO_PHY1_P3_BASE + 0x5E)
#define REG_COMBO_PHY1_P3_2F_H       (REG_COMBO_PHY1_P3_BASE + 0x5F)
#define REG_COMBO_PHY1_P3_30_L       (REG_COMBO_PHY1_P3_BASE + 0x60)
#define REG_COMBO_PHY1_P3_30_H       (REG_COMBO_PHY1_P3_BASE + 0x61)
#define REG_COMBO_PHY1_P3_31_L       (REG_COMBO_PHY1_P3_BASE + 0x62)
#define REG_COMBO_PHY1_P3_31_H       (REG_COMBO_PHY1_P3_BASE + 0x63)
#define REG_COMBO_PHY1_P3_32_L       (REG_COMBO_PHY1_P3_BASE + 0x64)
#define REG_COMBO_PHY1_P3_32_H       (REG_COMBO_PHY1_P3_BASE + 0x65)
#define REG_COMBO_PHY1_P3_33_L       (REG_COMBO_PHY1_P3_BASE + 0x66)
#define REG_COMBO_PHY1_P3_33_H       (REG_COMBO_PHY1_P3_BASE + 0x67)
#define REG_COMBO_PHY1_P3_34_L       (REG_COMBO_PHY1_P3_BASE + 0x68)
#define REG_COMBO_PHY1_P3_34_H       (REG_COMBO_PHY1_P3_BASE + 0x69)
#define REG_COMBO_PHY1_P3_35_L       (REG_COMBO_PHY1_P3_BASE + 0x6A)
#define REG_COMBO_PHY1_P3_35_H       (REG_COMBO_PHY1_P3_BASE + 0x6B)
#define REG_COMBO_PHY1_P3_36_L       (REG_COMBO_PHY1_P3_BASE + 0x6C)
#define REG_COMBO_PHY1_P3_36_H       (REG_COMBO_PHY1_P3_BASE + 0x6D)
#define REG_COMBO_PHY1_P3_37_L       (REG_COMBO_PHY1_P3_BASE + 0x6E)
#define REG_COMBO_PHY1_P3_37_H       (REG_COMBO_PHY1_P3_BASE + 0x6F)
#define REG_COMBO_PHY1_P3_38_L       (REG_COMBO_PHY1_P3_BASE + 0x70)
#define REG_COMBO_PHY1_P3_38_H       (REG_COMBO_PHY1_P3_BASE + 0x71)
#define REG_COMBO_PHY1_P3_39_L       (REG_COMBO_PHY1_P3_BASE + 0x72)
#define REG_COMBO_PHY1_P3_39_H       (REG_COMBO_PHY1_P3_BASE + 0x73)
#define REG_COMBO_PHY1_P3_3A_L       (REG_COMBO_PHY1_P3_BASE + 0x74)
#define REG_COMBO_PHY1_P3_3A_H       (REG_COMBO_PHY1_P3_BASE + 0x75)
#define REG_COMBO_PHY1_P3_3B_L       (REG_COMBO_PHY1_P3_BASE + 0x76)
#define REG_COMBO_PHY1_P3_3B_H       (REG_COMBO_PHY1_P3_BASE + 0x77)
#define REG_COMBO_PHY1_P3_3C_L       (REG_COMBO_PHY1_P3_BASE + 0x78)
#define REG_COMBO_PHY1_P3_3C_H       (REG_COMBO_PHY1_P3_BASE + 0x79)
#define REG_COMBO_PHY1_P3_3D_L       (REG_COMBO_PHY1_P3_BASE + 0x7A)
#define REG_COMBO_PHY1_P3_3D_H       (REG_COMBO_PHY1_P3_BASE + 0x7B)
#define REG_COMBO_PHY1_P3_3E_L       (REG_COMBO_PHY1_P3_BASE + 0x7C)
#define REG_COMBO_PHY1_P3_3E_H       (REG_COMBO_PHY1_P3_BASE + 0x7D)
#define REG_COMBO_PHY1_P3_3F_L       (REG_COMBO_PHY1_P3_BASE + 0x7E)
#define REG_COMBO_PHY1_P3_3F_H       (REG_COMBO_PHY1_P3_BASE + 0x7F)
#define REG_COMBO_PHY1_P3_40_L       (REG_COMBO_PHY1_P3_BASE + 0x80)
#define REG_COMBO_PHY1_P3_40_H       (REG_COMBO_PHY1_P3_BASE + 0x81)
#define REG_COMBO_PHY1_P3_41_L       (REG_COMBO_PHY1_P3_BASE + 0x82)
#define REG_COMBO_PHY1_P3_41_H       (REG_COMBO_PHY1_P3_BASE + 0x83)
#define REG_COMBO_PHY1_P3_42_L       (REG_COMBO_PHY1_P3_BASE + 0x84)
#define REG_COMBO_PHY1_P3_42_H       (REG_COMBO_PHY1_P3_BASE + 0x85)
#define REG_COMBO_PHY1_P3_43_L       (REG_COMBO_PHY1_P3_BASE + 0x86)
#define REG_COMBO_PHY1_P3_43_H       (REG_COMBO_PHY1_P3_BASE + 0x87)
#define REG_COMBO_PHY1_P3_44_L       (REG_COMBO_PHY1_P3_BASE + 0x88)
#define REG_COMBO_PHY1_P3_44_H       (REG_COMBO_PHY1_P3_BASE + 0x89)
#define REG_COMBO_PHY1_P3_45_L       (REG_COMBO_PHY1_P3_BASE + 0x8A)
#define REG_COMBO_PHY1_P3_45_H       (REG_COMBO_PHY1_P3_BASE + 0x8B)
#define REG_COMBO_PHY1_P3_46_L       (REG_COMBO_PHY1_P3_BASE + 0x8C)
#define REG_COMBO_PHY1_P3_46_H       (REG_COMBO_PHY1_P3_BASE + 0x8D)
#define REG_COMBO_PHY1_P3_47_L       (REG_COMBO_PHY1_P3_BASE + 0x8E)
#define REG_COMBO_PHY1_P3_47_H       (REG_COMBO_PHY1_P3_BASE + 0x8F)
#define REG_COMBO_PHY1_P3_48_L       (REG_COMBO_PHY1_P3_BASE + 0x90)
#define REG_COMBO_PHY1_P3_48_H       (REG_COMBO_PHY1_P3_BASE + 0x91)
#define REG_COMBO_PHY1_P3_49_L       (REG_COMBO_PHY1_P3_BASE + 0x92)
#define REG_COMBO_PHY1_P3_49_H       (REG_COMBO_PHY1_P3_BASE + 0x93)
#define REG_COMBO_PHY1_P3_4A_L       (REG_COMBO_PHY1_P3_BASE + 0x94)
#define REG_COMBO_PHY1_P3_4A_H       (REG_COMBO_PHY1_P3_BASE + 0x95)
#define REG_COMBO_PHY1_P3_4B_L       (REG_COMBO_PHY1_P3_BASE + 0x96)
#define REG_COMBO_PHY1_P3_4B_H       (REG_COMBO_PHY1_P3_BASE + 0x97)
#define REG_COMBO_PHY1_P3_4C_L       (REG_COMBO_PHY1_P3_BASE + 0x98)
#define REG_COMBO_PHY1_P3_4C_H       (REG_COMBO_PHY1_P3_BASE + 0x99)
#define REG_COMBO_PHY1_P3_4D_L       (REG_COMBO_PHY1_P3_BASE + 0x9A)
#define REG_COMBO_PHY1_P3_4D_H       (REG_COMBO_PHY1_P3_BASE + 0x9B)
#define REG_COMBO_PHY1_P3_4E_L       (REG_COMBO_PHY1_P3_BASE + 0x9C)
#define REG_COMBO_PHY1_P3_4E_H       (REG_COMBO_PHY1_P3_BASE + 0x9D)
#define REG_COMBO_PHY1_P3_4F_L       (REG_COMBO_PHY1_P3_BASE + 0x9E)
#define REG_COMBO_PHY1_P3_4F_H       (REG_COMBO_PHY1_P3_BASE + 0x9F)
#define REG_COMBO_PHY1_P3_50_L       (REG_COMBO_PHY1_P3_BASE + 0xA0)
#define REG_COMBO_PHY1_P3_50_H       (REG_COMBO_PHY1_P3_BASE + 0xA1)
#define REG_COMBO_PHY1_P3_51_L       (REG_COMBO_PHY1_P3_BASE + 0xA2)
#define REG_COMBO_PHY1_P3_51_H       (REG_COMBO_PHY1_P3_BASE + 0xA3)
#define REG_COMBO_PHY1_P3_52_L       (REG_COMBO_PHY1_P3_BASE + 0xA4)
#define REG_COMBO_PHY1_P3_52_H       (REG_COMBO_PHY1_P3_BASE + 0xA5)
#define REG_COMBO_PHY1_P3_53_L       (REG_COMBO_PHY1_P3_BASE + 0xA6)
#define REG_COMBO_PHY1_P3_53_H       (REG_COMBO_PHY1_P3_BASE + 0xA7)
#define REG_COMBO_PHY1_P3_54_L       (REG_COMBO_PHY1_P3_BASE + 0xA8)
#define REG_COMBO_PHY1_P3_54_H       (REG_COMBO_PHY1_P3_BASE + 0xA9)
#define REG_COMBO_PHY1_P3_55_L       (REG_COMBO_PHY1_P3_BASE + 0xAA)
#define REG_COMBO_PHY1_P3_55_H       (REG_COMBO_PHY1_P3_BASE + 0xAB)
#define REG_COMBO_PHY1_P3_56_L       (REG_COMBO_PHY1_P3_BASE + 0xAC)
#define REG_COMBO_PHY1_P3_56_H       (REG_COMBO_PHY1_P3_BASE + 0xAD)
#define REG_COMBO_PHY1_P3_57_L       (REG_COMBO_PHY1_P3_BASE + 0xAE)
#define REG_COMBO_PHY1_P3_57_H       (REG_COMBO_PHY1_P3_BASE + 0xAF)
#define REG_COMBO_PHY1_P3_58_L       (REG_COMBO_PHY1_P3_BASE + 0xB0)
#define REG_COMBO_PHY1_P3_58_H       (REG_COMBO_PHY1_P3_BASE + 0xB1)
#define REG_COMBO_PHY1_P3_59_L       (REG_COMBO_PHY1_P3_BASE + 0xB2)
#define REG_COMBO_PHY1_P3_59_H       (REG_COMBO_PHY1_P3_BASE + 0xB3)
#define REG_COMBO_PHY1_P3_5A_L       (REG_COMBO_PHY1_P3_BASE + 0xB4)
#define REG_COMBO_PHY1_P3_5A_H       (REG_COMBO_PHY1_P3_BASE + 0xB5)
#define REG_COMBO_PHY1_P3_5B_L       (REG_COMBO_PHY1_P3_BASE + 0xB6)
#define REG_COMBO_PHY1_P3_5B_H       (REG_COMBO_PHY1_P3_BASE + 0xB7)
#define REG_COMBO_PHY1_P3_5C_L       (REG_COMBO_PHY1_P3_BASE + 0xB8)
#define REG_COMBO_PHY1_P3_5C_H       (REG_COMBO_PHY1_P3_BASE + 0xB9)
#define REG_COMBO_PHY1_P3_5D_L       (REG_COMBO_PHY1_P3_BASE + 0xBA)
#define REG_COMBO_PHY1_P3_5D_H       (REG_COMBO_PHY1_P3_BASE + 0xBB)
#define REG_COMBO_PHY1_P3_5E_L       (REG_COMBO_PHY1_P3_BASE + 0xBC)
#define REG_COMBO_PHY1_P3_5E_H       (REG_COMBO_PHY1_P3_BASE + 0xBD)
#define REG_COMBO_PHY1_P3_5F_L       (REG_COMBO_PHY1_P3_BASE + 0xBE)
#define REG_COMBO_PHY1_P3_5F_H       (REG_COMBO_PHY1_P3_BASE + 0xBF)
#define REG_COMBO_PHY1_P3_60_L       (REG_COMBO_PHY1_P3_BASE + 0xC0)
#define REG_COMBO_PHY1_P3_60_H       (REG_COMBO_PHY1_P3_BASE + 0xC1)
#define REG_COMBO_PHY1_P3_61_L       (REG_COMBO_PHY1_P3_BASE + 0xC2)
#define REG_COMBO_PHY1_P3_61_H       (REG_COMBO_PHY1_P3_BASE + 0xC3)
#define REG_COMBO_PHY1_P3_62_L       (REG_COMBO_PHY1_P3_BASE + 0xC4)
#define REG_COMBO_PHY1_P3_62_H       (REG_COMBO_PHY1_P3_BASE + 0xC5)
#define REG_COMBO_PHY1_P3_63_L       (REG_COMBO_PHY1_P3_BASE + 0xC6)
#define REG_COMBO_PHY1_P3_63_H       (REG_COMBO_PHY1_P3_BASE + 0xC7)
#define REG_COMBO_PHY1_P3_64_L       (REG_COMBO_PHY1_P3_BASE + 0xC8)
#define REG_COMBO_PHY1_P3_64_H       (REG_COMBO_PHY1_P3_BASE + 0xC9)
#define REG_COMBO_PHY1_P3_65_L       (REG_COMBO_PHY1_P3_BASE + 0xCA)
#define REG_COMBO_PHY1_P3_65_H       (REG_COMBO_PHY1_P3_BASE + 0xCB)
#define REG_COMBO_PHY1_P3_66_L       (REG_COMBO_PHY1_P3_BASE + 0xCC)
#define REG_COMBO_PHY1_P3_66_H       (REG_COMBO_PHY1_P3_BASE + 0xCD)
#define REG_COMBO_PHY1_P3_67_L       (REG_COMBO_PHY1_P3_BASE + 0xCE)
#define REG_COMBO_PHY1_P3_67_H       (REG_COMBO_PHY1_P3_BASE + 0xCF)
#define REG_COMBO_PHY1_P3_68_L       (REG_COMBO_PHY1_P3_BASE + 0xD0)
#define REG_COMBO_PHY1_P3_68_H       (REG_COMBO_PHY1_P3_BASE + 0xD1)
#define REG_COMBO_PHY1_P3_69_L       (REG_COMBO_PHY1_P3_BASE + 0xD2)
#define REG_COMBO_PHY1_P3_69_H       (REG_COMBO_PHY1_P3_BASE + 0xD3)
#define REG_COMBO_PHY1_P3_6A_L       (REG_COMBO_PHY1_P3_BASE + 0xD4)
#define REG_COMBO_PHY1_P3_6A_H       (REG_COMBO_PHY1_P3_BASE + 0xD5)
#define REG_COMBO_PHY1_P3_6B_L       (REG_COMBO_PHY1_P3_BASE + 0xD6)
#define REG_COMBO_PHY1_P3_6B_H       (REG_COMBO_PHY1_P3_BASE + 0xD7)
#define REG_COMBO_PHY1_P3_6C_L       (REG_COMBO_PHY1_P3_BASE + 0xD8)
#define REG_COMBO_PHY1_P3_6C_H       (REG_COMBO_PHY1_P3_BASE + 0xD9)
#define REG_COMBO_PHY1_P3_6D_L       (REG_COMBO_PHY1_P3_BASE + 0xDA)
#define REG_COMBO_PHY1_P3_6D_H       (REG_COMBO_PHY1_P3_BASE + 0xDB)
#define REG_COMBO_PHY1_P3_6E_L       (REG_COMBO_PHY1_P3_BASE + 0xDC)
#define REG_COMBO_PHY1_P3_6E_H       (REG_COMBO_PHY1_P3_BASE + 0xDD)
#define REG_COMBO_PHY1_P3_6F_L       (REG_COMBO_PHY1_P3_BASE + 0xDE)
#define REG_COMBO_PHY1_P3_6F_H       (REG_COMBO_PHY1_P3_BASE + 0xDF)
#define REG_COMBO_PHY1_P3_70_L       (REG_COMBO_PHY1_P3_BASE + 0xE0)
#define REG_COMBO_PHY1_P3_70_H       (REG_COMBO_PHY1_P3_BASE + 0xE1)
#define REG_COMBO_PHY1_P3_71_L       (REG_COMBO_PHY1_P3_BASE + 0xE2)
#define REG_COMBO_PHY1_P3_71_H       (REG_COMBO_PHY1_P3_BASE + 0xE3)
#define REG_COMBO_PHY1_P3_72_L       (REG_COMBO_PHY1_P3_BASE + 0xE4)
#define REG_COMBO_PHY1_P3_72_H       (REG_COMBO_PHY1_P3_BASE + 0xE5)
#define REG_COMBO_PHY1_P3_73_L       (REG_COMBO_PHY1_P3_BASE + 0xE6)
#define REG_COMBO_PHY1_P3_73_H       (REG_COMBO_PHY1_P3_BASE + 0xE7)
#define REG_COMBO_PHY1_P3_74_L       (REG_COMBO_PHY1_P3_BASE + 0xE8)
#define REG_COMBO_PHY1_P3_74_H       (REG_COMBO_PHY1_P3_BASE + 0xE9)
#define REG_COMBO_PHY1_P3_75_L       (REG_COMBO_PHY1_P3_BASE + 0xEA)
#define REG_COMBO_PHY1_P3_75_H       (REG_COMBO_PHY1_P3_BASE + 0xEB)
#define REG_COMBO_PHY1_P3_76_L       (REG_COMBO_PHY1_P3_BASE + 0xEC)
#define REG_COMBO_PHY1_P3_76_H       (REG_COMBO_PHY1_P3_BASE + 0xED)
#define REG_COMBO_PHY1_P3_77_L       (REG_COMBO_PHY1_P3_BASE + 0xEE)
#define REG_COMBO_PHY1_P3_77_H       (REG_COMBO_PHY1_P3_BASE + 0xEF)
#define REG_COMBO_PHY1_P3_78_L       (REG_COMBO_PHY1_P3_BASE + 0xF0)
#define REG_COMBO_PHY1_P3_78_H       (REG_COMBO_PHY1_P3_BASE + 0xF1)
#define REG_COMBO_PHY1_P3_79_L       (REG_COMBO_PHY1_P3_BASE + 0xF2)
#define REG_COMBO_PHY1_P3_79_H       (REG_COMBO_PHY1_P3_BASE + 0xF3)
#define REG_COMBO_PHY1_P3_7A_L       (REG_COMBO_PHY1_P3_BASE + 0xF4)
#define REG_COMBO_PHY1_P3_7A_H       (REG_COMBO_PHY1_P3_BASE + 0xF5)
#define REG_COMBO_PHY1_P3_7B_L       (REG_COMBO_PHY1_P3_BASE + 0xF6)
#define REG_COMBO_PHY1_P3_7B_H       (REG_COMBO_PHY1_P3_BASE + 0xF7)
#define REG_COMBO_PHY1_P3_7C_L       (REG_COMBO_PHY1_P3_BASE + 0xF8)
#define REG_COMBO_PHY1_P3_7C_H       (REG_COMBO_PHY1_P3_BASE + 0xF9)
#define REG_COMBO_PHY1_P3_7D_L       (REG_COMBO_PHY1_P3_BASE + 0xFA)
#define REG_COMBO_PHY1_P3_7D_H       (REG_COMBO_PHY1_P3_BASE + 0xFB)
#define REG_COMBO_PHY1_P3_7E_L       (REG_COMBO_PHY1_P3_BASE + 0xFC)
#define REG_COMBO_PHY1_P3_7E_H       (REG_COMBO_PHY1_P3_BASE + 0xFD)
#define REG_COMBO_PHY1_P3_7F_L       (REG_COMBO_PHY1_P3_BASE + 0xFE)
#define REG_COMBO_PHY1_P3_7F_H       (REG_COMBO_PHY1_P3_BASE + 0xFF)

//=============================================================

// DVI_DTOP_DUAL_P0
#define REG_DVI_DTOP_DUAL_P0_00_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
#define REG_DVI_DTOP_DUAL_P0_00_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
#define REG_DVI_DTOP_DUAL_P0_01_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
#define REG_DVI_DTOP_DUAL_P0_01_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
#define REG_DVI_DTOP_DUAL_P0_02_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
#define REG_DVI_DTOP_DUAL_P0_02_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
#define REG_DVI_DTOP_DUAL_P0_03_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
#define REG_DVI_DTOP_DUAL_P0_03_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
#define REG_DVI_DTOP_DUAL_P0_04_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
#define REG_DVI_DTOP_DUAL_P0_04_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
#define REG_DVI_DTOP_DUAL_P0_05_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0A)
#define REG_DVI_DTOP_DUAL_P0_05_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0B)
#define REG_DVI_DTOP_DUAL_P0_06_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0C)
#define REG_DVI_DTOP_DUAL_P0_06_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0D)
#define REG_DVI_DTOP_DUAL_P0_07_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0E)
#define REG_DVI_DTOP_DUAL_P0_07_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0F)
#define REG_DVI_DTOP_DUAL_P0_08_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x10)
#define REG_DVI_DTOP_DUAL_P0_08_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x11)
#define REG_DVI_DTOP_DUAL_P0_09_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x12)
#define REG_DVI_DTOP_DUAL_P0_09_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x13)
#define REG_DVI_DTOP_DUAL_P0_0A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x14)
#define REG_DVI_DTOP_DUAL_P0_0A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x15)
#define REG_DVI_DTOP_DUAL_P0_0B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x16)
#define REG_DVI_DTOP_DUAL_P0_0B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x17)
#define REG_DVI_DTOP_DUAL_P0_0C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x18)
#define REG_DVI_DTOP_DUAL_P0_0C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x19)
#define REG_DVI_DTOP_DUAL_P0_0D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1A)
#define REG_DVI_DTOP_DUAL_P0_0D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1B)
#define REG_DVI_DTOP_DUAL_P0_0E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1C)
#define REG_DVI_DTOP_DUAL_P0_0E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1D)
#define REG_DVI_DTOP_DUAL_P0_0F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1E)
#define REG_DVI_DTOP_DUAL_P0_0F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1F)
#define REG_DVI_DTOP_DUAL_P0_10_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x20)
#define REG_DVI_DTOP_DUAL_P0_10_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x21)
#define REG_DVI_DTOP_DUAL_P0_11_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x22)
#define REG_DVI_DTOP_DUAL_P0_11_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x23)
#define REG_DVI_DTOP_DUAL_P0_12_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x24)
#define REG_DVI_DTOP_DUAL_P0_12_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x25)
#define REG_DVI_DTOP_DUAL_P0_13_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x26)
#define REG_DVI_DTOP_DUAL_P0_13_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x27)
#define REG_DVI_DTOP_DUAL_P0_14_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x28)
#define REG_DVI_DTOP_DUAL_P0_14_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x29)
#define REG_DVI_DTOP_DUAL_P0_15_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2A)
#define REG_DVI_DTOP_DUAL_P0_15_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2B)
#define REG_DVI_DTOP_DUAL_P0_16_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2C)
#define REG_DVI_DTOP_DUAL_P0_16_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2D)
#define REG_DVI_DTOP_DUAL_P0_17_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2E)
#define REG_DVI_DTOP_DUAL_P0_17_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2F)
#define REG_DVI_DTOP_DUAL_P0_18_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x30)
#define REG_DVI_DTOP_DUAL_P0_18_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x31)
#define REG_DVI_DTOP_DUAL_P0_19_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x32)
#define REG_DVI_DTOP_DUAL_P0_19_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x33)
#define REG_DVI_DTOP_DUAL_P0_1A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x34)
#define REG_DVI_DTOP_DUAL_P0_1A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x35)
#define REG_DVI_DTOP_DUAL_P0_1B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x36)
#define REG_DVI_DTOP_DUAL_P0_1B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x37)
#define REG_DVI_DTOP_DUAL_P0_1C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x38)
#define REG_DVI_DTOP_DUAL_P0_1C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x39)
#define REG_DVI_DTOP_DUAL_P0_1D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3A)
#define REG_DVI_DTOP_DUAL_P0_1D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3B)
#define REG_DVI_DTOP_DUAL_P0_1E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3C)
#define REG_DVI_DTOP_DUAL_P0_1E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3D)
#define REG_DVI_DTOP_DUAL_P0_1F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3E)
#define REG_DVI_DTOP_DUAL_P0_1F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3F)
#define REG_DVI_DTOP_DUAL_P0_20_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x40)
#define REG_DVI_DTOP_DUAL_P0_20_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x41)
#define REG_DVI_DTOP_DUAL_P0_21_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x42)
#define REG_DVI_DTOP_DUAL_P0_21_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x43)
#define REG_DVI_DTOP_DUAL_P0_22_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x44)
#define REG_DVI_DTOP_DUAL_P0_22_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x45)
#define REG_DVI_DTOP_DUAL_P0_23_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x46)
#define REG_DVI_DTOP_DUAL_P0_23_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x47)
#define REG_DVI_DTOP_DUAL_P0_24_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x48)
#define REG_DVI_DTOP_DUAL_P0_24_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x49)
#define REG_DVI_DTOP_DUAL_P0_25_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4A)
#define REG_DVI_DTOP_DUAL_P0_25_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4B)
#define REG_DVI_DTOP_DUAL_P0_26_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4C)
#define REG_DVI_DTOP_DUAL_P0_26_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4D)
#define REG_DVI_DTOP_DUAL_P0_27_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4E)
#define REG_DVI_DTOP_DUAL_P0_27_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4F)
#define REG_DVI_DTOP_DUAL_P0_28_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x50)
#define REG_DVI_DTOP_DUAL_P0_28_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x51)
#define REG_DVI_DTOP_DUAL_P0_29_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x52)
#define REG_DVI_DTOP_DUAL_P0_29_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x53)
#define REG_DVI_DTOP_DUAL_P0_2A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x54)
#define REG_DVI_DTOP_DUAL_P0_2A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x55)
#define REG_DVI_DTOP_DUAL_P0_2B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x56)
#define REG_DVI_DTOP_DUAL_P0_2B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x57)
#define REG_DVI_DTOP_DUAL_P0_2C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x58)
#define REG_DVI_DTOP_DUAL_P0_2C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x59)
#define REG_DVI_DTOP_DUAL_P0_2D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5A)
#define REG_DVI_DTOP_DUAL_P0_2D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5B)
#define REG_DVI_DTOP_DUAL_P0_2E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5C)
#define REG_DVI_DTOP_DUAL_P0_2E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5D)
#define REG_DVI_DTOP_DUAL_P0_2F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5E)
#define REG_DVI_DTOP_DUAL_P0_2F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5F)
#define REG_DVI_DTOP_DUAL_P0_30_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x60)
#define REG_DVI_DTOP_DUAL_P0_30_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x61)
#define REG_DVI_DTOP_DUAL_P0_31_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x62)
#define REG_DVI_DTOP_DUAL_P0_31_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x63)
#define REG_DVI_DTOP_DUAL_P0_32_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x64)
#define REG_DVI_DTOP_DUAL_P0_32_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x65)
#define REG_DVI_DTOP_DUAL_P0_33_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x66)
#define REG_DVI_DTOP_DUAL_P0_33_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x67)
#define REG_DVI_DTOP_DUAL_P0_34_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x68)
#define REG_DVI_DTOP_DUAL_P0_34_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x69)
#define REG_DVI_DTOP_DUAL_P0_35_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6A)
#define REG_DVI_DTOP_DUAL_P0_35_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6B)
#define REG_DVI_DTOP_DUAL_P0_36_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6C)
#define REG_DVI_DTOP_DUAL_P0_36_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6D)
#define REG_DVI_DTOP_DUAL_P0_37_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6E)
#define REG_DVI_DTOP_DUAL_P0_37_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6F)
#define REG_DVI_DTOP_DUAL_P0_38_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x70)
#define REG_DVI_DTOP_DUAL_P0_38_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x71)
#define REG_DVI_DTOP_DUAL_P0_39_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x72)
#define REG_DVI_DTOP_DUAL_P0_39_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x73)
#define REG_DVI_DTOP_DUAL_P0_3A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x74)
#define REG_DVI_DTOP_DUAL_P0_3A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x75)
#define REG_DVI_DTOP_DUAL_P0_3B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x76)
#define REG_DVI_DTOP_DUAL_P0_3B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x77)
#define REG_DVI_DTOP_DUAL_P0_3C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x78)
#define REG_DVI_DTOP_DUAL_P0_3C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x79)
#define REG_DVI_DTOP_DUAL_P0_3D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7A)
#define REG_DVI_DTOP_DUAL_P0_3D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7B)
#define REG_DVI_DTOP_DUAL_P0_3E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C)
#define REG_DVI_DTOP_DUAL_P0_3E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7D)
#define REG_DVI_DTOP_DUAL_P0_3F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7E)
#define REG_DVI_DTOP_DUAL_P0_3F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7F)
#define REG_DVI_DTOP_DUAL_P0_40_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x80)
#define REG_DVI_DTOP_DUAL_P0_40_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x81)
#define REG_DVI_DTOP_DUAL_P0_41_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x82)
#define REG_DVI_DTOP_DUAL_P0_41_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x83)
#define REG_DVI_DTOP_DUAL_P0_42_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x84)
#define REG_DVI_DTOP_DUAL_P0_42_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x85)
#define REG_DVI_DTOP_DUAL_P0_43_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x86)
#define REG_DVI_DTOP_DUAL_P0_43_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x87)
#define REG_DVI_DTOP_DUAL_P0_44_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x88)
#define REG_DVI_DTOP_DUAL_P0_44_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x89)
#define REG_DVI_DTOP_DUAL_P0_45_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8A)
#define REG_DVI_DTOP_DUAL_P0_45_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8B)
#define REG_DVI_DTOP_DUAL_P0_46_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8C)
#define REG_DVI_DTOP_DUAL_P0_46_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8D)
#define REG_DVI_DTOP_DUAL_P0_47_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8E)
#define REG_DVI_DTOP_DUAL_P0_47_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8F)
#define REG_DVI_DTOP_DUAL_P0_48_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x90)
#define REG_DVI_DTOP_DUAL_P0_48_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x91)
#define REG_DVI_DTOP_DUAL_P0_49_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x92)
#define REG_DVI_DTOP_DUAL_P0_49_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x93)
#define REG_DVI_DTOP_DUAL_P0_4A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x94)
#define REG_DVI_DTOP_DUAL_P0_4A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x95)
#define REG_DVI_DTOP_DUAL_P0_4B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x96)
#define REG_DVI_DTOP_DUAL_P0_4B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x97)
#define REG_DVI_DTOP_DUAL_P0_4C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x98)
#define REG_DVI_DTOP_DUAL_P0_4C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x99)
#define REG_DVI_DTOP_DUAL_P0_4D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9A)
#define REG_DVI_DTOP_DUAL_P0_4D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9B)
#define REG_DVI_DTOP_DUAL_P0_4E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9C)
#define REG_DVI_DTOP_DUAL_P0_4E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9D)
#define REG_DVI_DTOP_DUAL_P0_4F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9E)
#define REG_DVI_DTOP_DUAL_P0_4F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9F)
#define REG_DVI_DTOP_DUAL_P0_50_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA0)
#define REG_DVI_DTOP_DUAL_P0_50_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA1)
#define REG_DVI_DTOP_DUAL_P0_51_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA2)
#define REG_DVI_DTOP_DUAL_P0_51_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA3)
#define REG_DVI_DTOP_DUAL_P0_52_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA4)
#define REG_DVI_DTOP_DUAL_P0_52_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA5)
#define REG_DVI_DTOP_DUAL_P0_53_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA6)
#define REG_DVI_DTOP_DUAL_P0_53_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA7)
#define REG_DVI_DTOP_DUAL_P0_54_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA8)
#define REG_DVI_DTOP_DUAL_P0_54_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA9)
#define REG_DVI_DTOP_DUAL_P0_55_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAA)
#define REG_DVI_DTOP_DUAL_P0_55_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAB)
#define REG_DVI_DTOP_DUAL_P0_56_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAC)
#define REG_DVI_DTOP_DUAL_P0_56_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAD)
#define REG_DVI_DTOP_DUAL_P0_57_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAE)
#define REG_DVI_DTOP_DUAL_P0_57_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAF)
#define REG_DVI_DTOP_DUAL_P0_58_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB0)
#define REG_DVI_DTOP_DUAL_P0_58_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB1)
#define REG_DVI_DTOP_DUAL_P0_59_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB2)
#define REG_DVI_DTOP_DUAL_P0_59_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB3)
#define REG_DVI_DTOP_DUAL_P0_5A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB4)
#define REG_DVI_DTOP_DUAL_P0_5A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB5)
#define REG_DVI_DTOP_DUAL_P0_5B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB6)
#define REG_DVI_DTOP_DUAL_P0_5B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB7)
#define REG_DVI_DTOP_DUAL_P0_5C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB8)
#define REG_DVI_DTOP_DUAL_P0_5C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB9)
#define REG_DVI_DTOP_DUAL_P0_5D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBA)
#define REG_DVI_DTOP_DUAL_P0_5D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBB)
#define REG_DVI_DTOP_DUAL_P0_5E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBC)
#define REG_DVI_DTOP_DUAL_P0_5E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBD)
#define REG_DVI_DTOP_DUAL_P0_5F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBE)
#define REG_DVI_DTOP_DUAL_P0_5F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBF)
#define REG_DVI_DTOP_DUAL_P0_60_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC0)
#define REG_DVI_DTOP_DUAL_P0_60_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC1)
#define REG_DVI_DTOP_DUAL_P0_61_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC2)
#define REG_DVI_DTOP_DUAL_P0_61_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC3)
#define REG_DVI_DTOP_DUAL_P0_62_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC4)
#define REG_DVI_DTOP_DUAL_P0_62_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC5)
#define REG_DVI_DTOP_DUAL_P0_63_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC6)
#define REG_DVI_DTOP_DUAL_P0_63_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC7)
#define REG_DVI_DTOP_DUAL_P0_64_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC8)
#define REG_DVI_DTOP_DUAL_P0_64_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC9)
#define REG_DVI_DTOP_DUAL_P0_65_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCA)
#define REG_DVI_DTOP_DUAL_P0_65_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCB)
#define REG_DVI_DTOP_DUAL_P0_66_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCC)
#define REG_DVI_DTOP_DUAL_P0_66_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCD)
#define REG_DVI_DTOP_DUAL_P0_67_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCE)
#define REG_DVI_DTOP_DUAL_P0_67_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCF)
#define REG_DVI_DTOP_DUAL_P0_68_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD0)
#define REG_DVI_DTOP_DUAL_P0_68_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD1)
#define REG_DVI_DTOP_DUAL_P0_69_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD2)
#define REG_DVI_DTOP_DUAL_P0_69_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD3)
#define REG_DVI_DTOP_DUAL_P0_6A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD4)
#define REG_DVI_DTOP_DUAL_P0_6A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD5)
#define REG_DVI_DTOP_DUAL_P0_6B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD6)
#define REG_DVI_DTOP_DUAL_P0_6B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD7)
#define REG_DVI_DTOP_DUAL_P0_6C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD8)
#define REG_DVI_DTOP_DUAL_P0_6C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD9)
#define REG_DVI_DTOP_DUAL_P0_6D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDA)
#define REG_DVI_DTOP_DUAL_P0_6D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDB)
#define REG_DVI_DTOP_DUAL_P0_6E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDC)
#define REG_DVI_DTOP_DUAL_P0_6E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDD)
#define REG_DVI_DTOP_DUAL_P0_6F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDE)
#define REG_DVI_DTOP_DUAL_P0_6F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDF)
#define REG_DVI_DTOP_DUAL_P0_70_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE0)
#define REG_DVI_DTOP_DUAL_P0_70_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE1)
#define REG_DVI_DTOP_DUAL_P0_71_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE2)
#define REG_DVI_DTOP_DUAL_P0_71_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE3)
#define REG_DVI_DTOP_DUAL_P0_72_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE4)
#define REG_DVI_DTOP_DUAL_P0_72_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE5)
#define REG_DVI_DTOP_DUAL_P0_73_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE6)
#define REG_DVI_DTOP_DUAL_P0_73_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE7)
#define REG_DVI_DTOP_DUAL_P0_74_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE8)
#define REG_DVI_DTOP_DUAL_P0_74_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE9)
#define REG_DVI_DTOP_DUAL_P0_75_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEA)
#define REG_DVI_DTOP_DUAL_P0_75_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEB)
#define REG_DVI_DTOP_DUAL_P0_76_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEC)
#define REG_DVI_DTOP_DUAL_P0_76_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xED)
#define REG_DVI_DTOP_DUAL_P0_77_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEE)
#define REG_DVI_DTOP_DUAL_P0_77_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEF)
#define REG_DVI_DTOP_DUAL_P0_78_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF0)
#define REG_DVI_DTOP_DUAL_P0_78_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF1)
#define REG_DVI_DTOP_DUAL_P0_79_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF2)
#define REG_DVI_DTOP_DUAL_P0_79_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF3)
#define REG_DVI_DTOP_DUAL_P0_7A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF4)
#define REG_DVI_DTOP_DUAL_P0_7A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF5)
#define REG_DVI_DTOP_DUAL_P0_7B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF6)
#define REG_DVI_DTOP_DUAL_P0_7B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF7)
#define REG_DVI_DTOP_DUAL_P0_7C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF8)
#define REG_DVI_DTOP_DUAL_P0_7C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF9)
#define REG_DVI_DTOP_DUAL_P0_7D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFA)
#define REG_DVI_DTOP_DUAL_P0_7D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFB)
#define REG_DVI_DTOP_DUAL_P0_7E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFC)
#define REG_DVI_DTOP_DUAL_P0_7E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFD)
#define REG_DVI_DTOP_DUAL_P0_7F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFE)
#define REG_DVI_DTOP_DUAL_P0_7F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFF)

// DVI_RSV_DUAL_P0
#define REG_DVI_RSV_DUAL_P0_00_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
#define REG_DVI_RSV_DUAL_P0_00_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
#define REG_DVI_RSV_DUAL_P0_01_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
#define REG_DVI_RSV_DUAL_P0_01_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
#define REG_DVI_RSV_DUAL_P0_02_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
#define REG_DVI_RSV_DUAL_P0_02_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
#define REG_DVI_RSV_DUAL_P0_03_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
#define REG_DVI_RSV_DUAL_P0_03_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
#define REG_DVI_RSV_DUAL_P0_04_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
#define REG_DVI_RSV_DUAL_P0_04_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
#define REG_DVI_RSV_DUAL_P0_05_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0A)
#define REG_DVI_RSV_DUAL_P0_05_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0B)
#define REG_DVI_RSV_DUAL_P0_06_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0C)
#define REG_DVI_RSV_DUAL_P0_06_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0D)
#define REG_DVI_RSV_DUAL_P0_07_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0E)
#define REG_DVI_RSV_DUAL_P0_07_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0F)
#define REG_DVI_RSV_DUAL_P0_08_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x10)
#define REG_DVI_RSV_DUAL_P0_08_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x11)
#define REG_DVI_RSV_DUAL_P0_09_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x12)
#define REG_DVI_RSV_DUAL_P0_09_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x13)
#define REG_DVI_RSV_DUAL_P0_0A_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x14)
#define REG_DVI_RSV_DUAL_P0_0A_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x15)
#define REG_DVI_RSV_DUAL_P0_0B_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x16)
#define REG_DVI_RSV_DUAL_P0_0B_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x17)
#define REG_DVI_RSV_DUAL_P0_0C_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x18)
#define REG_DVI_RSV_DUAL_P0_0C_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x19)
#define REG_DVI_RSV_DUAL_P0_0D_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1A)
#define REG_DVI_RSV_DUAL_P0_0D_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1B)
#define REG_DVI_RSV_DUAL_P0_0E_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1C)
#define REG_DVI_RSV_DUAL_P0_0E_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1D)
#define REG_DVI_RSV_DUAL_P0_0F_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1E)
#define REG_DVI_RSV_DUAL_P0_0F_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1F)
#define REG_DVI_RSV_DUAL_P0_10_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x20)
#define REG_DVI_RSV_DUAL_P0_10_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x21)
#define REG_DVI_RSV_DUAL_P0_11_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x22)
#define REG_DVI_RSV_DUAL_P0_11_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x23)
#define REG_DVI_RSV_DUAL_P0_12_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x24)
#define REG_DVI_RSV_DUAL_P0_12_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x25)
#define REG_DVI_RSV_DUAL_P0_13_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x26)
#define REG_DVI_RSV_DUAL_P0_13_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x27)
#define REG_DVI_RSV_DUAL_P0_14_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x28)
#define REG_DVI_RSV_DUAL_P0_14_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x29)
#define REG_DVI_RSV_DUAL_P0_15_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2A)
#define REG_DVI_RSV_DUAL_P0_15_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2B)
#define REG_DVI_RSV_DUAL_P0_16_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2C)
#define REG_DVI_RSV_DUAL_P0_16_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2D)
#define REG_DVI_RSV_DUAL_P0_17_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2E)
#define REG_DVI_RSV_DUAL_P0_17_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2F)
#define REG_DVI_RSV_DUAL_P0_18_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x30)
#define REG_DVI_RSV_DUAL_P0_18_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x31)
#define REG_DVI_RSV_DUAL_P0_19_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x32)
#define REG_DVI_RSV_DUAL_P0_19_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x33)
#define REG_DVI_RSV_DUAL_P0_1A_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x34)
#define REG_DVI_RSV_DUAL_P0_1A_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x35)
#define REG_DVI_RSV_DUAL_P0_1B_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x36)
#define REG_DVI_RSV_DUAL_P0_1B_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x37)
#define REG_DVI_RSV_DUAL_P0_1C_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x38)
#define REG_DVI_RSV_DUAL_P0_1C_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x39)
#define REG_DVI_RSV_DUAL_P0_1D_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3A)
#define REG_DVI_RSV_DUAL_P0_1D_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3B)
#define REG_DVI_RSV_DUAL_P0_1E_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3C)
#define REG_DVI_RSV_DUAL_P0_1E_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3D)
#define REG_DVI_RSV_DUAL_P0_1F_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3E)
#define REG_DVI_RSV_DUAL_P0_1F_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3F)

// HDCP_DUAL_P0
#define REG_HDCP_DUAL_P0_00_L       (REG_HDCP_DUAL_P0_BASE + 0x00)
#define REG_HDCP_DUAL_P0_00_H       (REG_HDCP_DUAL_P0_BASE + 0x01)
#define REG_HDCP_DUAL_P0_01_L       (REG_HDCP_DUAL_P0_BASE + 0x02)
#define REG_HDCP_DUAL_P0_01_H       (REG_HDCP_DUAL_P0_BASE + 0x03)
#define REG_HDCP_DUAL_P0_02_L       (REG_HDCP_DUAL_P0_BASE + 0x04)
#define REG_HDCP_DUAL_P0_02_H       (REG_HDCP_DUAL_P0_BASE + 0x05)
#define REG_HDCP_DUAL_P0_03_L       (REG_HDCP_DUAL_P0_BASE + 0x06)
#define REG_HDCP_DUAL_P0_03_H       (REG_HDCP_DUAL_P0_BASE + 0x07)
#define REG_HDCP_DUAL_P0_04_L       (REG_HDCP_DUAL_P0_BASE + 0x08)
#define REG_HDCP_DUAL_P0_04_H       (REG_HDCP_DUAL_P0_BASE + 0x09)
#define REG_HDCP_DUAL_P0_05_L       (REG_HDCP_DUAL_P0_BASE + 0x0A)
#define REG_HDCP_DUAL_P0_05_H       (REG_HDCP_DUAL_P0_BASE + 0x0B)
#define REG_HDCP_DUAL_P0_06_L       (REG_HDCP_DUAL_P0_BASE + 0x0C)
#define REG_HDCP_DUAL_P0_06_H       (REG_HDCP_DUAL_P0_BASE + 0x0D)
#define REG_HDCP_DUAL_P0_07_L       (REG_HDCP_DUAL_P0_BASE + 0x0E)
#define REG_HDCP_DUAL_P0_07_H       (REG_HDCP_DUAL_P0_BASE + 0x0F)
#define REG_HDCP_DUAL_P0_08_L       (REG_HDCP_DUAL_P0_BASE + 0x10)
#define REG_HDCP_DUAL_P0_08_H       (REG_HDCP_DUAL_P0_BASE + 0x11)
#define REG_HDCP_DUAL_P0_09_L       (REG_HDCP_DUAL_P0_BASE + 0x12)
#define REG_HDCP_DUAL_P0_09_H       (REG_HDCP_DUAL_P0_BASE + 0x13)
#define REG_HDCP_DUAL_P0_0A_L       (REG_HDCP_DUAL_P0_BASE + 0x14)
#define REG_HDCP_DUAL_P0_0A_H       (REG_HDCP_DUAL_P0_BASE + 0x15)
#define REG_HDCP_DUAL_P0_0B_L       (REG_HDCP_DUAL_P0_BASE + 0x16)
#define REG_HDCP_DUAL_P0_0B_H       (REG_HDCP_DUAL_P0_BASE + 0x17)
#define REG_HDCP_DUAL_P0_0C_L       (REG_HDCP_DUAL_P0_BASE + 0x18)
#define REG_HDCP_DUAL_P0_0C_H       (REG_HDCP_DUAL_P0_BASE + 0x19)
#define REG_HDCP_DUAL_P0_0D_L       (REG_HDCP_DUAL_P0_BASE + 0x1A)
#define REG_HDCP_DUAL_P0_0D_H       (REG_HDCP_DUAL_P0_BASE + 0x1B)
#define REG_HDCP_DUAL_P0_0E_L       (REG_HDCP_DUAL_P0_BASE + 0x1C)
#define REG_HDCP_DUAL_P0_0E_H       (REG_HDCP_DUAL_P0_BASE + 0x1D)
#define REG_HDCP_DUAL_P0_0F_L       (REG_HDCP_DUAL_P0_BASE + 0x1E)
#define REG_HDCP_DUAL_P0_0F_H       (REG_HDCP_DUAL_P0_BASE + 0x1F)
#define REG_HDCP_DUAL_P0_10_L       (REG_HDCP_DUAL_P0_BASE + 0x20)
#define REG_HDCP_DUAL_P0_10_H       (REG_HDCP_DUAL_P0_BASE + 0x21)
#define REG_HDCP_DUAL_P0_11_L       (REG_HDCP_DUAL_P0_BASE + 0x22)
#define REG_HDCP_DUAL_P0_11_H       (REG_HDCP_DUAL_P0_BASE + 0x23)
#define REG_HDCP_DUAL_P0_12_L       (REG_HDCP_DUAL_P0_BASE + 0x24)
#define REG_HDCP_DUAL_P0_12_H       (REG_HDCP_DUAL_P0_BASE + 0x25)
#define REG_HDCP_DUAL_P0_13_L       (REG_HDCP_DUAL_P0_BASE + 0x26)
#define REG_HDCP_DUAL_P0_13_H       (REG_HDCP_DUAL_P0_BASE + 0x27)
#define REG_HDCP_DUAL_P0_14_L       (REG_HDCP_DUAL_P0_BASE + 0x28)
#define REG_HDCP_DUAL_P0_14_H       (REG_HDCP_DUAL_P0_BASE + 0x29)
#define REG_HDCP_DUAL_P0_15_L       (REG_HDCP_DUAL_P0_BASE + 0x2A)
#define REG_HDCP_DUAL_P0_15_H       (REG_HDCP_DUAL_P0_BASE + 0x2B)
#define REG_HDCP_DUAL_P0_16_L       (REG_HDCP_DUAL_P0_BASE + 0x2C)
#define REG_HDCP_DUAL_P0_16_H       (REG_HDCP_DUAL_P0_BASE + 0x2D)
#define REG_HDCP_DUAL_P0_17_L       (REG_HDCP_DUAL_P0_BASE + 0x2E)
#define REG_HDCP_DUAL_P0_17_H       (REG_HDCP_DUAL_P0_BASE + 0x2F)
#define REG_HDCP_DUAL_P0_18_L       (REG_HDCP_DUAL_P0_BASE + 0x30)
#define REG_HDCP_DUAL_P0_18_H       (REG_HDCP_DUAL_P0_BASE + 0x31)
#define REG_HDCP_DUAL_P0_19_L       (REG_HDCP_DUAL_P0_BASE + 0x32)
#define REG_HDCP_DUAL_P0_19_H       (REG_HDCP_DUAL_P0_BASE + 0x33)
#define REG_HDCP_DUAL_P0_1A_L       (REG_HDCP_DUAL_P0_BASE + 0x34)
#define REG_HDCP_DUAL_P0_1A_H       (REG_HDCP_DUAL_P0_BASE + 0x35)
#define REG_HDCP_DUAL_P0_1B_L       (REG_HDCP_DUAL_P0_BASE + 0x36)
#define REG_HDCP_DUAL_P0_1B_H       (REG_HDCP_DUAL_P0_BASE + 0x37)
#define REG_HDCP_DUAL_P0_1C_L       (REG_HDCP_DUAL_P0_BASE + 0x38)
#define REG_HDCP_DUAL_P0_1C_H       (REG_HDCP_DUAL_P0_BASE + 0x39)
#define REG_HDCP_DUAL_P0_1D_L       (REG_HDCP_DUAL_P0_BASE + 0x3A)
#define REG_HDCP_DUAL_P0_1D_H       (REG_HDCP_DUAL_P0_BASE + 0x3B)
#define REG_HDCP_DUAL_P0_1E_L       (REG_HDCP_DUAL_P0_BASE + 0x3C)
#define REG_HDCP_DUAL_P0_1E_H       (REG_HDCP_DUAL_P0_BASE + 0x3D)
#define REG_HDCP_DUAL_P0_1F_L       (REG_HDCP_DUAL_P0_BASE + 0x3E)
#define REG_HDCP_DUAL_P0_1F_H       (REG_HDCP_DUAL_P0_BASE + 0x3F)
#define REG_HDCP_DUAL_P0_20_L       (REG_HDCP_DUAL_P0_BASE + 0x40)
#define REG_HDCP_DUAL_P0_20_H       (REG_HDCP_DUAL_P0_BASE + 0x41)
#define REG_HDCP_DUAL_P0_21_L       (REG_HDCP_DUAL_P0_BASE + 0x42)
#define REG_HDCP_DUAL_P0_21_H       (REG_HDCP_DUAL_P0_BASE + 0x43)
#define REG_HDCP_DUAL_P0_22_L       (REG_HDCP_DUAL_P0_BASE + 0x44)
#define REG_HDCP_DUAL_P0_22_H       (REG_HDCP_DUAL_P0_BASE + 0x45)
#define REG_HDCP_DUAL_P0_23_L       (REG_HDCP_DUAL_P0_BASE + 0x46)
#define REG_HDCP_DUAL_P0_23_H       (REG_HDCP_DUAL_P0_BASE + 0x47)
#define REG_HDCP_DUAL_P0_24_L       (REG_HDCP_DUAL_P0_BASE + 0x48)
#define REG_HDCP_DUAL_P0_24_H       (REG_HDCP_DUAL_P0_BASE + 0x49)
#define REG_HDCP_DUAL_P0_25_L       (REG_HDCP_DUAL_P0_BASE + 0x4A)
#define REG_HDCP_DUAL_P0_25_H       (REG_HDCP_DUAL_P0_BASE + 0x4B)
#define REG_HDCP_DUAL_P0_26_L       (REG_HDCP_DUAL_P0_BASE + 0x4C)
#define REG_HDCP_DUAL_P0_26_H       (REG_HDCP_DUAL_P0_BASE + 0x4D)
#define REG_HDCP_DUAL_P0_27_L       (REG_HDCP_DUAL_P0_BASE + 0x4E)
#define REG_HDCP_DUAL_P0_27_H       (REG_HDCP_DUAL_P0_BASE + 0x4F)
#define REG_HDCP_DUAL_P0_28_L       (REG_HDCP_DUAL_P0_BASE + 0x50)
#define REG_HDCP_DUAL_P0_28_H       (REG_HDCP_DUAL_P0_BASE + 0x51)
#define REG_HDCP_DUAL_P0_29_L       (REG_HDCP_DUAL_P0_BASE + 0x52)
#define REG_HDCP_DUAL_P0_29_H       (REG_HDCP_DUAL_P0_BASE + 0x53)
#define REG_HDCP_DUAL_P0_2A_L       (REG_HDCP_DUAL_P0_BASE + 0x54)
#define REG_HDCP_DUAL_P0_2A_H       (REG_HDCP_DUAL_P0_BASE + 0x55)
#define REG_HDCP_DUAL_P0_2B_L       (REG_HDCP_DUAL_P0_BASE + 0x56)
#define REG_HDCP_DUAL_P0_2B_H       (REG_HDCP_DUAL_P0_BASE + 0x57)
#define REG_HDCP_DUAL_P0_2C_L       (REG_HDCP_DUAL_P0_BASE + 0x58)
#define REG_HDCP_DUAL_P0_2C_H       (REG_HDCP_DUAL_P0_BASE + 0x59)
#define REG_HDCP_DUAL_P0_2D_L       (REG_HDCP_DUAL_P0_BASE + 0x5A)
#define REG_HDCP_DUAL_P0_2D_H       (REG_HDCP_DUAL_P0_BASE + 0x5B)
#define REG_HDCP_DUAL_P0_2E_L       (REG_HDCP_DUAL_P0_BASE + 0x5C)
#define REG_HDCP_DUAL_P0_2E_H       (REG_HDCP_DUAL_P0_BASE + 0x5D)
#define REG_HDCP_DUAL_P0_2F_L       (REG_HDCP_DUAL_P0_BASE + 0x5E)
#define REG_HDCP_DUAL_P0_2F_H       (REG_HDCP_DUAL_P0_BASE + 0x5F)
#define REG_HDCP_DUAL_P0_30_L       (REG_HDCP_DUAL_P0_BASE + 0x60)
#define REG_HDCP_DUAL_P0_30_H       (REG_HDCP_DUAL_P0_BASE + 0x61)
#define REG_HDCP_DUAL_P0_31_L       (REG_HDCP_DUAL_P0_BASE + 0x62)
#define REG_HDCP_DUAL_P0_31_H       (REG_HDCP_DUAL_P0_BASE + 0x63)
#define REG_HDCP_DUAL_P0_32_L       (REG_HDCP_DUAL_P0_BASE + 0x64)
#define REG_HDCP_DUAL_P0_32_H       (REG_HDCP_DUAL_P0_BASE + 0x65)
#define REG_HDCP_DUAL_P0_33_L       (REG_HDCP_DUAL_P0_BASE + 0x66)
#define REG_HDCP_DUAL_P0_33_H       (REG_HDCP_DUAL_P0_BASE + 0x67)
#define REG_HDCP_DUAL_P0_34_L       (REG_HDCP_DUAL_P0_BASE + 0x68)
#define REG_HDCP_DUAL_P0_34_H       (REG_HDCP_DUAL_P0_BASE + 0x69)
#define REG_HDCP_DUAL_P0_35_L       (REG_HDCP_DUAL_P0_BASE + 0x6A)
#define REG_HDCP_DUAL_P0_35_H       (REG_HDCP_DUAL_P0_BASE + 0x6B)
#define REG_HDCP_DUAL_P0_36_L       (REG_HDCP_DUAL_P0_BASE + 0x6C)
#define REG_HDCP_DUAL_P0_36_H       (REG_HDCP_DUAL_P0_BASE + 0x6D)
#define REG_HDCP_DUAL_P0_37_L       (REG_HDCP_DUAL_P0_BASE + 0x6E)
#define REG_HDCP_DUAL_P0_37_H       (REG_HDCP_DUAL_P0_BASE + 0x6F)
#define REG_HDCP_DUAL_P0_38_L       (REG_HDCP_DUAL_P0_BASE + 0x70)
#define REG_HDCP_DUAL_P0_38_H       (REG_HDCP_DUAL_P0_BASE + 0x71)
#define REG_HDCP_DUAL_P0_39_L       (REG_HDCP_DUAL_P0_BASE + 0x72)
#define REG_HDCP_DUAL_P0_39_H       (REG_HDCP_DUAL_P0_BASE + 0x73)
#define REG_HDCP_DUAL_P0_3A_L       (REG_HDCP_DUAL_P0_BASE + 0x74)
#define REG_HDCP_DUAL_P0_3A_H       (REG_HDCP_DUAL_P0_BASE + 0x75)
#define REG_HDCP_DUAL_P0_3B_L       (REG_HDCP_DUAL_P0_BASE + 0x76)
#define REG_HDCP_DUAL_P0_3B_H       (REG_HDCP_DUAL_P0_BASE + 0x77)
#define REG_HDCP_DUAL_P0_3C_L       (REG_HDCP_DUAL_P0_BASE + 0x78)
#define REG_HDCP_DUAL_P0_3C_H       (REG_HDCP_DUAL_P0_BASE + 0x79)
#define REG_HDCP_DUAL_P0_3D_L       (REG_HDCP_DUAL_P0_BASE + 0x7A)
#define REG_HDCP_DUAL_P0_3D_H       (REG_HDCP_DUAL_P0_BASE + 0x7B)
#define REG_HDCP_DUAL_P0_3E_L       (REG_HDCP_DUAL_P0_BASE + 0x7C)
#define REG_HDCP_DUAL_P0_3E_H       (REG_HDCP_DUAL_P0_BASE + 0x7D)
#define REG_HDCP_DUAL_P0_3F_L       (REG_HDCP_DUAL_P0_BASE + 0x7E)
#define REG_HDCP_DUAL_P0_3F_H       (REG_HDCP_DUAL_P0_BASE + 0x7F)
#define REG_HDCP_DUAL_P0_40_L       (REG_HDCP_DUAL_P0_BASE + 0x80)
#define REG_HDCP_DUAL_P0_40_H       (REG_HDCP_DUAL_P0_BASE + 0x81)
#define REG_HDCP_DUAL_P0_41_L       (REG_HDCP_DUAL_P0_BASE + 0x82)
#define REG_HDCP_DUAL_P0_41_H       (REG_HDCP_DUAL_P0_BASE + 0x83)
#define REG_HDCP_DUAL_P0_42_L       (REG_HDCP_DUAL_P0_BASE + 0x84)
#define REG_HDCP_DUAL_P0_42_H       (REG_HDCP_DUAL_P0_BASE + 0x85)
#define REG_HDCP_DUAL_P0_43_L       (REG_HDCP_DUAL_P0_BASE + 0x86)
#define REG_HDCP_DUAL_P0_43_H       (REG_HDCP_DUAL_P0_BASE + 0x87)
#define REG_HDCP_DUAL_P0_44_L       (REG_HDCP_DUAL_P0_BASE + 0x88)
#define REG_HDCP_DUAL_P0_44_H       (REG_HDCP_DUAL_P0_BASE + 0x89)
#define REG_HDCP_DUAL_P0_45_L       (REG_HDCP_DUAL_P0_BASE + 0x8A)
#define REG_HDCP_DUAL_P0_45_H       (REG_HDCP_DUAL_P0_BASE + 0x8B)
#define REG_HDCP_DUAL_P0_46_L       (REG_HDCP_DUAL_P0_BASE + 0x8C)
#define REG_HDCP_DUAL_P0_46_H       (REG_HDCP_DUAL_P0_BASE + 0x8D)
#define REG_HDCP_DUAL_P0_47_L       (REG_HDCP_DUAL_P0_BASE + 0x8E)
#define REG_HDCP_DUAL_P0_47_H       (REG_HDCP_DUAL_P0_BASE + 0x8F)
#define REG_HDCP_DUAL_P0_48_L       (REG_HDCP_DUAL_P0_BASE + 0x90)
#define REG_HDCP_DUAL_P0_48_H       (REG_HDCP_DUAL_P0_BASE + 0x91)
#define REG_HDCP_DUAL_P0_49_L       (REG_HDCP_DUAL_P0_BASE + 0x92)
#define REG_HDCP_DUAL_P0_49_H       (REG_HDCP_DUAL_P0_BASE + 0x93)
#define REG_HDCP_DUAL_P0_4A_L       (REG_HDCP_DUAL_P0_BASE + 0x94)
#define REG_HDCP_DUAL_P0_4A_H       (REG_HDCP_DUAL_P0_BASE + 0x95)
#define REG_HDCP_DUAL_P0_4B_L       (REG_HDCP_DUAL_P0_BASE + 0x96)
#define REG_HDCP_DUAL_P0_4B_H       (REG_HDCP_DUAL_P0_BASE + 0x97)
#define REG_HDCP_DUAL_P0_4C_L       (REG_HDCP_DUAL_P0_BASE + 0x98)
#define REG_HDCP_DUAL_P0_4C_H       (REG_HDCP_DUAL_P0_BASE + 0x99)
#define REG_HDCP_DUAL_P0_4D_L       (REG_HDCP_DUAL_P0_BASE + 0x9A)
#define REG_HDCP_DUAL_P0_4D_H       (REG_HDCP_DUAL_P0_BASE + 0x9B)
#define REG_HDCP_DUAL_P0_4E_L       (REG_HDCP_DUAL_P0_BASE + 0x9C)
#define REG_HDCP_DUAL_P0_4E_H       (REG_HDCP_DUAL_P0_BASE + 0x9D)
#define REG_HDCP_DUAL_P0_4F_L       (REG_HDCP_DUAL_P0_BASE + 0x9E)
#define REG_HDCP_DUAL_P0_4F_H       (REG_HDCP_DUAL_P0_BASE + 0x9F)
#define REG_HDCP_DUAL_P0_50_L       (REG_HDCP_DUAL_P0_BASE + 0xA0)
#define REG_HDCP_DUAL_P0_50_H       (REG_HDCP_DUAL_P0_BASE + 0xA1)
#define REG_HDCP_DUAL_P0_51_L       (REG_HDCP_DUAL_P0_BASE + 0xA2)
#define REG_HDCP_DUAL_P0_51_H       (REG_HDCP_DUAL_P0_BASE + 0xA3)
#define REG_HDCP_DUAL_P0_52_L       (REG_HDCP_DUAL_P0_BASE + 0xA4)
#define REG_HDCP_DUAL_P0_52_H       (REG_HDCP_DUAL_P0_BASE + 0xA5)
#define REG_HDCP_DUAL_P0_53_L       (REG_HDCP_DUAL_P0_BASE + 0xA6)
#define REG_HDCP_DUAL_P0_53_H       (REG_HDCP_DUAL_P0_BASE + 0xA7)
#define REG_HDCP_DUAL_P0_54_L       (REG_HDCP_DUAL_P0_BASE + 0xA8)
#define REG_HDCP_DUAL_P0_54_H       (REG_HDCP_DUAL_P0_BASE + 0xA9)
#define REG_HDCP_DUAL_P0_55_L       (REG_HDCP_DUAL_P0_BASE + 0xAA)
#define REG_HDCP_DUAL_P0_55_H       (REG_HDCP_DUAL_P0_BASE + 0xAB)
#define REG_HDCP_DUAL_P0_56_L       (REG_HDCP_DUAL_P0_BASE + 0xAC)
#define REG_HDCP_DUAL_P0_56_H       (REG_HDCP_DUAL_P0_BASE + 0xAD)
#define REG_HDCP_DUAL_P0_57_L       (REG_HDCP_DUAL_P0_BASE + 0xAE)
#define REG_HDCP_DUAL_P0_57_H       (REG_HDCP_DUAL_P0_BASE + 0xAF)
#define REG_HDCP_DUAL_P0_58_L       (REG_HDCP_DUAL_P0_BASE + 0xB0)
#define REG_HDCP_DUAL_P0_58_H       (REG_HDCP_DUAL_P0_BASE + 0xB1)
#define REG_HDCP_DUAL_P0_59_L       (REG_HDCP_DUAL_P0_BASE + 0xB2)
#define REG_HDCP_DUAL_P0_59_H       (REG_HDCP_DUAL_P0_BASE + 0xB3)
#define REG_HDCP_DUAL_P0_5A_L       (REG_HDCP_DUAL_P0_BASE + 0xB4)
#define REG_HDCP_DUAL_P0_5A_H       (REG_HDCP_DUAL_P0_BASE + 0xB5)
#define REG_HDCP_DUAL_P0_5B_L       (REG_HDCP_DUAL_P0_BASE + 0xB6)
#define REG_HDCP_DUAL_P0_5B_H       (REG_HDCP_DUAL_P0_BASE + 0xB7)
#define REG_HDCP_DUAL_P0_5C_L       (REG_HDCP_DUAL_P0_BASE + 0xB8)
#define REG_HDCP_DUAL_P0_5C_H       (REG_HDCP_DUAL_P0_BASE + 0xB9)
#define REG_HDCP_DUAL_P0_5D_L       (REG_HDCP_DUAL_P0_BASE + 0xBA)
#define REG_HDCP_DUAL_P0_5D_H       (REG_HDCP_DUAL_P0_BASE + 0xBB)
#define REG_HDCP_DUAL_P0_5E_L       (REG_HDCP_DUAL_P0_BASE + 0xBC)
#define REG_HDCP_DUAL_P0_5E_H       (REG_HDCP_DUAL_P0_BASE + 0xBD)
#define REG_HDCP_DUAL_P0_5F_L       (REG_HDCP_DUAL_P0_BASE + 0xBE)
#define REG_HDCP_DUAL_P0_5F_H       (REG_HDCP_DUAL_P0_BASE + 0xBF)
#define REG_HDCP_DUAL_P0_60_L       (REG_HDCP_DUAL_P0_BASE + 0xC0)
#define REG_HDCP_DUAL_P0_60_H       (REG_HDCP_DUAL_P0_BASE + 0xC1)
#define REG_HDCP_DUAL_P0_61_L       (REG_HDCP_DUAL_P0_BASE + 0xC2)
#define REG_HDCP_DUAL_P0_61_H       (REG_HDCP_DUAL_P0_BASE + 0xC3)
#define REG_HDCP_DUAL_P0_62_L       (REG_HDCP_DUAL_P0_BASE + 0xC4)
#define REG_HDCP_DUAL_P0_62_H       (REG_HDCP_DUAL_P0_BASE + 0xC5)
#define REG_HDCP_DUAL_P0_63_L       (REG_HDCP_DUAL_P0_BASE + 0xC6)
#define REG_HDCP_DUAL_P0_63_H       (REG_HDCP_DUAL_P0_BASE + 0xC7)
#define REG_HDCP_DUAL_P0_64_L       (REG_HDCP_DUAL_P0_BASE + 0xC8)
#define REG_HDCP_DUAL_P0_64_H       (REG_HDCP_DUAL_P0_BASE + 0xC9)
#define REG_HDCP_DUAL_P0_65_L       (REG_HDCP_DUAL_P0_BASE + 0xCA)
#define REG_HDCP_DUAL_P0_65_H       (REG_HDCP_DUAL_P0_BASE + 0xCB)
#define REG_HDCP_DUAL_P0_66_L       (REG_HDCP_DUAL_P0_BASE + 0xCC)
#define REG_HDCP_DUAL_P0_66_H       (REG_HDCP_DUAL_P0_BASE + 0xCD)
#define REG_HDCP_DUAL_P0_67_L       (REG_HDCP_DUAL_P0_BASE + 0xCE)
#define REG_HDCP_DUAL_P0_67_H       (REG_HDCP_DUAL_P0_BASE + 0xCF)
#define REG_HDCP_DUAL_P0_68_L       (REG_HDCP_DUAL_P0_BASE + 0xD0)
#define REG_HDCP_DUAL_P0_68_H       (REG_HDCP_DUAL_P0_BASE + 0xD1)

// DVI_DTOP_DUAL_P1
#define REG_DVI_DTOP_DUAL_P1_00_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x00)
#define REG_DVI_DTOP_DUAL_P1_00_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x01)
#define REG_DVI_DTOP_DUAL_P1_01_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x02)
#define REG_DVI_DTOP_DUAL_P1_01_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x03)
#define REG_DVI_DTOP_DUAL_P1_02_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x04)
#define REG_DVI_DTOP_DUAL_P1_02_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x05)
#define REG_DVI_DTOP_DUAL_P1_03_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x06)
#define REG_DVI_DTOP_DUAL_P1_03_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x07)
#define REG_DVI_DTOP_DUAL_P1_04_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x08)
#define REG_DVI_DTOP_DUAL_P1_04_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x09)
#define REG_DVI_DTOP_DUAL_P1_05_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0A)
#define REG_DVI_DTOP_DUAL_P1_05_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0B)
#define REG_DVI_DTOP_DUAL_P1_06_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0C)
#define REG_DVI_DTOP_DUAL_P1_06_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0D)
#define REG_DVI_DTOP_DUAL_P1_07_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0E)
#define REG_DVI_DTOP_DUAL_P1_07_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0F)
#define REG_DVI_DTOP_DUAL_P1_08_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x10)
#define REG_DVI_DTOP_DUAL_P1_08_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x11)
#define REG_DVI_DTOP_DUAL_P1_09_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x12)
#define REG_DVI_DTOP_DUAL_P1_09_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x13)
#define REG_DVI_DTOP_DUAL_P1_0A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x14)
#define REG_DVI_DTOP_DUAL_P1_0A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x15)
#define REG_DVI_DTOP_DUAL_P1_0B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x16)
#define REG_DVI_DTOP_DUAL_P1_0B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x17)
#define REG_DVI_DTOP_DUAL_P1_0C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x18)
#define REG_DVI_DTOP_DUAL_P1_0C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x19)
#define REG_DVI_DTOP_DUAL_P1_0D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1A)
#define REG_DVI_DTOP_DUAL_P1_0D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1B)
#define REG_DVI_DTOP_DUAL_P1_0E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1C)
#define REG_DVI_DTOP_DUAL_P1_0E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1D)
#define REG_DVI_DTOP_DUAL_P1_0F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1E)
#define REG_DVI_DTOP_DUAL_P1_0F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1F)
#define REG_DVI_DTOP_DUAL_P1_10_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x20)
#define REG_DVI_DTOP_DUAL_P1_10_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x21)
#define REG_DVI_DTOP_DUAL_P1_11_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x22)
#define REG_DVI_DTOP_DUAL_P1_11_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x23)
#define REG_DVI_DTOP_DUAL_P1_12_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x24)
#define REG_DVI_DTOP_DUAL_P1_12_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x25)
#define REG_DVI_DTOP_DUAL_P1_13_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x26)
#define REG_DVI_DTOP_DUAL_P1_13_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x27)
#define REG_DVI_DTOP_DUAL_P1_14_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x28)
#define REG_DVI_DTOP_DUAL_P1_14_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x29)
#define REG_DVI_DTOP_DUAL_P1_15_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2A)
#define REG_DVI_DTOP_DUAL_P1_15_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2B)
#define REG_DVI_DTOP_DUAL_P1_16_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2C)
#define REG_DVI_DTOP_DUAL_P1_16_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2D)
#define REG_DVI_DTOP_DUAL_P1_17_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2E)
#define REG_DVI_DTOP_DUAL_P1_17_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2F)
#define REG_DVI_DTOP_DUAL_P1_18_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x30)
#define REG_DVI_DTOP_DUAL_P1_18_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x31)
#define REG_DVI_DTOP_DUAL_P1_19_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x32)
#define REG_DVI_DTOP_DUAL_P1_19_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x33)
#define REG_DVI_DTOP_DUAL_P1_1A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x34)
#define REG_DVI_DTOP_DUAL_P1_1A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x35)
#define REG_DVI_DTOP_DUAL_P1_1B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x36)
#define REG_DVI_DTOP_DUAL_P1_1B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x37)
#define REG_DVI_DTOP_DUAL_P1_1C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x38)
#define REG_DVI_DTOP_DUAL_P1_1C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x39)
#define REG_DVI_DTOP_DUAL_P1_1D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3A)
#define REG_DVI_DTOP_DUAL_P1_1D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3B)
#define REG_DVI_DTOP_DUAL_P1_1E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3C)
#define REG_DVI_DTOP_DUAL_P1_1E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3D)
#define REG_DVI_DTOP_DUAL_P1_1F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3E)
#define REG_DVI_DTOP_DUAL_P1_1F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3F)
#define REG_DVI_DTOP_DUAL_P1_20_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x40)
#define REG_DVI_DTOP_DUAL_P1_20_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x41)
#define REG_DVI_DTOP_DUAL_P1_21_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x42)
#define REG_DVI_DTOP_DUAL_P1_21_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x43)
#define REG_DVI_DTOP_DUAL_P1_22_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x44)
#define REG_DVI_DTOP_DUAL_P1_22_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x45)
#define REG_DVI_DTOP_DUAL_P1_23_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x46)
#define REG_DVI_DTOP_DUAL_P1_23_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x47)
#define REG_DVI_DTOP_DUAL_P1_24_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x48)
#define REG_DVI_DTOP_DUAL_P1_24_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x49)
#define REG_DVI_DTOP_DUAL_P1_25_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4A)
#define REG_DVI_DTOP_DUAL_P1_25_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4B)
#define REG_DVI_DTOP_DUAL_P1_26_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4C)
#define REG_DVI_DTOP_DUAL_P1_26_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4D)
#define REG_DVI_DTOP_DUAL_P1_27_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4E)
#define REG_DVI_DTOP_DUAL_P1_27_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4F)
#define REG_DVI_DTOP_DUAL_P1_28_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x50)
#define REG_DVI_DTOP_DUAL_P1_28_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x51)
#define REG_DVI_DTOP_DUAL_P1_29_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x52)
#define REG_DVI_DTOP_DUAL_P1_29_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x53)
#define REG_DVI_DTOP_DUAL_P1_2A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x54)
#define REG_DVI_DTOP_DUAL_P1_2A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x55)
#define REG_DVI_DTOP_DUAL_P1_2B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x56)
#define REG_DVI_DTOP_DUAL_P1_2B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x57)
#define REG_DVI_DTOP_DUAL_P1_2C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x58)
#define REG_DVI_DTOP_DUAL_P1_2C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x59)
#define REG_DVI_DTOP_DUAL_P1_2D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5A)
#define REG_DVI_DTOP_DUAL_P1_2D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5B)
#define REG_DVI_DTOP_DUAL_P1_2E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5C)
#define REG_DVI_DTOP_DUAL_P1_2E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5D)
#define REG_DVI_DTOP_DUAL_P1_2F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5E)
#define REG_DVI_DTOP_DUAL_P1_2F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5F)
#define REG_DVI_DTOP_DUAL_P1_30_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x60)
#define REG_DVI_DTOP_DUAL_P1_30_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x61)
#define REG_DVI_DTOP_DUAL_P1_31_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x62)
#define REG_DVI_DTOP_DUAL_P1_31_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x63)
#define REG_DVI_DTOP_DUAL_P1_32_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x64)
#define REG_DVI_DTOP_DUAL_P1_32_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x65)
#define REG_DVI_DTOP_DUAL_P1_33_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x66)
#define REG_DVI_DTOP_DUAL_P1_33_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x67)
#define REG_DVI_DTOP_DUAL_P1_34_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x68)
#define REG_DVI_DTOP_DUAL_P1_34_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x69)
#define REG_DVI_DTOP_DUAL_P1_35_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6A)
#define REG_DVI_DTOP_DUAL_P1_35_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6B)
#define REG_DVI_DTOP_DUAL_P1_36_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6C)
#define REG_DVI_DTOP_DUAL_P1_36_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6D)
#define REG_DVI_DTOP_DUAL_P1_37_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6E)
#define REG_DVI_DTOP_DUAL_P1_37_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6F)
#define REG_DVI_DTOP_DUAL_P1_38_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x70)
#define REG_DVI_DTOP_DUAL_P1_38_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x71)
#define REG_DVI_DTOP_DUAL_P1_39_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x72)
#define REG_DVI_DTOP_DUAL_P1_39_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x73)
#define REG_DVI_DTOP_DUAL_P1_3A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x74)
#define REG_DVI_DTOP_DUAL_P1_3A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x75)
#define REG_DVI_DTOP_DUAL_P1_3B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x76)
#define REG_DVI_DTOP_DUAL_P1_3B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x77)
#define REG_DVI_DTOP_DUAL_P1_3C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x78)
#define REG_DVI_DTOP_DUAL_P1_3C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x79)
#define REG_DVI_DTOP_DUAL_P1_3D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7A)
#define REG_DVI_DTOP_DUAL_P1_3D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7B)
#define REG_DVI_DTOP_DUAL_P1_3E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7C)
#define REG_DVI_DTOP_DUAL_P1_3E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7D)
#define REG_DVI_DTOP_DUAL_P1_3F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7E)
#define REG_DVI_DTOP_DUAL_P1_3F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7F)
#define REG_DVI_DTOP_DUAL_P1_40_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x80)
#define REG_DVI_DTOP_DUAL_P1_40_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x81)
#define REG_DVI_DTOP_DUAL_P1_41_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x82)
#define REG_DVI_DTOP_DUAL_P1_41_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x83)
#define REG_DVI_DTOP_DUAL_P1_42_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x84)
#define REG_DVI_DTOP_DUAL_P1_42_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x85)
#define REG_DVI_DTOP_DUAL_P1_43_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x86)
#define REG_DVI_DTOP_DUAL_P1_43_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x87)
#define REG_DVI_DTOP_DUAL_P1_44_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x88)
#define REG_DVI_DTOP_DUAL_P1_44_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x89)
#define REG_DVI_DTOP_DUAL_P1_45_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8A)
#define REG_DVI_DTOP_DUAL_P1_45_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8B)
#define REG_DVI_DTOP_DUAL_P1_46_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8C)
#define REG_DVI_DTOP_DUAL_P1_46_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8D)
#define REG_DVI_DTOP_DUAL_P1_47_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8E)
#define REG_DVI_DTOP_DUAL_P1_47_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8F)
#define REG_DVI_DTOP_DUAL_P1_48_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x90)
#define REG_DVI_DTOP_DUAL_P1_48_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x91)
#define REG_DVI_DTOP_DUAL_P1_49_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x92)
#define REG_DVI_DTOP_DUAL_P1_49_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x93)
#define REG_DVI_DTOP_DUAL_P1_4A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x94)
#define REG_DVI_DTOP_DUAL_P1_4A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x95)
#define REG_DVI_DTOP_DUAL_P1_4B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x96)
#define REG_DVI_DTOP_DUAL_P1_4B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x97)
#define REG_DVI_DTOP_DUAL_P1_4C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x98)
#define REG_DVI_DTOP_DUAL_P1_4C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x99)
#define REG_DVI_DTOP_DUAL_P1_4D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9A)
#define REG_DVI_DTOP_DUAL_P1_4D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9B)
#define REG_DVI_DTOP_DUAL_P1_4E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9C)
#define REG_DVI_DTOP_DUAL_P1_4E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9D)
#define REG_DVI_DTOP_DUAL_P1_4F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9E)
#define REG_DVI_DTOP_DUAL_P1_4F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9F)
#define REG_DVI_DTOP_DUAL_P1_50_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA0)
#define REG_DVI_DTOP_DUAL_P1_50_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA1)
#define REG_DVI_DTOP_DUAL_P1_51_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA2)
#define REG_DVI_DTOP_DUAL_P1_51_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA3)
#define REG_DVI_DTOP_DUAL_P1_52_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA4)
#define REG_DVI_DTOP_DUAL_P1_52_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA5)
#define REG_DVI_DTOP_DUAL_P1_53_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA6)
#define REG_DVI_DTOP_DUAL_P1_53_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA7)
#define REG_DVI_DTOP_DUAL_P1_54_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA8)
#define REG_DVI_DTOP_DUAL_P1_54_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA9)
#define REG_DVI_DTOP_DUAL_P1_55_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAA)
#define REG_DVI_DTOP_DUAL_P1_55_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAB)
#define REG_DVI_DTOP_DUAL_P1_56_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAC)
#define REG_DVI_DTOP_DUAL_P1_56_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAD)
#define REG_DVI_DTOP_DUAL_P1_57_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAE)
#define REG_DVI_DTOP_DUAL_P1_57_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAF)
#define REG_DVI_DTOP_DUAL_P1_58_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB0)
#define REG_DVI_DTOP_DUAL_P1_58_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB1)
#define REG_DVI_DTOP_DUAL_P1_59_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB2)
#define REG_DVI_DTOP_DUAL_P1_59_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB3)
#define REG_DVI_DTOP_DUAL_P1_5A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB4)
#define REG_DVI_DTOP_DUAL_P1_5A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB5)
#define REG_DVI_DTOP_DUAL_P1_5B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB6)
#define REG_DVI_DTOP_DUAL_P1_5B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB7)
#define REG_DVI_DTOP_DUAL_P1_5C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB8)
#define REG_DVI_DTOP_DUAL_P1_5C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB9)
#define REG_DVI_DTOP_DUAL_P1_5D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBA)
#define REG_DVI_DTOP_DUAL_P1_5D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBB)
#define REG_DVI_DTOP_DUAL_P1_5E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBC)
#define REG_DVI_DTOP_DUAL_P1_5E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBD)
#define REG_DVI_DTOP_DUAL_P1_5F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBE)
#define REG_DVI_DTOP_DUAL_P1_5F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBF)
#define REG_DVI_DTOP_DUAL_P1_60_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC0)
#define REG_DVI_DTOP_DUAL_P1_60_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC1)
#define REG_DVI_DTOP_DUAL_P1_61_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC2)
#define REG_DVI_DTOP_DUAL_P1_61_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC3)
#define REG_DVI_DTOP_DUAL_P1_62_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC4)
#define REG_DVI_DTOP_DUAL_P1_62_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC5)
#define REG_DVI_DTOP_DUAL_P1_63_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6)
#define REG_DVI_DTOP_DUAL_P1_63_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC7)
#define REG_DVI_DTOP_DUAL_P1_64_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC8)
#define REG_DVI_DTOP_DUAL_P1_64_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC9)
#define REG_DVI_DTOP_DUAL_P1_65_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCA)
#define REG_DVI_DTOP_DUAL_P1_65_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCB)
#define REG_DVI_DTOP_DUAL_P1_66_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCC)
#define REG_DVI_DTOP_DUAL_P1_66_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCD)
#define REG_DVI_DTOP_DUAL_P1_67_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCE)
#define REG_DVI_DTOP_DUAL_P1_67_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCF)
#define REG_DVI_DTOP_DUAL_P1_68_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD0)
#define REG_DVI_DTOP_DUAL_P1_68_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD1)
#define REG_DVI_DTOP_DUAL_P1_69_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD2)
#define REG_DVI_DTOP_DUAL_P1_69_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD3)
#define REG_DVI_DTOP_DUAL_P1_6A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD4)
#define REG_DVI_DTOP_DUAL_P1_6A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD5)
#define REG_DVI_DTOP_DUAL_P1_6B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD6)
#define REG_DVI_DTOP_DUAL_P1_6B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD7)
#define REG_DVI_DTOP_DUAL_P1_6C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD8)
#define REG_DVI_DTOP_DUAL_P1_6C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD9)
#define REG_DVI_DTOP_DUAL_P1_6D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDA)
#define REG_DVI_DTOP_DUAL_P1_6D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDB)
#define REG_DVI_DTOP_DUAL_P1_6E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDC)
#define REG_DVI_DTOP_DUAL_P1_6E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDD)
#define REG_DVI_DTOP_DUAL_P1_6F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDE)
#define REG_DVI_DTOP_DUAL_P1_6F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDF)
#define REG_DVI_DTOP_DUAL_P1_70_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE0)
#define REG_DVI_DTOP_DUAL_P1_70_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE1)
#define REG_DVI_DTOP_DUAL_P1_71_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE2)
#define REG_DVI_DTOP_DUAL_P1_71_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE3)
#define REG_DVI_DTOP_DUAL_P1_72_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE4)
#define REG_DVI_DTOP_DUAL_P1_72_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE5)
#define REG_DVI_DTOP_DUAL_P1_73_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE6)
#define REG_DVI_DTOP_DUAL_P1_73_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE7)
#define REG_DVI_DTOP_DUAL_P1_74_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE8)
#define REG_DVI_DTOP_DUAL_P1_74_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE9)
#define REG_DVI_DTOP_DUAL_P1_75_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEA)
#define REG_DVI_DTOP_DUAL_P1_75_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEB)
#define REG_DVI_DTOP_DUAL_P1_76_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEC)
#define REG_DVI_DTOP_DUAL_P1_76_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xED)
#define REG_DVI_DTOP_DUAL_P1_77_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEE)
#define REG_DVI_DTOP_DUAL_P1_77_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEF)
#define REG_DVI_DTOP_DUAL_P1_78_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF0)
#define REG_DVI_DTOP_DUAL_P1_78_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF1)
#define REG_DVI_DTOP_DUAL_P1_79_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF2)
#define REG_DVI_DTOP_DUAL_P1_79_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF3)
#define REG_DVI_DTOP_DUAL_P1_7A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF4)
#define REG_DVI_DTOP_DUAL_P1_7A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF5)
#define REG_DVI_DTOP_DUAL_P1_7B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF6)
#define REG_DVI_DTOP_DUAL_P1_7B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF7)
#define REG_DVI_DTOP_DUAL_P1_7C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF8)
#define REG_DVI_DTOP_DUAL_P1_7C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF9)
#define REG_DVI_DTOP_DUAL_P1_7D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFA)
#define REG_DVI_DTOP_DUAL_P1_7D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFB)
#define REG_DVI_DTOP_DUAL_P1_7E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFC)
#define REG_DVI_DTOP_DUAL_P1_7E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFD)
#define REG_DVI_DTOP_DUAL_P1_7F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFE)
#define REG_DVI_DTOP_DUAL_P1_7F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFF)

// DVI_RSV_DUAL_P1
#define REG_DVI_RSV_DUAL_P1_00_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
#define REG_DVI_RSV_DUAL_P1_00_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
#define REG_DVI_RSV_DUAL_P1_01_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
#define REG_DVI_RSV_DUAL_P1_01_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
#define REG_DVI_RSV_DUAL_P1_02_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
#define REG_DVI_RSV_DUAL_P1_02_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
#define REG_DVI_RSV_DUAL_P1_03_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
#define REG_DVI_RSV_DUAL_P1_03_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
#define REG_DVI_RSV_DUAL_P1_04_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
#define REG_DVI_RSV_DUAL_P1_04_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
#define REG_DVI_RSV_DUAL_P1_05_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0A)
#define REG_DVI_RSV_DUAL_P1_05_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0B)
#define REG_DVI_RSV_DUAL_P1_06_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0C)
#define REG_DVI_RSV_DUAL_P1_06_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0D)
#define REG_DVI_RSV_DUAL_P1_07_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0E)
#define REG_DVI_RSV_DUAL_P1_07_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0F)
#define REG_DVI_RSV_DUAL_P1_08_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x10)
#define REG_DVI_RSV_DUAL_P1_08_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x11)
#define REG_DVI_RSV_DUAL_P1_09_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x12)
#define REG_DVI_RSV_DUAL_P1_09_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x13)
#define REG_DVI_RSV_DUAL_P1_0A_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x14)
#define REG_DVI_RSV_DUAL_P1_0A_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x15)
#define REG_DVI_RSV_DUAL_P1_0B_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x16)
#define REG_DVI_RSV_DUAL_P1_0B_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x17)
#define REG_DVI_RSV_DUAL_P1_0C_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x18)
#define REG_DVI_RSV_DUAL_P1_0C_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x19)
#define REG_DVI_RSV_DUAL_P1_0D_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1A)
#define REG_DVI_RSV_DUAL_P1_0D_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1B)
#define REG_DVI_RSV_DUAL_P1_0E_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1C)
#define REG_DVI_RSV_DUAL_P1_0E_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1D)
#define REG_DVI_RSV_DUAL_P1_0F_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1E)
#define REG_DVI_RSV_DUAL_P1_0F_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1F)
#define REG_DVI_RSV_DUAL_P1_10_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x20)
#define REG_DVI_RSV_DUAL_P1_10_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x21)
#define REG_DVI_RSV_DUAL_P1_11_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x22)
#define REG_DVI_RSV_DUAL_P1_11_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x23)
#define REG_DVI_RSV_DUAL_P1_12_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x24)
#define REG_DVI_RSV_DUAL_P1_12_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x25)
#define REG_DVI_RSV_DUAL_P1_13_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x26)
#define REG_DVI_RSV_DUAL_P1_13_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x27)
#define REG_DVI_RSV_DUAL_P1_14_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x28)
#define REG_DVI_RSV_DUAL_P1_14_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x29)
#define REG_DVI_RSV_DUAL_P1_15_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2A)
#define REG_DVI_RSV_DUAL_P1_15_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2B)
#define REG_DVI_RSV_DUAL_P1_16_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2C)
#define REG_DVI_RSV_DUAL_P1_16_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2D)
#define REG_DVI_RSV_DUAL_P1_17_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2E)
#define REG_DVI_RSV_DUAL_P1_17_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2F)
#define REG_DVI_RSV_DUAL_P1_18_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x30)
#define REG_DVI_RSV_DUAL_P1_18_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x31)
#define REG_DVI_RSV_DUAL_P1_19_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x32)
#define REG_DVI_RSV_DUAL_P1_19_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x33)
#define REG_DVI_RSV_DUAL_P1_1A_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x34)
#define REG_DVI_RSV_DUAL_P1_1A_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x35)
#define REG_DVI_RSV_DUAL_P1_1B_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x36)
#define REG_DVI_RSV_DUAL_P1_1B_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x37)
#define REG_DVI_RSV_DUAL_P1_1C_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x38)
#define REG_DVI_RSV_DUAL_P1_1C_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x39)
#define REG_DVI_RSV_DUAL_P1_1D_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3A)
#define REG_DVI_RSV_DUAL_P1_1D_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3B)
#define REG_DVI_RSV_DUAL_P1_1E_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3C)
#define REG_DVI_RSV_DUAL_P1_1E_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3D)
#define REG_DVI_RSV_DUAL_P1_1F_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3E)
#define REG_DVI_RSV_DUAL_P1_1F_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3F)

// HDCP_DUAL_P1
#define REG_HDCP_DUAL_P1_00_L       (REG_HDCP_DUAL_P1_BASE + 0x00)
#define REG_HDCP_DUAL_P1_00_H       (REG_HDCP_DUAL_P1_BASE + 0x01)
#define REG_HDCP_DUAL_P1_01_L       (REG_HDCP_DUAL_P1_BASE + 0x02)
#define REG_HDCP_DUAL_P1_01_H       (REG_HDCP_DUAL_P1_BASE + 0x03)
#define REG_HDCP_DUAL_P1_02_L       (REG_HDCP_DUAL_P1_BASE + 0x04)
#define REG_HDCP_DUAL_P1_02_H       (REG_HDCP_DUAL_P1_BASE + 0x05)
#define REG_HDCP_DUAL_P1_03_L       (REG_HDCP_DUAL_P1_BASE + 0x06)
#define REG_HDCP_DUAL_P1_03_H       (REG_HDCP_DUAL_P1_BASE + 0x07)
#define REG_HDCP_DUAL_P1_04_L       (REG_HDCP_DUAL_P1_BASE + 0x08)
#define REG_HDCP_DUAL_P1_04_H       (REG_HDCP_DUAL_P1_BASE + 0x09)
#define REG_HDCP_DUAL_P1_05_L       (REG_HDCP_DUAL_P1_BASE + 0x0A)
#define REG_HDCP_DUAL_P1_05_H       (REG_HDCP_DUAL_P1_BASE + 0x0B)
#define REG_HDCP_DUAL_P1_06_L       (REG_HDCP_DUAL_P1_BASE + 0x0C)
#define REG_HDCP_DUAL_P1_06_H       (REG_HDCP_DUAL_P1_BASE + 0x0D)
#define REG_HDCP_DUAL_P1_07_L       (REG_HDCP_DUAL_P1_BASE + 0x0E)
#define REG_HDCP_DUAL_P1_07_H       (REG_HDCP_DUAL_P1_BASE + 0x0F)
#define REG_HDCP_DUAL_P1_08_L       (REG_HDCP_DUAL_P1_BASE + 0x10)
#define REG_HDCP_DUAL_P1_08_H       (REG_HDCP_DUAL_P1_BASE + 0x11)
#define REG_HDCP_DUAL_P1_09_L       (REG_HDCP_DUAL_P1_BASE + 0x12)
#define REG_HDCP_DUAL_P1_09_H       (REG_HDCP_DUAL_P1_BASE + 0x13)
#define REG_HDCP_DUAL_P1_0A_L       (REG_HDCP_DUAL_P1_BASE + 0x14)
#define REG_HDCP_DUAL_P1_0A_H       (REG_HDCP_DUAL_P1_BASE + 0x15)
#define REG_HDCP_DUAL_P1_0B_L       (REG_HDCP_DUAL_P1_BASE + 0x16)
#define REG_HDCP_DUAL_P1_0B_H       (REG_HDCP_DUAL_P1_BASE + 0x17)
#define REG_HDCP_DUAL_P1_0C_L       (REG_HDCP_DUAL_P1_BASE + 0x18)
#define REG_HDCP_DUAL_P1_0C_H       (REG_HDCP_DUAL_P1_BASE + 0x19)
#define REG_HDCP_DUAL_P1_0D_L       (REG_HDCP_DUAL_P1_BASE + 0x1A)
#define REG_HDCP_DUAL_P1_0D_H       (REG_HDCP_DUAL_P1_BASE + 0x1B)
#define REG_HDCP_DUAL_P1_0E_L       (REG_HDCP_DUAL_P1_BASE + 0x1C)
#define REG_HDCP_DUAL_P1_0E_H       (REG_HDCP_DUAL_P1_BASE + 0x1D)
#define REG_HDCP_DUAL_P1_0F_L       (REG_HDCP_DUAL_P1_BASE + 0x1E)
#define REG_HDCP_DUAL_P1_0F_H       (REG_HDCP_DUAL_P1_BASE + 0x1F)
#define REG_HDCP_DUAL_P1_10_L       (REG_HDCP_DUAL_P1_BASE + 0x20)
#define REG_HDCP_DUAL_P1_10_H       (REG_HDCP_DUAL_P1_BASE + 0x21)
#define REG_HDCP_DUAL_P1_11_L       (REG_HDCP_DUAL_P1_BASE + 0x22)
#define REG_HDCP_DUAL_P1_11_H       (REG_HDCP_DUAL_P1_BASE + 0x23)
#define REG_HDCP_DUAL_P1_12_L       (REG_HDCP_DUAL_P1_BASE + 0x24)
#define REG_HDCP_DUAL_P1_12_H       (REG_HDCP_DUAL_P1_BASE + 0x25)
#define REG_HDCP_DUAL_P1_13_L       (REG_HDCP_DUAL_P1_BASE + 0x26)
#define REG_HDCP_DUAL_P1_13_H       (REG_HDCP_DUAL_P1_BASE + 0x27)
#define REG_HDCP_DUAL_P1_14_L       (REG_HDCP_DUAL_P1_BASE + 0x28)
#define REG_HDCP_DUAL_P1_14_H       (REG_HDCP_DUAL_P1_BASE + 0x29)
#define REG_HDCP_DUAL_P1_15_L       (REG_HDCP_DUAL_P1_BASE + 0x2A)
#define REG_HDCP_DUAL_P1_15_H       (REG_HDCP_DUAL_P1_BASE + 0x2B)
#define REG_HDCP_DUAL_P1_16_L       (REG_HDCP_DUAL_P1_BASE + 0x2C)
#define REG_HDCP_DUAL_P1_16_H       (REG_HDCP_DUAL_P1_BASE + 0x2D)
#define REG_HDCP_DUAL_P1_17_L       (REG_HDCP_DUAL_P1_BASE + 0x2E)
#define REG_HDCP_DUAL_P1_17_H       (REG_HDCP_DUAL_P1_BASE + 0x2F)
#define REG_HDCP_DUAL_P1_18_L       (REG_HDCP_DUAL_P1_BASE + 0x30)
#define REG_HDCP_DUAL_P1_18_H       (REG_HDCP_DUAL_P1_BASE + 0x31)
#define REG_HDCP_DUAL_P1_19_L       (REG_HDCP_DUAL_P1_BASE + 0x32)
#define REG_HDCP_DUAL_P1_19_H       (REG_HDCP_DUAL_P1_BASE + 0x33)
#define REG_HDCP_DUAL_P1_1A_L       (REG_HDCP_DUAL_P1_BASE + 0x34)
#define REG_HDCP_DUAL_P1_1A_H       (REG_HDCP_DUAL_P1_BASE + 0x35)
#define REG_HDCP_DUAL_P1_1B_L       (REG_HDCP_DUAL_P1_BASE + 0x36)
#define REG_HDCP_DUAL_P1_1B_H       (REG_HDCP_DUAL_P1_BASE + 0x37)
#define REG_HDCP_DUAL_P1_1C_L       (REG_HDCP_DUAL_P1_BASE + 0x38)
#define REG_HDCP_DUAL_P1_1C_H       (REG_HDCP_DUAL_P1_BASE + 0x39)
#define REG_HDCP_DUAL_P1_1D_L       (REG_HDCP_DUAL_P1_BASE + 0x3A)
#define REG_HDCP_DUAL_P1_1D_H       (REG_HDCP_DUAL_P1_BASE + 0x3B)
#define REG_HDCP_DUAL_P1_1E_L       (REG_HDCP_DUAL_P1_BASE + 0x3C)
#define REG_HDCP_DUAL_P1_1E_H       (REG_HDCP_DUAL_P1_BASE + 0x3D)
#define REG_HDCP_DUAL_P1_1F_L       (REG_HDCP_DUAL_P1_BASE + 0x3E)
#define REG_HDCP_DUAL_P1_1F_H       (REG_HDCP_DUAL_P1_BASE + 0x3F)
#define REG_HDCP_DUAL_P1_20_L       (REG_HDCP_DUAL_P1_BASE + 0x40)
#define REG_HDCP_DUAL_P1_20_H       (REG_HDCP_DUAL_P1_BASE + 0x41)
#define REG_HDCP_DUAL_P1_21_L       (REG_HDCP_DUAL_P1_BASE + 0x42)
#define REG_HDCP_DUAL_P1_21_H       (REG_HDCP_DUAL_P1_BASE + 0x43)
#define REG_HDCP_DUAL_P1_22_L       (REG_HDCP_DUAL_P1_BASE + 0x44)
#define REG_HDCP_DUAL_P1_22_H       (REG_HDCP_DUAL_P1_BASE + 0x45)
#define REG_HDCP_DUAL_P1_23_L       (REG_HDCP_DUAL_P1_BASE + 0x46)
#define REG_HDCP_DUAL_P1_23_H       (REG_HDCP_DUAL_P1_BASE + 0x47)
#define REG_HDCP_DUAL_P1_24_L       (REG_HDCP_DUAL_P1_BASE + 0x48)
#define REG_HDCP_DUAL_P1_24_H       (REG_HDCP_DUAL_P1_BASE + 0x49)
#define REG_HDCP_DUAL_P1_25_L       (REG_HDCP_DUAL_P1_BASE + 0x4A)
#define REG_HDCP_DUAL_P1_25_H       (REG_HDCP_DUAL_P1_BASE + 0x4B)
#define REG_HDCP_DUAL_P1_26_L       (REG_HDCP_DUAL_P1_BASE + 0x4C)
#define REG_HDCP_DUAL_P1_26_H       (REG_HDCP_DUAL_P1_BASE + 0x4D)
#define REG_HDCP_DUAL_P1_27_L       (REG_HDCP_DUAL_P1_BASE + 0x4E)
#define REG_HDCP_DUAL_P1_27_H       (REG_HDCP_DUAL_P1_BASE + 0x4F)
#define REG_HDCP_DUAL_P1_28_L       (REG_HDCP_DUAL_P1_BASE + 0x50)
#define REG_HDCP_DUAL_P1_28_H       (REG_HDCP_DUAL_P1_BASE + 0x51)
#define REG_HDCP_DUAL_P1_29_L       (REG_HDCP_DUAL_P1_BASE + 0x52)
#define REG_HDCP_DUAL_P1_29_H       (REG_HDCP_DUAL_P1_BASE + 0x53)
#define REG_HDCP_DUAL_P1_2A_L       (REG_HDCP_DUAL_P1_BASE + 0x54)
#define REG_HDCP_DUAL_P1_2A_H       (REG_HDCP_DUAL_P1_BASE + 0x55)
#define REG_HDCP_DUAL_P1_2B_L       (REG_HDCP_DUAL_P1_BASE + 0x56)
#define REG_HDCP_DUAL_P1_2B_H       (REG_HDCP_DUAL_P1_BASE + 0x57)
#define REG_HDCP_DUAL_P1_2C_L       (REG_HDCP_DUAL_P1_BASE + 0x58)
#define REG_HDCP_DUAL_P1_2C_H       (REG_HDCP_DUAL_P1_BASE + 0x59)
#define REG_HDCP_DUAL_P1_2D_L       (REG_HDCP_DUAL_P1_BASE + 0x5A)
#define REG_HDCP_DUAL_P1_2D_H       (REG_HDCP_DUAL_P1_BASE + 0x5B)
#define REG_HDCP_DUAL_P1_2E_L       (REG_HDCP_DUAL_P1_BASE + 0x5C)
#define REG_HDCP_DUAL_P1_2E_H       (REG_HDCP_DUAL_P1_BASE + 0x5D)
#define REG_HDCP_DUAL_P1_2F_L       (REG_HDCP_DUAL_P1_BASE + 0x5E)
#define REG_HDCP_DUAL_P1_2F_H       (REG_HDCP_DUAL_P1_BASE + 0x5F)
#define REG_HDCP_DUAL_P1_30_L       (REG_HDCP_DUAL_P1_BASE + 0x60)
#define REG_HDCP_DUAL_P1_30_H       (REG_HDCP_DUAL_P1_BASE + 0x61)
#define REG_HDCP_DUAL_P1_31_L       (REG_HDCP_DUAL_P1_BASE + 0x62)
#define REG_HDCP_DUAL_P1_31_H       (REG_HDCP_DUAL_P1_BASE + 0x63)
#define REG_HDCP_DUAL_P1_32_L       (REG_HDCP_DUAL_P1_BASE + 0x64)
#define REG_HDCP_DUAL_P1_32_H       (REG_HDCP_DUAL_P1_BASE + 0x65)
#define REG_HDCP_DUAL_P1_33_L       (REG_HDCP_DUAL_P1_BASE + 0x66)
#define REG_HDCP_DUAL_P1_33_H       (REG_HDCP_DUAL_P1_BASE + 0x67)
#define REG_HDCP_DUAL_P1_34_L       (REG_HDCP_DUAL_P1_BASE + 0x68)
#define REG_HDCP_DUAL_P1_34_H       (REG_HDCP_DUAL_P1_BASE + 0x69)
#define REG_HDCP_DUAL_P1_35_L       (REG_HDCP_DUAL_P1_BASE + 0x6A)
#define REG_HDCP_DUAL_P1_35_H       (REG_HDCP_DUAL_P1_BASE + 0x6B)
#define REG_HDCP_DUAL_P1_36_L       (REG_HDCP_DUAL_P1_BASE + 0x6C)
#define REG_HDCP_DUAL_P1_36_H       (REG_HDCP_DUAL_P1_BASE + 0x6D)
#define REG_HDCP_DUAL_P1_37_L       (REG_HDCP_DUAL_P1_BASE + 0x6E)
#define REG_HDCP_DUAL_P1_37_H       (REG_HDCP_DUAL_P1_BASE + 0x6F)
#define REG_HDCP_DUAL_P1_38_L       (REG_HDCP_DUAL_P1_BASE + 0x70)
#define REG_HDCP_DUAL_P1_38_H       (REG_HDCP_DUAL_P1_BASE + 0x71)
#define REG_HDCP_DUAL_P1_39_L       (REG_HDCP_DUAL_P1_BASE + 0x72)
#define REG_HDCP_DUAL_P1_39_H       (REG_HDCP_DUAL_P1_BASE + 0x73)
#define REG_HDCP_DUAL_P1_3A_L       (REG_HDCP_DUAL_P1_BASE + 0x74)
#define REG_HDCP_DUAL_P1_3A_H       (REG_HDCP_DUAL_P1_BASE + 0x75)
#define REG_HDCP_DUAL_P1_3B_L       (REG_HDCP_DUAL_P1_BASE + 0x76)
#define REG_HDCP_DUAL_P1_3B_H       (REG_HDCP_DUAL_P1_BASE + 0x77)
#define REG_HDCP_DUAL_P1_3C_L       (REG_HDCP_DUAL_P1_BASE + 0x78)
#define REG_HDCP_DUAL_P1_3C_H       (REG_HDCP_DUAL_P1_BASE + 0x79)
#define REG_HDCP_DUAL_P1_3D_L       (REG_HDCP_DUAL_P1_BASE + 0x7A)
#define REG_HDCP_DUAL_P1_3D_H       (REG_HDCP_DUAL_P1_BASE + 0x7B)
#define REG_HDCP_DUAL_P1_3E_L       (REG_HDCP_DUAL_P1_BASE + 0x7C)
#define REG_HDCP_DUAL_P1_3E_H       (REG_HDCP_DUAL_P1_BASE + 0x7D)
#define REG_HDCP_DUAL_P1_3F_L       (REG_HDCP_DUAL_P1_BASE + 0x7E)
#define REG_HDCP_DUAL_P1_3F_H       (REG_HDCP_DUAL_P1_BASE + 0x7F)
#define REG_HDCP_DUAL_P1_40_L       (REG_HDCP_DUAL_P1_BASE + 0x80)
#define REG_HDCP_DUAL_P1_40_H       (REG_HDCP_DUAL_P1_BASE + 0x81)
#define REG_HDCP_DUAL_P1_41_L       (REG_HDCP_DUAL_P1_BASE + 0x82)
#define REG_HDCP_DUAL_P1_41_H       (REG_HDCP_DUAL_P1_BASE + 0x83)
#define REG_HDCP_DUAL_P1_42_L       (REG_HDCP_DUAL_P1_BASE + 0x84)
#define REG_HDCP_DUAL_P1_42_H       (REG_HDCP_DUAL_P1_BASE + 0x85)
#define REG_HDCP_DUAL_P1_43_L       (REG_HDCP_DUAL_P1_BASE + 0x86)
#define REG_HDCP_DUAL_P1_43_H       (REG_HDCP_DUAL_P1_BASE + 0x87)
#define REG_HDCP_DUAL_P1_44_L       (REG_HDCP_DUAL_P1_BASE + 0x88)
#define REG_HDCP_DUAL_P1_44_H       (REG_HDCP_DUAL_P1_BASE + 0x89)
#define REG_HDCP_DUAL_P1_45_L       (REG_HDCP_DUAL_P1_BASE + 0x8A)
#define REG_HDCP_DUAL_P1_45_H       (REG_HDCP_DUAL_P1_BASE + 0x8B)
#define REG_HDCP_DUAL_P1_46_L       (REG_HDCP_DUAL_P1_BASE + 0x8C)
#define REG_HDCP_DUAL_P1_46_H       (REG_HDCP_DUAL_P1_BASE + 0x8D)
#define REG_HDCP_DUAL_P1_47_L       (REG_HDCP_DUAL_P1_BASE + 0x8E)
#define REG_HDCP_DUAL_P1_47_H       (REG_HDCP_DUAL_P1_BASE + 0x8F)
#define REG_HDCP_DUAL_P1_48_L       (REG_HDCP_DUAL_P1_BASE + 0x90)
#define REG_HDCP_DUAL_P1_48_H       (REG_HDCP_DUAL_P1_BASE + 0x91)
#define REG_HDCP_DUAL_P1_49_L       (REG_HDCP_DUAL_P1_BASE + 0x92)
#define REG_HDCP_DUAL_P1_49_H       (REG_HDCP_DUAL_P1_BASE + 0x93)
#define REG_HDCP_DUAL_P1_4A_L       (REG_HDCP_DUAL_P1_BASE + 0x94)
#define REG_HDCP_DUAL_P1_4A_H       (REG_HDCP_DUAL_P1_BASE + 0x95)
#define REG_HDCP_DUAL_P1_4B_L       (REG_HDCP_DUAL_P1_BASE + 0x96)
#define REG_HDCP_DUAL_P1_4B_H       (REG_HDCP_DUAL_P1_BASE + 0x97)
#define REG_HDCP_DUAL_P1_4C_L       (REG_HDCP_DUAL_P1_BASE + 0x98)
#define REG_HDCP_DUAL_P1_4C_H       (REG_HDCP_DUAL_P1_BASE + 0x99)
#define REG_HDCP_DUAL_P1_4D_L       (REG_HDCP_DUAL_P1_BASE + 0x9A)
#define REG_HDCP_DUAL_P1_4D_H       (REG_HDCP_DUAL_P1_BASE + 0x9B)
#define REG_HDCP_DUAL_P1_4E_L       (REG_HDCP_DUAL_P1_BASE + 0x9C)
#define REG_HDCP_DUAL_P1_4E_H       (REG_HDCP_DUAL_P1_BASE + 0x9D)
#define REG_HDCP_DUAL_P1_4F_L       (REG_HDCP_DUAL_P1_BASE + 0x9E)
#define REG_HDCP_DUAL_P1_4F_H       (REG_HDCP_DUAL_P1_BASE + 0x9F)
#define REG_HDCP_DUAL_P1_50_L       (REG_HDCP_DUAL_P1_BASE + 0xA0)
#define REG_HDCP_DUAL_P1_50_H       (REG_HDCP_DUAL_P1_BASE + 0xA1)
#define REG_HDCP_DUAL_P1_51_L       (REG_HDCP_DUAL_P1_BASE + 0xA2)
#define REG_HDCP_DUAL_P1_51_H       (REG_HDCP_DUAL_P1_BASE + 0xA3)
#define REG_HDCP_DUAL_P1_52_L       (REG_HDCP_DUAL_P1_BASE + 0xA4)
#define REG_HDCP_DUAL_P1_52_H       (REG_HDCP_DUAL_P1_BASE + 0xA5)
#define REG_HDCP_DUAL_P1_53_L       (REG_HDCP_DUAL_P1_BASE + 0xA6)
#define REG_HDCP_DUAL_P1_53_H       (REG_HDCP_DUAL_P1_BASE + 0xA7)
#define REG_HDCP_DUAL_P1_54_L       (REG_HDCP_DUAL_P1_BASE + 0xA8)
#define REG_HDCP_DUAL_P1_54_H       (REG_HDCP_DUAL_P1_BASE + 0xA9)
#define REG_HDCP_DUAL_P1_55_L       (REG_HDCP_DUAL_P1_BASE + 0xAA)
#define REG_HDCP_DUAL_P1_55_H       (REG_HDCP_DUAL_P1_BASE + 0xAB)
#define REG_HDCP_DUAL_P1_56_L       (REG_HDCP_DUAL_P1_BASE + 0xAC)
#define REG_HDCP_DUAL_P1_56_H       (REG_HDCP_DUAL_P1_BASE + 0xAD)
#define REG_HDCP_DUAL_P1_57_L       (REG_HDCP_DUAL_P1_BASE + 0xAE)
#define REG_HDCP_DUAL_P1_57_H       (REG_HDCP_DUAL_P1_BASE + 0xAF)
#define REG_HDCP_DUAL_P1_58_L       (REG_HDCP_DUAL_P1_BASE + 0xB0)
#define REG_HDCP_DUAL_P1_58_H       (REG_HDCP_DUAL_P1_BASE + 0xB1)
#define REG_HDCP_DUAL_P1_59_L       (REG_HDCP_DUAL_P1_BASE + 0xB2)
#define REG_HDCP_DUAL_P1_59_H       (REG_HDCP_DUAL_P1_BASE + 0xB3)
#define REG_HDCP_DUAL_P1_5A_L       (REG_HDCP_DUAL_P1_BASE + 0xB4)
#define REG_HDCP_DUAL_P1_5A_H       (REG_HDCP_DUAL_P1_BASE + 0xB5)
#define REG_HDCP_DUAL_P1_5B_L       (REG_HDCP_DUAL_P1_BASE + 0xB6)
#define REG_HDCP_DUAL_P1_5B_H       (REG_HDCP_DUAL_P1_BASE + 0xB7)
#define REG_HDCP_DUAL_P1_5C_L       (REG_HDCP_DUAL_P1_BASE + 0xB8)
#define REG_HDCP_DUAL_P1_5C_H       (REG_HDCP_DUAL_P1_BASE + 0xB9)
#define REG_HDCP_DUAL_P1_5D_L       (REG_HDCP_DUAL_P1_BASE + 0xBA)
#define REG_HDCP_DUAL_P1_5D_H       (REG_HDCP_DUAL_P1_BASE + 0xBB)
#define REG_HDCP_DUAL_P1_5E_L       (REG_HDCP_DUAL_P1_BASE + 0xBC)
#define REG_HDCP_DUAL_P1_5E_H       (REG_HDCP_DUAL_P1_BASE + 0xBD)
#define REG_HDCP_DUAL_P1_5F_L       (REG_HDCP_DUAL_P1_BASE + 0xBE)
#define REG_HDCP_DUAL_P1_5F_H       (REG_HDCP_DUAL_P1_BASE + 0xBF)
#define REG_HDCP_DUAL_P1_60_L       (REG_HDCP_DUAL_P1_BASE + 0xC0)
#define REG_HDCP_DUAL_P1_60_H       (REG_HDCP_DUAL_P1_BASE + 0xC1)
#define REG_HDCP_DUAL_P1_61_L       (REG_HDCP_DUAL_P1_BASE + 0xC2)
#define REG_HDCP_DUAL_P1_61_H       (REG_HDCP_DUAL_P1_BASE + 0xC3)
#define REG_HDCP_DUAL_P1_62_L       (REG_HDCP_DUAL_P1_BASE + 0xC4)
#define REG_HDCP_DUAL_P1_62_H       (REG_HDCP_DUAL_P1_BASE + 0xC5)
#define REG_HDCP_DUAL_P1_63_L       (REG_HDCP_DUAL_P1_BASE + 0xC6)
#define REG_HDCP_DUAL_P1_63_H       (REG_HDCP_DUAL_P1_BASE + 0xC7)
#define REG_HDCP_DUAL_P1_64_L       (REG_HDCP_DUAL_P1_BASE + 0xC8)
#define REG_HDCP_DUAL_P1_64_H       (REG_HDCP_DUAL_P1_BASE + 0xC9)
#define REG_HDCP_DUAL_P1_65_L       (REG_HDCP_DUAL_P1_BASE + 0xCA)
#define REG_HDCP_DUAL_P1_65_H       (REG_HDCP_DUAL_P1_BASE + 0xCB)
#define REG_HDCP_DUAL_P1_66_L       (REG_HDCP_DUAL_P1_BASE + 0xCC)
#define REG_HDCP_DUAL_P1_66_H       (REG_HDCP_DUAL_P1_BASE + 0xCD)
#define REG_HDCP_DUAL_P1_67_L       (REG_HDCP_DUAL_P1_BASE + 0xCE)
#define REG_HDCP_DUAL_P1_67_H       (REG_HDCP_DUAL_P1_BASE + 0xCF)
#define REG_HDCP_DUAL_P1_68_L       (REG_HDCP_DUAL_P1_BASE + 0xD0)
#define REG_HDCP_DUAL_P1_68_H       (REG_HDCP_DUAL_P1_BASE + 0xD1)

// DVI_DTOP_DUAL_P2
#define REG_DVI_DTOP_DUAL_P2_00_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x00)
#define REG_DVI_DTOP_DUAL_P2_00_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x01)
#define REG_DVI_DTOP_DUAL_P2_01_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x02)
#define REG_DVI_DTOP_DUAL_P2_01_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x03)
#define REG_DVI_DTOP_DUAL_P2_02_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x04)
#define REG_DVI_DTOP_DUAL_P2_02_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x05)
#define REG_DVI_DTOP_DUAL_P2_03_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x06)
#define REG_DVI_DTOP_DUAL_P2_03_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x07)
#define REG_DVI_DTOP_DUAL_P2_04_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x08)
#define REG_DVI_DTOP_DUAL_P2_04_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x09)
#define REG_DVI_DTOP_DUAL_P2_05_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0A)
#define REG_DVI_DTOP_DUAL_P2_05_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0B)
#define REG_DVI_DTOP_DUAL_P2_06_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0C)
#define REG_DVI_DTOP_DUAL_P2_06_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0D)
#define REG_DVI_DTOP_DUAL_P2_07_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0E)
#define REG_DVI_DTOP_DUAL_P2_07_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0F)
#define REG_DVI_DTOP_DUAL_P2_08_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x10)
#define REG_DVI_DTOP_DUAL_P2_08_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x11)
#define REG_DVI_DTOP_DUAL_P2_09_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x12)
#define REG_DVI_DTOP_DUAL_P2_09_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x13)
#define REG_DVI_DTOP_DUAL_P2_0A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x14)
#define REG_DVI_DTOP_DUAL_P2_0A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x15)
#define REG_DVI_DTOP_DUAL_P2_0B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x16)
#define REG_DVI_DTOP_DUAL_P2_0B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x17)
#define REG_DVI_DTOP_DUAL_P2_0C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x18)
#define REG_DVI_DTOP_DUAL_P2_0C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x19)
#define REG_DVI_DTOP_DUAL_P2_0D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1A)
#define REG_DVI_DTOP_DUAL_P2_0D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1B)
#define REG_DVI_DTOP_DUAL_P2_0E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1C)
#define REG_DVI_DTOP_DUAL_P2_0E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1D)
#define REG_DVI_DTOP_DUAL_P2_0F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1E)
#define REG_DVI_DTOP_DUAL_P2_0F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1F)
#define REG_DVI_DTOP_DUAL_P2_10_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x20)
#define REG_DVI_DTOP_DUAL_P2_10_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x21)
#define REG_DVI_DTOP_DUAL_P2_11_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x22)
#define REG_DVI_DTOP_DUAL_P2_11_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x23)
#define REG_DVI_DTOP_DUAL_P2_12_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x24)
#define REG_DVI_DTOP_DUAL_P2_12_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x25)
#define REG_DVI_DTOP_DUAL_P2_13_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x26)
#define REG_DVI_DTOP_DUAL_P2_13_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x27)
#define REG_DVI_DTOP_DUAL_P2_14_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x28)
#define REG_DVI_DTOP_DUAL_P2_14_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x29)
#define REG_DVI_DTOP_DUAL_P2_15_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2A)
#define REG_DVI_DTOP_DUAL_P2_15_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2B)
#define REG_DVI_DTOP_DUAL_P2_16_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2C)
#define REG_DVI_DTOP_DUAL_P2_16_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2D)
#define REG_DVI_DTOP_DUAL_P2_17_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2E)
#define REG_DVI_DTOP_DUAL_P2_17_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2F)
#define REG_DVI_DTOP_DUAL_P2_18_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x30)
#define REG_DVI_DTOP_DUAL_P2_18_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x31)
#define REG_DVI_DTOP_DUAL_P2_19_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x32)
#define REG_DVI_DTOP_DUAL_P2_19_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x33)
#define REG_DVI_DTOP_DUAL_P2_1A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x34)
#define REG_DVI_DTOP_DUAL_P2_1A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x35)
#define REG_DVI_DTOP_DUAL_P2_1B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x36)
#define REG_DVI_DTOP_DUAL_P2_1B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x37)
#define REG_DVI_DTOP_DUAL_P2_1C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x38)
#define REG_DVI_DTOP_DUAL_P2_1C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x39)
#define REG_DVI_DTOP_DUAL_P2_1D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3A)
#define REG_DVI_DTOP_DUAL_P2_1D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3B)
#define REG_DVI_DTOP_DUAL_P2_1E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3C)
#define REG_DVI_DTOP_DUAL_P2_1E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3D)
#define REG_DVI_DTOP_DUAL_P2_1F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3E)
#define REG_DVI_DTOP_DUAL_P2_1F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3F)
#define REG_DVI_DTOP_DUAL_P2_20_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x40)
#define REG_DVI_DTOP_DUAL_P2_20_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x41)
#define REG_DVI_DTOP_DUAL_P2_21_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x42)
#define REG_DVI_DTOP_DUAL_P2_21_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x43)
#define REG_DVI_DTOP_DUAL_P2_22_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x44)
#define REG_DVI_DTOP_DUAL_P2_22_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x45)
#define REG_DVI_DTOP_DUAL_P2_23_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x46)
#define REG_DVI_DTOP_DUAL_P2_23_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x47)
#define REG_DVI_DTOP_DUAL_P2_24_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x48)
#define REG_DVI_DTOP_DUAL_P2_24_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x49)
#define REG_DVI_DTOP_DUAL_P2_25_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4A)
#define REG_DVI_DTOP_DUAL_P2_25_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4B)
#define REG_DVI_DTOP_DUAL_P2_26_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4C)
#define REG_DVI_DTOP_DUAL_P2_26_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4D)
#define REG_DVI_DTOP_DUAL_P2_27_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4E)
#define REG_DVI_DTOP_DUAL_P2_27_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4F)
#define REG_DVI_DTOP_DUAL_P2_28_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x50)
#define REG_DVI_DTOP_DUAL_P2_28_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x51)
#define REG_DVI_DTOP_DUAL_P2_29_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x52)
#define REG_DVI_DTOP_DUAL_P2_29_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x53)
#define REG_DVI_DTOP_DUAL_P2_2A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x54)
#define REG_DVI_DTOP_DUAL_P2_2A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x55)
#define REG_DVI_DTOP_DUAL_P2_2B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x56)
#define REG_DVI_DTOP_DUAL_P2_2B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x57)
#define REG_DVI_DTOP_DUAL_P2_2C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x58)
#define REG_DVI_DTOP_DUAL_P2_2C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x59)
#define REG_DVI_DTOP_DUAL_P2_2D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5A)
#define REG_DVI_DTOP_DUAL_P2_2D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5B)
#define REG_DVI_DTOP_DUAL_P2_2E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5C)
#define REG_DVI_DTOP_DUAL_P2_2E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5D)
#define REG_DVI_DTOP_DUAL_P2_2F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5E)
#define REG_DVI_DTOP_DUAL_P2_2F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5F)
#define REG_DVI_DTOP_DUAL_P2_30_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x60)
#define REG_DVI_DTOP_DUAL_P2_30_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x61)
#define REG_DVI_DTOP_DUAL_P2_31_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x62)
#define REG_DVI_DTOP_DUAL_P2_31_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x63)
#define REG_DVI_DTOP_DUAL_P2_32_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x64)
#define REG_DVI_DTOP_DUAL_P2_32_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x65)
#define REG_DVI_DTOP_DUAL_P2_33_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x66)
#define REG_DVI_DTOP_DUAL_P2_33_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x67)
#define REG_DVI_DTOP_DUAL_P2_34_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x68)
#define REG_DVI_DTOP_DUAL_P2_34_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x69)
#define REG_DVI_DTOP_DUAL_P2_35_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6A)
#define REG_DVI_DTOP_DUAL_P2_35_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6B)
#define REG_DVI_DTOP_DUAL_P2_36_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6C)
#define REG_DVI_DTOP_DUAL_P2_36_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6D)
#define REG_DVI_DTOP_DUAL_P2_37_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6E)
#define REG_DVI_DTOP_DUAL_P2_37_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6F)
#define REG_DVI_DTOP_DUAL_P2_38_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x70)
#define REG_DVI_DTOP_DUAL_P2_38_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x71)
#define REG_DVI_DTOP_DUAL_P2_39_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x72)
#define REG_DVI_DTOP_DUAL_P2_39_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x73)
#define REG_DVI_DTOP_DUAL_P2_3A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x74)
#define REG_DVI_DTOP_DUAL_P2_3A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x75)
#define REG_DVI_DTOP_DUAL_P2_3B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x76)
#define REG_DVI_DTOP_DUAL_P2_3B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x77)
#define REG_DVI_DTOP_DUAL_P2_3C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x78)
#define REG_DVI_DTOP_DUAL_P2_3C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x79)
#define REG_DVI_DTOP_DUAL_P2_3D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7A)
#define REG_DVI_DTOP_DUAL_P2_3D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7B)
#define REG_DVI_DTOP_DUAL_P2_3E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7C)
#define REG_DVI_DTOP_DUAL_P2_3E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7D)
#define REG_DVI_DTOP_DUAL_P2_3F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7E)
#define REG_DVI_DTOP_DUAL_P2_3F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7F)
#define REG_DVI_DTOP_DUAL_P2_40_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x80)
#define REG_DVI_DTOP_DUAL_P2_40_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x81)
#define REG_DVI_DTOP_DUAL_P2_41_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x82)
#define REG_DVI_DTOP_DUAL_P2_41_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x83)
#define REG_DVI_DTOP_DUAL_P2_42_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x84)
#define REG_DVI_DTOP_DUAL_P2_42_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x85)
#define REG_DVI_DTOP_DUAL_P2_43_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x86)
#define REG_DVI_DTOP_DUAL_P2_43_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x87)
#define REG_DVI_DTOP_DUAL_P2_44_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x88)
#define REG_DVI_DTOP_DUAL_P2_44_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x89)
#define REG_DVI_DTOP_DUAL_P2_45_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8A)
#define REG_DVI_DTOP_DUAL_P2_45_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8B)
#define REG_DVI_DTOP_DUAL_P2_46_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8C)
#define REG_DVI_DTOP_DUAL_P2_46_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8D)
#define REG_DVI_DTOP_DUAL_P2_47_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8E)
#define REG_DVI_DTOP_DUAL_P2_47_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8F)
#define REG_DVI_DTOP_DUAL_P2_48_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x90)
#define REG_DVI_DTOP_DUAL_P2_48_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x91)
#define REG_DVI_DTOP_DUAL_P2_49_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x92)
#define REG_DVI_DTOP_DUAL_P2_49_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x93)
#define REG_DVI_DTOP_DUAL_P2_4A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x94)
#define REG_DVI_DTOP_DUAL_P2_4A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x95)
#define REG_DVI_DTOP_DUAL_P2_4B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x96)
#define REG_DVI_DTOP_DUAL_P2_4B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x97)
#define REG_DVI_DTOP_DUAL_P2_4C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x98)
#define REG_DVI_DTOP_DUAL_P2_4C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x99)
#define REG_DVI_DTOP_DUAL_P2_4D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9A)
#define REG_DVI_DTOP_DUAL_P2_4D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9B)
#define REG_DVI_DTOP_DUAL_P2_4E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9C)
#define REG_DVI_DTOP_DUAL_P2_4E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9D)
#define REG_DVI_DTOP_DUAL_P2_4F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9E)
#define REG_DVI_DTOP_DUAL_P2_4F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9F)
#define REG_DVI_DTOP_DUAL_P2_50_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA0)
#define REG_DVI_DTOP_DUAL_P2_50_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA1)
#define REG_DVI_DTOP_DUAL_P2_51_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA2)
#define REG_DVI_DTOP_DUAL_P2_51_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA3)
#define REG_DVI_DTOP_DUAL_P2_52_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA4)
#define REG_DVI_DTOP_DUAL_P2_52_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA5)
#define REG_DVI_DTOP_DUAL_P2_53_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA6)
#define REG_DVI_DTOP_DUAL_P2_53_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA7)
#define REG_DVI_DTOP_DUAL_P2_54_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA8)
#define REG_DVI_DTOP_DUAL_P2_54_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA9)
#define REG_DVI_DTOP_DUAL_P2_55_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAA)
#define REG_DVI_DTOP_DUAL_P2_55_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAB)
#define REG_DVI_DTOP_DUAL_P2_56_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAC)
#define REG_DVI_DTOP_DUAL_P2_56_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAD)
#define REG_DVI_DTOP_DUAL_P2_57_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAE)
#define REG_DVI_DTOP_DUAL_P2_57_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAF)
#define REG_DVI_DTOP_DUAL_P2_58_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB0)
#define REG_DVI_DTOP_DUAL_P2_58_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB1)
#define REG_DVI_DTOP_DUAL_P2_59_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB2)
#define REG_DVI_DTOP_DUAL_P2_59_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB3)
#define REG_DVI_DTOP_DUAL_P2_5A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB4)
#define REG_DVI_DTOP_DUAL_P2_5A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB5)
#define REG_DVI_DTOP_DUAL_P2_5B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB6)
#define REG_DVI_DTOP_DUAL_P2_5B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB7)
#define REG_DVI_DTOP_DUAL_P2_5C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB8)
#define REG_DVI_DTOP_DUAL_P2_5C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB9)
#define REG_DVI_DTOP_DUAL_P2_5D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBA)
#define REG_DVI_DTOP_DUAL_P2_5D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBB)
#define REG_DVI_DTOP_DUAL_P2_5E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBC)
#define REG_DVI_DTOP_DUAL_P2_5E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBD)
#define REG_DVI_DTOP_DUAL_P2_5F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBE)
#define REG_DVI_DTOP_DUAL_P2_5F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBF)
#define REG_DVI_DTOP_DUAL_P2_60_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC0)
#define REG_DVI_DTOP_DUAL_P2_60_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC1)
#define REG_DVI_DTOP_DUAL_P2_61_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC2)
#define REG_DVI_DTOP_DUAL_P2_61_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC3)
#define REG_DVI_DTOP_DUAL_P2_62_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC4)
#define REG_DVI_DTOP_DUAL_P2_62_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC5)
#define REG_DVI_DTOP_DUAL_P2_63_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6)
#define REG_DVI_DTOP_DUAL_P2_63_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC7)
#define REG_DVI_DTOP_DUAL_P2_64_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC8)
#define REG_DVI_DTOP_DUAL_P2_64_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC9)
#define REG_DVI_DTOP_DUAL_P2_65_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCA)
#define REG_DVI_DTOP_DUAL_P2_65_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCB)
#define REG_DVI_DTOP_DUAL_P2_66_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCC)
#define REG_DVI_DTOP_DUAL_P2_66_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCD)
#define REG_DVI_DTOP_DUAL_P2_67_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCE)
#define REG_DVI_DTOP_DUAL_P2_67_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCF)
#define REG_DVI_DTOP_DUAL_P2_68_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD0)
#define REG_DVI_DTOP_DUAL_P2_68_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD1)
#define REG_DVI_DTOP_DUAL_P2_69_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD2)
#define REG_DVI_DTOP_DUAL_P2_69_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD3)
#define REG_DVI_DTOP_DUAL_P2_6A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD4)
#define REG_DVI_DTOP_DUAL_P2_6A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD5)
#define REG_DVI_DTOP_DUAL_P2_6B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD6)
#define REG_DVI_DTOP_DUAL_P2_6B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD7)
#define REG_DVI_DTOP_DUAL_P2_6C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD8)
#define REG_DVI_DTOP_DUAL_P2_6C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD9)
#define REG_DVI_DTOP_DUAL_P2_6D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDA)
#define REG_DVI_DTOP_DUAL_P2_6D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDB)
#define REG_DVI_DTOP_DUAL_P2_6E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDC)
#define REG_DVI_DTOP_DUAL_P2_6E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDD)
#define REG_DVI_DTOP_DUAL_P2_6F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDE)
#define REG_DVI_DTOP_DUAL_P2_6F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDF)
#define REG_DVI_DTOP_DUAL_P2_70_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE0)
#define REG_DVI_DTOP_DUAL_P2_70_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE1)
#define REG_DVI_DTOP_DUAL_P2_71_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE2)
#define REG_DVI_DTOP_DUAL_P2_71_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE3)
#define REG_DVI_DTOP_DUAL_P2_72_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE4)
#define REG_DVI_DTOP_DUAL_P2_72_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE5)
#define REG_DVI_DTOP_DUAL_P2_73_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE6)
#define REG_DVI_DTOP_DUAL_P2_73_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE7)
#define REG_DVI_DTOP_DUAL_P2_74_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE8)
#define REG_DVI_DTOP_DUAL_P2_74_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE9)
#define REG_DVI_DTOP_DUAL_P2_75_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEA)
#define REG_DVI_DTOP_DUAL_P2_75_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEB)
#define REG_DVI_DTOP_DUAL_P2_76_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEC)
#define REG_DVI_DTOP_DUAL_P2_76_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xED)
#define REG_DVI_DTOP_DUAL_P2_77_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEE)
#define REG_DVI_DTOP_DUAL_P2_77_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEF)
#define REG_DVI_DTOP_DUAL_P2_78_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF0)
#define REG_DVI_DTOP_DUAL_P2_78_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF1)
#define REG_DVI_DTOP_DUAL_P2_79_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF2)
#define REG_DVI_DTOP_DUAL_P2_79_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF3)
#define REG_DVI_DTOP_DUAL_P2_7A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF4)
#define REG_DVI_DTOP_DUAL_P2_7A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF5)
#define REG_DVI_DTOP_DUAL_P2_7B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF6)
#define REG_DVI_DTOP_DUAL_P2_7B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF7)
#define REG_DVI_DTOP_DUAL_P2_7C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF8)
#define REG_DVI_DTOP_DUAL_P2_7C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF9)
#define REG_DVI_DTOP_DUAL_P2_7D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFA)
#define REG_DVI_DTOP_DUAL_P2_7D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFB)
#define REG_DVI_DTOP_DUAL_P2_7E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFC)
#define REG_DVI_DTOP_DUAL_P2_7E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFD)
#define REG_DVI_DTOP_DUAL_P2_7F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFE)
#define REG_DVI_DTOP_DUAL_P2_7F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFF)

// DVI_RSV_DUAL_P2
#define REG_DVI_RSV_DUAL_P2_00_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
#define REG_DVI_RSV_DUAL_P2_00_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
#define REG_DVI_RSV_DUAL_P2_01_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
#define REG_DVI_RSV_DUAL_P2_01_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
#define REG_DVI_RSV_DUAL_P2_02_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
#define REG_DVI_RSV_DUAL_P2_02_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
#define REG_DVI_RSV_DUAL_P2_03_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
#define REG_DVI_RSV_DUAL_P2_03_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
#define REG_DVI_RSV_DUAL_P2_04_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
#define REG_DVI_RSV_DUAL_P2_04_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
#define REG_DVI_RSV_DUAL_P2_05_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0A)
#define REG_DVI_RSV_DUAL_P2_05_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0B)
#define REG_DVI_RSV_DUAL_P2_06_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0C)
#define REG_DVI_RSV_DUAL_P2_06_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0D)
#define REG_DVI_RSV_DUAL_P2_07_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0E)
#define REG_DVI_RSV_DUAL_P2_07_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0F)
#define REG_DVI_RSV_DUAL_P2_08_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x10)
#define REG_DVI_RSV_DUAL_P2_08_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x11)
#define REG_DVI_RSV_DUAL_P2_09_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x12)
#define REG_DVI_RSV_DUAL_P2_09_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x13)
#define REG_DVI_RSV_DUAL_P2_0A_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x14)
#define REG_DVI_RSV_DUAL_P2_0A_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x15)
#define REG_DVI_RSV_DUAL_P2_0B_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x16)
#define REG_DVI_RSV_DUAL_P2_0B_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x17)
#define REG_DVI_RSV_DUAL_P2_0C_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x18)
#define REG_DVI_RSV_DUAL_P2_0C_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x19)
#define REG_DVI_RSV_DUAL_P2_0D_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1A)
#define REG_DVI_RSV_DUAL_P2_0D_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1B)
#define REG_DVI_RSV_DUAL_P2_0E_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1C)
#define REG_DVI_RSV_DUAL_P2_0E_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1D)
#define REG_DVI_RSV_DUAL_P2_0F_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1E)
#define REG_DVI_RSV_DUAL_P2_0F_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1F)
#define REG_DVI_RSV_DUAL_P2_10_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x20)
#define REG_DVI_RSV_DUAL_P2_10_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x21)
#define REG_DVI_RSV_DUAL_P2_11_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x22)
#define REG_DVI_RSV_DUAL_P2_11_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x23)
#define REG_DVI_RSV_DUAL_P2_12_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x24)
#define REG_DVI_RSV_DUAL_P2_12_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x25)
#define REG_DVI_RSV_DUAL_P2_13_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x26)
#define REG_DVI_RSV_DUAL_P2_13_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x27)
#define REG_DVI_RSV_DUAL_P2_14_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x28)
#define REG_DVI_RSV_DUAL_P2_14_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x29)
#define REG_DVI_RSV_DUAL_P2_15_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2A)
#define REG_DVI_RSV_DUAL_P2_15_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2B)
#define REG_DVI_RSV_DUAL_P2_16_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2C)
#define REG_DVI_RSV_DUAL_P2_16_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2D)
#define REG_DVI_RSV_DUAL_P2_17_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2E)
#define REG_DVI_RSV_DUAL_P2_17_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2F)
#define REG_DVI_RSV_DUAL_P2_18_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x30)
#define REG_DVI_RSV_DUAL_P2_18_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x31)
#define REG_DVI_RSV_DUAL_P2_19_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x32)
#define REG_DVI_RSV_DUAL_P2_19_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x33)
#define REG_DVI_RSV_DUAL_P2_1A_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x34)
#define REG_DVI_RSV_DUAL_P2_1A_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x35)
#define REG_DVI_RSV_DUAL_P2_1B_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x36)
#define REG_DVI_RSV_DUAL_P2_1B_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x37)
#define REG_DVI_RSV_DUAL_P2_1C_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x38)
#define REG_DVI_RSV_DUAL_P2_1C_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x39)
#define REG_DVI_RSV_DUAL_P2_1D_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3A)
#define REG_DVI_RSV_DUAL_P2_1D_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3B)
#define REG_DVI_RSV_DUAL_P2_1E_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3C)
#define REG_DVI_RSV_DUAL_P2_1E_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3D)
#define REG_DVI_RSV_DUAL_P2_1F_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3E)
#define REG_DVI_RSV_DUAL_P2_1F_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3F)

// HDCP_DUAL_P2
#define REG_HDCP_DUAL_P2_00_L       (REG_HDCP_DUAL_P2_BASE + 0x00)
#define REG_HDCP_DUAL_P2_00_H       (REG_HDCP_DUAL_P2_BASE + 0x01)
#define REG_HDCP_DUAL_P2_01_L       (REG_HDCP_DUAL_P2_BASE + 0x02)
#define REG_HDCP_DUAL_P2_01_H       (REG_HDCP_DUAL_P2_BASE + 0x03)
#define REG_HDCP_DUAL_P2_02_L       (REG_HDCP_DUAL_P2_BASE + 0x04)
#define REG_HDCP_DUAL_P2_02_H       (REG_HDCP_DUAL_P2_BASE + 0x05)
#define REG_HDCP_DUAL_P2_03_L       (REG_HDCP_DUAL_P2_BASE + 0x06)
#define REG_HDCP_DUAL_P2_03_H       (REG_HDCP_DUAL_P2_BASE + 0x07)
#define REG_HDCP_DUAL_P2_04_L       (REG_HDCP_DUAL_P2_BASE + 0x08)
#define REG_HDCP_DUAL_P2_04_H       (REG_HDCP_DUAL_P2_BASE + 0x09)
#define REG_HDCP_DUAL_P2_05_L       (REG_HDCP_DUAL_P2_BASE + 0x0A)
#define REG_HDCP_DUAL_P2_05_H       (REG_HDCP_DUAL_P2_BASE + 0x0B)
#define REG_HDCP_DUAL_P2_06_L       (REG_HDCP_DUAL_P2_BASE + 0x0C)
#define REG_HDCP_DUAL_P2_06_H       (REG_HDCP_DUAL_P2_BASE + 0x0D)
#define REG_HDCP_DUAL_P2_07_L       (REG_HDCP_DUAL_P2_BASE + 0x0E)
#define REG_HDCP_DUAL_P2_07_H       (REG_HDCP_DUAL_P2_BASE + 0x0F)
#define REG_HDCP_DUAL_P2_08_L       (REG_HDCP_DUAL_P2_BASE + 0x10)
#define REG_HDCP_DUAL_P2_08_H       (REG_HDCP_DUAL_P2_BASE + 0x11)
#define REG_HDCP_DUAL_P2_09_L       (REG_HDCP_DUAL_P2_BASE + 0x12)
#define REG_HDCP_DUAL_P2_09_H       (REG_HDCP_DUAL_P2_BASE + 0x13)
#define REG_HDCP_DUAL_P2_0A_L       (REG_HDCP_DUAL_P2_BASE + 0x14)
#define REG_HDCP_DUAL_P2_0A_H       (REG_HDCP_DUAL_P2_BASE + 0x15)
#define REG_HDCP_DUAL_P2_0B_L       (REG_HDCP_DUAL_P2_BASE + 0x16)
#define REG_HDCP_DUAL_P2_0B_H       (REG_HDCP_DUAL_P2_BASE + 0x17)
#define REG_HDCP_DUAL_P2_0C_L       (REG_HDCP_DUAL_P2_BASE + 0x18)
#define REG_HDCP_DUAL_P2_0C_H       (REG_HDCP_DUAL_P2_BASE + 0x19)
#define REG_HDCP_DUAL_P2_0D_L       (REG_HDCP_DUAL_P2_BASE + 0x1A)
#define REG_HDCP_DUAL_P2_0D_H       (REG_HDCP_DUAL_P2_BASE + 0x1B)
#define REG_HDCP_DUAL_P2_0E_L       (REG_HDCP_DUAL_P2_BASE + 0x1C)
#define REG_HDCP_DUAL_P2_0E_H       (REG_HDCP_DUAL_P2_BASE + 0x1D)
#define REG_HDCP_DUAL_P2_0F_L       (REG_HDCP_DUAL_P2_BASE + 0x1E)
#define REG_HDCP_DUAL_P2_0F_H       (REG_HDCP_DUAL_P2_BASE + 0x1F)
#define REG_HDCP_DUAL_P2_10_L       (REG_HDCP_DUAL_P2_BASE + 0x20)
#define REG_HDCP_DUAL_P2_10_H       (REG_HDCP_DUAL_P2_BASE + 0x21)
#define REG_HDCP_DUAL_P2_11_L       (REG_HDCP_DUAL_P2_BASE + 0x22)
#define REG_HDCP_DUAL_P2_11_H       (REG_HDCP_DUAL_P2_BASE + 0x23)
#define REG_HDCP_DUAL_P2_12_L       (REG_HDCP_DUAL_P2_BASE + 0x24)
#define REG_HDCP_DUAL_P2_12_H       (REG_HDCP_DUAL_P2_BASE + 0x25)
#define REG_HDCP_DUAL_P2_13_L       (REG_HDCP_DUAL_P2_BASE + 0x26)
#define REG_HDCP_DUAL_P2_13_H       (REG_HDCP_DUAL_P2_BASE + 0x27)
#define REG_HDCP_DUAL_P2_14_L       (REG_HDCP_DUAL_P2_BASE + 0x28)
#define REG_HDCP_DUAL_P2_14_H       (REG_HDCP_DUAL_P2_BASE + 0x29)
#define REG_HDCP_DUAL_P2_15_L       (REG_HDCP_DUAL_P2_BASE + 0x2A)
#define REG_HDCP_DUAL_P2_15_H       (REG_HDCP_DUAL_P2_BASE + 0x2B)
#define REG_HDCP_DUAL_P2_16_L       (REG_HDCP_DUAL_P2_BASE + 0x2C)
#define REG_HDCP_DUAL_P2_16_H       (REG_HDCP_DUAL_P2_BASE + 0x2D)
#define REG_HDCP_DUAL_P2_17_L       (REG_HDCP_DUAL_P2_BASE + 0x2E)
#define REG_HDCP_DUAL_P2_17_H       (REG_HDCP_DUAL_P2_BASE + 0x2F)
#define REG_HDCP_DUAL_P2_18_L       (REG_HDCP_DUAL_P2_BASE + 0x30)
#define REG_HDCP_DUAL_P2_18_H       (REG_HDCP_DUAL_P2_BASE + 0x31)
#define REG_HDCP_DUAL_P2_19_L       (REG_HDCP_DUAL_P2_BASE + 0x32)
#define REG_HDCP_DUAL_P2_19_H       (REG_HDCP_DUAL_P2_BASE + 0x33)
#define REG_HDCP_DUAL_P2_1A_L       (REG_HDCP_DUAL_P2_BASE + 0x34)
#define REG_HDCP_DUAL_P2_1A_H       (REG_HDCP_DUAL_P2_BASE + 0x35)
#define REG_HDCP_DUAL_P2_1B_L       (REG_HDCP_DUAL_P2_BASE + 0x36)
#define REG_HDCP_DUAL_P2_1B_H       (REG_HDCP_DUAL_P2_BASE + 0x37)
#define REG_HDCP_DUAL_P2_1C_L       (REG_HDCP_DUAL_P2_BASE + 0x38)
#define REG_HDCP_DUAL_P2_1C_H       (REG_HDCP_DUAL_P2_BASE + 0x39)
#define REG_HDCP_DUAL_P2_1D_L       (REG_HDCP_DUAL_P2_BASE + 0x3A)
#define REG_HDCP_DUAL_P2_1D_H       (REG_HDCP_DUAL_P2_BASE + 0x3B)
#define REG_HDCP_DUAL_P2_1E_L       (REG_HDCP_DUAL_P2_BASE + 0x3C)
#define REG_HDCP_DUAL_P2_1E_H       (REG_HDCP_DUAL_P2_BASE + 0x3D)
#define REG_HDCP_DUAL_P2_1F_L       (REG_HDCP_DUAL_P2_BASE + 0x3E)
#define REG_HDCP_DUAL_P2_1F_H       (REG_HDCP_DUAL_P2_BASE + 0x3F)
#define REG_HDCP_DUAL_P2_20_L       (REG_HDCP_DUAL_P2_BASE + 0x40)
#define REG_HDCP_DUAL_P2_20_H       (REG_HDCP_DUAL_P2_BASE + 0x41)
#define REG_HDCP_DUAL_P2_21_L       (REG_HDCP_DUAL_P2_BASE + 0x42)
#define REG_HDCP_DUAL_P2_21_H       (REG_HDCP_DUAL_P2_BASE + 0x43)
#define REG_HDCP_DUAL_P2_22_L       (REG_HDCP_DUAL_P2_BASE + 0x44)
#define REG_HDCP_DUAL_P2_22_H       (REG_HDCP_DUAL_P2_BASE + 0x45)
#define REG_HDCP_DUAL_P2_23_L       (REG_HDCP_DUAL_P2_BASE + 0x46)
#define REG_HDCP_DUAL_P2_23_H       (REG_HDCP_DUAL_P2_BASE + 0x47)
#define REG_HDCP_DUAL_P2_24_L       (REG_HDCP_DUAL_P2_BASE + 0x48)
#define REG_HDCP_DUAL_P2_24_H       (REG_HDCP_DUAL_P2_BASE + 0x49)
#define REG_HDCP_DUAL_P2_25_L       (REG_HDCP_DUAL_P2_BASE + 0x4A)
#define REG_HDCP_DUAL_P2_25_H       (REG_HDCP_DUAL_P2_BASE + 0x4B)
#define REG_HDCP_DUAL_P2_26_L       (REG_HDCP_DUAL_P2_BASE + 0x4C)
#define REG_HDCP_DUAL_P2_26_H       (REG_HDCP_DUAL_P2_BASE + 0x4D)
#define REG_HDCP_DUAL_P2_27_L       (REG_HDCP_DUAL_P2_BASE + 0x4E)
#define REG_HDCP_DUAL_P2_27_H       (REG_HDCP_DUAL_P2_BASE + 0x4F)
#define REG_HDCP_DUAL_P2_28_L       (REG_HDCP_DUAL_P2_BASE + 0x50)
#define REG_HDCP_DUAL_P2_28_H       (REG_HDCP_DUAL_P2_BASE + 0x51)
#define REG_HDCP_DUAL_P2_29_L       (REG_HDCP_DUAL_P2_BASE + 0x52)
#define REG_HDCP_DUAL_P2_29_H       (REG_HDCP_DUAL_P2_BASE + 0x53)
#define REG_HDCP_DUAL_P2_2A_L       (REG_HDCP_DUAL_P2_BASE + 0x54)
#define REG_HDCP_DUAL_P2_2A_H       (REG_HDCP_DUAL_P2_BASE + 0x55)
#define REG_HDCP_DUAL_P2_2B_L       (REG_HDCP_DUAL_P2_BASE + 0x56)
#define REG_HDCP_DUAL_P2_2B_H       (REG_HDCP_DUAL_P2_BASE + 0x57)
#define REG_HDCP_DUAL_P2_2C_L       (REG_HDCP_DUAL_P2_BASE + 0x58)
#define REG_HDCP_DUAL_P2_2C_H       (REG_HDCP_DUAL_P2_BASE + 0x59)
#define REG_HDCP_DUAL_P2_2D_L       (REG_HDCP_DUAL_P2_BASE + 0x5A)
#define REG_HDCP_DUAL_P2_2D_H       (REG_HDCP_DUAL_P2_BASE + 0x5B)
#define REG_HDCP_DUAL_P2_2E_L       (REG_HDCP_DUAL_P2_BASE + 0x5C)
#define REG_HDCP_DUAL_P2_2E_H       (REG_HDCP_DUAL_P2_BASE + 0x5D)
#define REG_HDCP_DUAL_P2_2F_L       (REG_HDCP_DUAL_P2_BASE + 0x5E)
#define REG_HDCP_DUAL_P2_2F_H       (REG_HDCP_DUAL_P2_BASE + 0x5F)
#define REG_HDCP_DUAL_P2_30_L       (REG_HDCP_DUAL_P2_BASE + 0x60)
#define REG_HDCP_DUAL_P2_30_H       (REG_HDCP_DUAL_P2_BASE + 0x61)
#define REG_HDCP_DUAL_P2_31_L       (REG_HDCP_DUAL_P2_BASE + 0x62)
#define REG_HDCP_DUAL_P2_31_H       (REG_HDCP_DUAL_P2_BASE + 0x63)
#define REG_HDCP_DUAL_P2_32_L       (REG_HDCP_DUAL_P2_BASE + 0x64)
#define REG_HDCP_DUAL_P2_32_H       (REG_HDCP_DUAL_P2_BASE + 0x65)
#define REG_HDCP_DUAL_P2_33_L       (REG_HDCP_DUAL_P2_BASE + 0x66)
#define REG_HDCP_DUAL_P2_33_H       (REG_HDCP_DUAL_P2_BASE + 0x67)
#define REG_HDCP_DUAL_P2_34_L       (REG_HDCP_DUAL_P2_BASE + 0x68)
#define REG_HDCP_DUAL_P2_34_H       (REG_HDCP_DUAL_P2_BASE + 0x69)
#define REG_HDCP_DUAL_P2_35_L       (REG_HDCP_DUAL_P2_BASE + 0x6A)
#define REG_HDCP_DUAL_P2_35_H       (REG_HDCP_DUAL_P2_BASE + 0x6B)
#define REG_HDCP_DUAL_P2_36_L       (REG_HDCP_DUAL_P2_BASE + 0x6C)
#define REG_HDCP_DUAL_P2_36_H       (REG_HDCP_DUAL_P2_BASE + 0x6D)
#define REG_HDCP_DUAL_P2_37_L       (REG_HDCP_DUAL_P2_BASE + 0x6E)
#define REG_HDCP_DUAL_P2_37_H       (REG_HDCP_DUAL_P2_BASE + 0x6F)
#define REG_HDCP_DUAL_P2_38_L       (REG_HDCP_DUAL_P2_BASE + 0x70)
#define REG_HDCP_DUAL_P2_38_H       (REG_HDCP_DUAL_P2_BASE + 0x71)
#define REG_HDCP_DUAL_P2_39_L       (REG_HDCP_DUAL_P2_BASE + 0x72)
#define REG_HDCP_DUAL_P2_39_H       (REG_HDCP_DUAL_P2_BASE + 0x73)
#define REG_HDCP_DUAL_P2_3A_L       (REG_HDCP_DUAL_P2_BASE + 0x74)
#define REG_HDCP_DUAL_P2_3A_H       (REG_HDCP_DUAL_P2_BASE + 0x75)
#define REG_HDCP_DUAL_P2_3B_L       (REG_HDCP_DUAL_P2_BASE + 0x76)
#define REG_HDCP_DUAL_P2_3B_H       (REG_HDCP_DUAL_P2_BASE + 0x77)
#define REG_HDCP_DUAL_P2_3C_L       (REG_HDCP_DUAL_P2_BASE + 0x78)
#define REG_HDCP_DUAL_P2_3C_H       (REG_HDCP_DUAL_P2_BASE + 0x79)
#define REG_HDCP_DUAL_P2_3D_L       (REG_HDCP_DUAL_P2_BASE + 0x7A)
#define REG_HDCP_DUAL_P2_3D_H       (REG_HDCP_DUAL_P2_BASE + 0x7B)
#define REG_HDCP_DUAL_P2_3E_L       (REG_HDCP_DUAL_P2_BASE + 0x7C)
#define REG_HDCP_DUAL_P2_3E_H       (REG_HDCP_DUAL_P2_BASE + 0x7D)
#define REG_HDCP_DUAL_P2_3F_L       (REG_HDCP_DUAL_P2_BASE + 0x7E)
#define REG_HDCP_DUAL_P2_3F_H       (REG_HDCP_DUAL_P2_BASE + 0x7F)
#define REG_HDCP_DUAL_P2_40_L       (REG_HDCP_DUAL_P2_BASE + 0x80)
#define REG_HDCP_DUAL_P2_40_H       (REG_HDCP_DUAL_P2_BASE + 0x81)
#define REG_HDCP_DUAL_P2_41_L       (REG_HDCP_DUAL_P2_BASE + 0x82)
#define REG_HDCP_DUAL_P2_41_H       (REG_HDCP_DUAL_P2_BASE + 0x83)
#define REG_HDCP_DUAL_P2_42_L       (REG_HDCP_DUAL_P2_BASE + 0x84)
#define REG_HDCP_DUAL_P2_42_H       (REG_HDCP_DUAL_P2_BASE + 0x85)
#define REG_HDCP_DUAL_P2_43_L       (REG_HDCP_DUAL_P2_BASE + 0x86)
#define REG_HDCP_DUAL_P2_43_H       (REG_HDCP_DUAL_P2_BASE + 0x87)
#define REG_HDCP_DUAL_P2_44_L       (REG_HDCP_DUAL_P2_BASE + 0x88)
#define REG_HDCP_DUAL_P2_44_H       (REG_HDCP_DUAL_P2_BASE + 0x89)
#define REG_HDCP_DUAL_P2_45_L       (REG_HDCP_DUAL_P2_BASE + 0x8A)
#define REG_HDCP_DUAL_P2_45_H       (REG_HDCP_DUAL_P2_BASE + 0x8B)
#define REG_HDCP_DUAL_P2_46_L       (REG_HDCP_DUAL_P2_BASE + 0x8C)
#define REG_HDCP_DUAL_P2_46_H       (REG_HDCP_DUAL_P2_BASE + 0x8D)
#define REG_HDCP_DUAL_P2_47_L       (REG_HDCP_DUAL_P2_BASE + 0x8E)
#define REG_HDCP_DUAL_P2_47_H       (REG_HDCP_DUAL_P2_BASE + 0x8F)
#define REG_HDCP_DUAL_P2_48_L       (REG_HDCP_DUAL_P2_BASE + 0x90)
#define REG_HDCP_DUAL_P2_48_H       (REG_HDCP_DUAL_P2_BASE + 0x91)
#define REG_HDCP_DUAL_P2_49_L       (REG_HDCP_DUAL_P2_BASE + 0x92)
#define REG_HDCP_DUAL_P2_49_H       (REG_HDCP_DUAL_P2_BASE + 0x93)
#define REG_HDCP_DUAL_P2_4A_L       (REG_HDCP_DUAL_P2_BASE + 0x94)
#define REG_HDCP_DUAL_P2_4A_H       (REG_HDCP_DUAL_P2_BASE + 0x95)
#define REG_HDCP_DUAL_P2_4B_L       (REG_HDCP_DUAL_P2_BASE + 0x96)
#define REG_HDCP_DUAL_P2_4B_H       (REG_HDCP_DUAL_P2_BASE + 0x97)
#define REG_HDCP_DUAL_P2_4C_L       (REG_HDCP_DUAL_P2_BASE + 0x98)
#define REG_HDCP_DUAL_P2_4C_H       (REG_HDCP_DUAL_P2_BASE + 0x99)
#define REG_HDCP_DUAL_P2_4D_L       (REG_HDCP_DUAL_P2_BASE + 0x9A)
#define REG_HDCP_DUAL_P2_4D_H       (REG_HDCP_DUAL_P2_BASE + 0x9B)
#define REG_HDCP_DUAL_P2_4E_L       (REG_HDCP_DUAL_P2_BASE + 0x9C)
#define REG_HDCP_DUAL_P2_4E_H       (REG_HDCP_DUAL_P2_BASE + 0x9D)
#define REG_HDCP_DUAL_P2_4F_L       (REG_HDCP_DUAL_P2_BASE + 0x9E)
#define REG_HDCP_DUAL_P2_4F_H       (REG_HDCP_DUAL_P2_BASE + 0x9F)
#define REG_HDCP_DUAL_P2_50_L       (REG_HDCP_DUAL_P2_BASE + 0xA0)
#define REG_HDCP_DUAL_P2_50_H       (REG_HDCP_DUAL_P2_BASE + 0xA1)
#define REG_HDCP_DUAL_P2_51_L       (REG_HDCP_DUAL_P2_BASE + 0xA2)
#define REG_HDCP_DUAL_P2_51_H       (REG_HDCP_DUAL_P2_BASE + 0xA3)
#define REG_HDCP_DUAL_P2_52_L       (REG_HDCP_DUAL_P2_BASE + 0xA4)
#define REG_HDCP_DUAL_P2_52_H       (REG_HDCP_DUAL_P2_BASE + 0xA5)
#define REG_HDCP_DUAL_P2_53_L       (REG_HDCP_DUAL_P2_BASE + 0xA6)
#define REG_HDCP_DUAL_P2_53_H       (REG_HDCP_DUAL_P2_BASE + 0xA7)
#define REG_HDCP_DUAL_P2_54_L       (REG_HDCP_DUAL_P2_BASE + 0xA8)
#define REG_HDCP_DUAL_P2_54_H       (REG_HDCP_DUAL_P2_BASE + 0xA9)
#define REG_HDCP_DUAL_P2_55_L       (REG_HDCP_DUAL_P2_BASE + 0xAA)
#define REG_HDCP_DUAL_P2_55_H       (REG_HDCP_DUAL_P2_BASE + 0xAB)
#define REG_HDCP_DUAL_P2_56_L       (REG_HDCP_DUAL_P2_BASE + 0xAC)
#define REG_HDCP_DUAL_P2_56_H       (REG_HDCP_DUAL_P2_BASE + 0xAD)
#define REG_HDCP_DUAL_P2_57_L       (REG_HDCP_DUAL_P2_BASE + 0xAE)
#define REG_HDCP_DUAL_P2_57_H       (REG_HDCP_DUAL_P2_BASE + 0xAF)
#define REG_HDCP_DUAL_P2_58_L       (REG_HDCP_DUAL_P2_BASE + 0xB0)
#define REG_HDCP_DUAL_P2_58_H       (REG_HDCP_DUAL_P2_BASE + 0xB1)
#define REG_HDCP_DUAL_P2_59_L       (REG_HDCP_DUAL_P2_BASE + 0xB2)
#define REG_HDCP_DUAL_P2_59_H       (REG_HDCP_DUAL_P2_BASE + 0xB3)
#define REG_HDCP_DUAL_P2_5A_L       (REG_HDCP_DUAL_P2_BASE + 0xB4)
#define REG_HDCP_DUAL_P2_5A_H       (REG_HDCP_DUAL_P2_BASE + 0xB5)
#define REG_HDCP_DUAL_P2_5B_L       (REG_HDCP_DUAL_P2_BASE + 0xB6)
#define REG_HDCP_DUAL_P2_5B_H       (REG_HDCP_DUAL_P2_BASE + 0xB7)
#define REG_HDCP_DUAL_P2_5C_L       (REG_HDCP_DUAL_P2_BASE + 0xB8)
#define REG_HDCP_DUAL_P2_5C_H       (REG_HDCP_DUAL_P2_BASE + 0xB9)
#define REG_HDCP_DUAL_P2_5D_L       (REG_HDCP_DUAL_P2_BASE + 0xBA)
#define REG_HDCP_DUAL_P2_5D_H       (REG_HDCP_DUAL_P2_BASE + 0xBB)
#define REG_HDCP_DUAL_P2_5E_L       (REG_HDCP_DUAL_P2_BASE + 0xBC)
#define REG_HDCP_DUAL_P2_5E_H       (REG_HDCP_DUAL_P2_BASE + 0xBD)
#define REG_HDCP_DUAL_P2_5F_L       (REG_HDCP_DUAL_P2_BASE + 0xBE)
#define REG_HDCP_DUAL_P2_5F_H       (REG_HDCP_DUAL_P2_BASE + 0xBF)
#define REG_HDCP_DUAL_P2_60_L       (REG_HDCP_DUAL_P2_BASE + 0xC0)
#define REG_HDCP_DUAL_P2_60_H       (REG_HDCP_DUAL_P2_BASE + 0xC1)
#define REG_HDCP_DUAL_P2_61_L       (REG_HDCP_DUAL_P2_BASE + 0xC2)
#define REG_HDCP_DUAL_P2_61_H       (REG_HDCP_DUAL_P2_BASE + 0xC3)
#define REG_HDCP_DUAL_P2_62_L       (REG_HDCP_DUAL_P2_BASE + 0xC4)
#define REG_HDCP_DUAL_P2_62_H       (REG_HDCP_DUAL_P2_BASE + 0xC5)
#define REG_HDCP_DUAL_P2_63_L       (REG_HDCP_DUAL_P2_BASE + 0xC6)
#define REG_HDCP_DUAL_P2_63_H       (REG_HDCP_DUAL_P2_BASE + 0xC7)
#define REG_HDCP_DUAL_P2_64_L       (REG_HDCP_DUAL_P2_BASE + 0xC8)
#define REG_HDCP_DUAL_P2_64_H       (REG_HDCP_DUAL_P2_BASE + 0xC9)
#define REG_HDCP_DUAL_P2_65_L       (REG_HDCP_DUAL_P2_BASE + 0xCA)
#define REG_HDCP_DUAL_P2_65_H       (REG_HDCP_DUAL_P2_BASE + 0xCB)
#define REG_HDCP_DUAL_P2_66_L       (REG_HDCP_DUAL_P2_BASE + 0xCC)
#define REG_HDCP_DUAL_P2_66_H       (REG_HDCP_DUAL_P2_BASE + 0xCD)
#define REG_HDCP_DUAL_P2_67_L       (REG_HDCP_DUAL_P2_BASE + 0xCE)
#define REG_HDCP_DUAL_P2_67_H       (REG_HDCP_DUAL_P2_BASE + 0xCF)
#define REG_HDCP_DUAL_P2_68_L       (REG_HDCP_DUAL_P2_BASE + 0xD0)
#define REG_HDCP_DUAL_P2_68_H       (REG_HDCP_DUAL_P2_BASE + 0xD1)

// DVI_DTOP_DUAL_P3
#define REG_DVI_DTOP_DUAL_P3_00_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x00)
#define REG_DVI_DTOP_DUAL_P3_00_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x01)
#define REG_DVI_DTOP_DUAL_P3_01_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x02)
#define REG_DVI_DTOP_DUAL_P3_01_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x03)
#define REG_DVI_DTOP_DUAL_P3_02_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x04)
#define REG_DVI_DTOP_DUAL_P3_02_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x05)
#define REG_DVI_DTOP_DUAL_P3_03_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x06)
#define REG_DVI_DTOP_DUAL_P3_03_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x07)
#define REG_DVI_DTOP_DUAL_P3_04_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x08)
#define REG_DVI_DTOP_DUAL_P3_04_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x09)
#define REG_DVI_DTOP_DUAL_P3_05_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0A)
#define REG_DVI_DTOP_DUAL_P3_05_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0B)
#define REG_DVI_DTOP_DUAL_P3_06_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0C)
#define REG_DVI_DTOP_DUAL_P3_06_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0D)
#define REG_DVI_DTOP_DUAL_P3_07_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0E)
#define REG_DVI_DTOP_DUAL_P3_07_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0F)
#define REG_DVI_DTOP_DUAL_P3_08_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x10)
#define REG_DVI_DTOP_DUAL_P3_08_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x11)
#define REG_DVI_DTOP_DUAL_P3_09_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x12)
#define REG_DVI_DTOP_DUAL_P3_09_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x13)
#define REG_DVI_DTOP_DUAL_P3_0A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x14)
#define REG_DVI_DTOP_DUAL_P3_0A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x15)
#define REG_DVI_DTOP_DUAL_P3_0B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x16)
#define REG_DVI_DTOP_DUAL_P3_0B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x17)
#define REG_DVI_DTOP_DUAL_P3_0C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x18)
#define REG_DVI_DTOP_DUAL_P3_0C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x19)
#define REG_DVI_DTOP_DUAL_P3_0D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1A)
#define REG_DVI_DTOP_DUAL_P3_0D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1B)
#define REG_DVI_DTOP_DUAL_P3_0E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1C)
#define REG_DVI_DTOP_DUAL_P3_0E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1D)
#define REG_DVI_DTOP_DUAL_P3_0F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1E)
#define REG_DVI_DTOP_DUAL_P3_0F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1F)
#define REG_DVI_DTOP_DUAL_P3_10_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x20)
#define REG_DVI_DTOP_DUAL_P3_10_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x21)
#define REG_DVI_DTOP_DUAL_P3_11_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x22)
#define REG_DVI_DTOP_DUAL_P3_11_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x23)
#define REG_DVI_DTOP_DUAL_P3_12_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x24)
#define REG_DVI_DTOP_DUAL_P3_12_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x25)
#define REG_DVI_DTOP_DUAL_P3_13_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x26)
#define REG_DVI_DTOP_DUAL_P3_13_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x27)
#define REG_DVI_DTOP_DUAL_P3_14_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x28)
#define REG_DVI_DTOP_DUAL_P3_14_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x29)
#define REG_DVI_DTOP_DUAL_P3_15_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2A)
#define REG_DVI_DTOP_DUAL_P3_15_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2B)
#define REG_DVI_DTOP_DUAL_P3_16_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2C)
#define REG_DVI_DTOP_DUAL_P3_16_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2D)
#define REG_DVI_DTOP_DUAL_P3_17_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2E)
#define REG_DVI_DTOP_DUAL_P3_17_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2F)
#define REG_DVI_DTOP_DUAL_P3_18_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x30)
#define REG_DVI_DTOP_DUAL_P3_18_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x31)
#define REG_DVI_DTOP_DUAL_P3_19_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x32)
#define REG_DVI_DTOP_DUAL_P3_19_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x33)
#define REG_DVI_DTOP_DUAL_P3_1A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x34)
#define REG_DVI_DTOP_DUAL_P3_1A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x35)
#define REG_DVI_DTOP_DUAL_P3_1B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x36)
#define REG_DVI_DTOP_DUAL_P3_1B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x37)
#define REG_DVI_DTOP_DUAL_P3_1C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x38)
#define REG_DVI_DTOP_DUAL_P3_1C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x39)
#define REG_DVI_DTOP_DUAL_P3_1D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3A)
#define REG_DVI_DTOP_DUAL_P3_1D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3B)
#define REG_DVI_DTOP_DUAL_P3_1E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3C)
#define REG_DVI_DTOP_DUAL_P3_1E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3D)
#define REG_DVI_DTOP_DUAL_P3_1F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3E)
#define REG_DVI_DTOP_DUAL_P3_1F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3F)
#define REG_DVI_DTOP_DUAL_P3_20_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x40)
#define REG_DVI_DTOP_DUAL_P3_20_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x41)
#define REG_DVI_DTOP_DUAL_P3_21_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x42)
#define REG_DVI_DTOP_DUAL_P3_21_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x43)
#define REG_DVI_DTOP_DUAL_P3_22_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x44)
#define REG_DVI_DTOP_DUAL_P3_22_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x45)
#define REG_DVI_DTOP_DUAL_P3_23_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x46)
#define REG_DVI_DTOP_DUAL_P3_23_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x47)
#define REG_DVI_DTOP_DUAL_P3_24_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x48)
#define REG_DVI_DTOP_DUAL_P3_24_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x49)
#define REG_DVI_DTOP_DUAL_P3_25_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4A)
#define REG_DVI_DTOP_DUAL_P3_25_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4B)
#define REG_DVI_DTOP_DUAL_P3_26_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4C)
#define REG_DVI_DTOP_DUAL_P3_26_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4D)
#define REG_DVI_DTOP_DUAL_P3_27_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4E)
#define REG_DVI_DTOP_DUAL_P3_27_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4F)
#define REG_DVI_DTOP_DUAL_P3_28_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x50)
#define REG_DVI_DTOP_DUAL_P3_28_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x51)
#define REG_DVI_DTOP_DUAL_P3_29_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x52)
#define REG_DVI_DTOP_DUAL_P3_29_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x53)
#define REG_DVI_DTOP_DUAL_P3_2A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x54)
#define REG_DVI_DTOP_DUAL_P3_2A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x55)
#define REG_DVI_DTOP_DUAL_P3_2B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x56)
#define REG_DVI_DTOP_DUAL_P3_2B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x57)
#define REG_DVI_DTOP_DUAL_P3_2C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x58)
#define REG_DVI_DTOP_DUAL_P3_2C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x59)
#define REG_DVI_DTOP_DUAL_P3_2D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5A)
#define REG_DVI_DTOP_DUAL_P3_2D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5B)
#define REG_DVI_DTOP_DUAL_P3_2E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5C)
#define REG_DVI_DTOP_DUAL_P3_2E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5D)
#define REG_DVI_DTOP_DUAL_P3_2F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5E)
#define REG_DVI_DTOP_DUAL_P3_2F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5F)
#define REG_DVI_DTOP_DUAL_P3_30_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x60)
#define REG_DVI_DTOP_DUAL_P3_30_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x61)
#define REG_DVI_DTOP_DUAL_P3_31_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x62)
#define REG_DVI_DTOP_DUAL_P3_31_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x63)
#define REG_DVI_DTOP_DUAL_P3_32_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x64)
#define REG_DVI_DTOP_DUAL_P3_32_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x65)
#define REG_DVI_DTOP_DUAL_P3_33_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x66)
#define REG_DVI_DTOP_DUAL_P3_33_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x67)
#define REG_DVI_DTOP_DUAL_P3_34_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x68)
#define REG_DVI_DTOP_DUAL_P3_34_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x69)
#define REG_DVI_DTOP_DUAL_P3_35_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6A)
#define REG_DVI_DTOP_DUAL_P3_35_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6B)
#define REG_DVI_DTOP_DUAL_P3_36_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6C)
#define REG_DVI_DTOP_DUAL_P3_36_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6D)
#define REG_DVI_DTOP_DUAL_P3_37_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6E)
#define REG_DVI_DTOP_DUAL_P3_37_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6F)
#define REG_DVI_DTOP_DUAL_P3_38_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x70)
#define REG_DVI_DTOP_DUAL_P3_38_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x71)
#define REG_DVI_DTOP_DUAL_P3_39_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x72)
#define REG_DVI_DTOP_DUAL_P3_39_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x73)
#define REG_DVI_DTOP_DUAL_P3_3A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x74)
#define REG_DVI_DTOP_DUAL_P3_3A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x75)
#define REG_DVI_DTOP_DUAL_P3_3B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x76)
#define REG_DVI_DTOP_DUAL_P3_3B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x77)
#define REG_DVI_DTOP_DUAL_P3_3C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x78)
#define REG_DVI_DTOP_DUAL_P3_3C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x79)
#define REG_DVI_DTOP_DUAL_P3_3D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7A)
#define REG_DVI_DTOP_DUAL_P3_3D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7B)
#define REG_DVI_DTOP_DUAL_P3_3E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7C)
#define REG_DVI_DTOP_DUAL_P3_3E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7D)
#define REG_DVI_DTOP_DUAL_P3_3F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7E)
#define REG_DVI_DTOP_DUAL_P3_3F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7F)
#define REG_DVI_DTOP_DUAL_P3_40_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x80)
#define REG_DVI_DTOP_DUAL_P3_40_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x81)
#define REG_DVI_DTOP_DUAL_P3_41_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x82)
#define REG_DVI_DTOP_DUAL_P3_41_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x83)
#define REG_DVI_DTOP_DUAL_P3_42_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x84)
#define REG_DVI_DTOP_DUAL_P3_42_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x85)
#define REG_DVI_DTOP_DUAL_P3_43_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x86)
#define REG_DVI_DTOP_DUAL_P3_43_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x87)
#define REG_DVI_DTOP_DUAL_P3_44_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x88)
#define REG_DVI_DTOP_DUAL_P3_44_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x89)
#define REG_DVI_DTOP_DUAL_P3_45_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8A)
#define REG_DVI_DTOP_DUAL_P3_45_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8B)
#define REG_DVI_DTOP_DUAL_P3_46_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8C)
#define REG_DVI_DTOP_DUAL_P3_46_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8D)
#define REG_DVI_DTOP_DUAL_P3_47_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8E)
#define REG_DVI_DTOP_DUAL_P3_47_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8F)
#define REG_DVI_DTOP_DUAL_P3_48_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x90)
#define REG_DVI_DTOP_DUAL_P3_48_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x91)
#define REG_DVI_DTOP_DUAL_P3_49_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x92)
#define REG_DVI_DTOP_DUAL_P3_49_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x93)
#define REG_DVI_DTOP_DUAL_P3_4A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x94)
#define REG_DVI_DTOP_DUAL_P3_4A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x95)
#define REG_DVI_DTOP_DUAL_P3_4B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x96)
#define REG_DVI_DTOP_DUAL_P3_4B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x97)
#define REG_DVI_DTOP_DUAL_P3_4C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x98)
#define REG_DVI_DTOP_DUAL_P3_4C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x99)
#define REG_DVI_DTOP_DUAL_P3_4D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9A)
#define REG_DVI_DTOP_DUAL_P3_4D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9B)
#define REG_DVI_DTOP_DUAL_P3_4E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9C)
#define REG_DVI_DTOP_DUAL_P3_4E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9D)
#define REG_DVI_DTOP_DUAL_P3_4F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9E)
#define REG_DVI_DTOP_DUAL_P3_4F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9F)
#define REG_DVI_DTOP_DUAL_P3_50_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA0)
#define REG_DVI_DTOP_DUAL_P3_50_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA1)
#define REG_DVI_DTOP_DUAL_P3_51_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA2)
#define REG_DVI_DTOP_DUAL_P3_51_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA3)
#define REG_DVI_DTOP_DUAL_P3_52_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA4)
#define REG_DVI_DTOP_DUAL_P3_52_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA5)
#define REG_DVI_DTOP_DUAL_P3_53_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA6)
#define REG_DVI_DTOP_DUAL_P3_53_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA7)
#define REG_DVI_DTOP_DUAL_P3_54_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA8)
#define REG_DVI_DTOP_DUAL_P3_54_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA9)
#define REG_DVI_DTOP_DUAL_P3_55_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAA)
#define REG_DVI_DTOP_DUAL_P3_55_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAB)
#define REG_DVI_DTOP_DUAL_P3_56_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAC)
#define REG_DVI_DTOP_DUAL_P3_56_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAD)
#define REG_DVI_DTOP_DUAL_P3_57_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAE)
#define REG_DVI_DTOP_DUAL_P3_57_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAF)
#define REG_DVI_DTOP_DUAL_P3_58_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB0)
#define REG_DVI_DTOP_DUAL_P3_58_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB1)
#define REG_DVI_DTOP_DUAL_P3_59_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB2)
#define REG_DVI_DTOP_DUAL_P3_59_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB3)
#define REG_DVI_DTOP_DUAL_P3_5A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB4)
#define REG_DVI_DTOP_DUAL_P3_5A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB5)
#define REG_DVI_DTOP_DUAL_P3_5B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB6)
#define REG_DVI_DTOP_DUAL_P3_5B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB7)
#define REG_DVI_DTOP_DUAL_P3_5C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB8)
#define REG_DVI_DTOP_DUAL_P3_5C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB9)
#define REG_DVI_DTOP_DUAL_P3_5D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBA)
#define REG_DVI_DTOP_DUAL_P3_5D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBB)
#define REG_DVI_DTOP_DUAL_P3_5E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBC)
#define REG_DVI_DTOP_DUAL_P3_5E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBD)
#define REG_DVI_DTOP_DUAL_P3_5F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBE)
#define REG_DVI_DTOP_DUAL_P3_5F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBF)
#define REG_DVI_DTOP_DUAL_P3_60_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC0)
#define REG_DVI_DTOP_DUAL_P3_60_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC1)
#define REG_DVI_DTOP_DUAL_P3_61_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC2)
#define REG_DVI_DTOP_DUAL_P3_61_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC3)
#define REG_DVI_DTOP_DUAL_P3_62_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC4)
#define REG_DVI_DTOP_DUAL_P3_62_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC5)
#define REG_DVI_DTOP_DUAL_P3_63_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6)
#define REG_DVI_DTOP_DUAL_P3_63_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC7)
#define REG_DVI_DTOP_DUAL_P3_64_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC8)
#define REG_DVI_DTOP_DUAL_P3_64_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC9)
#define REG_DVI_DTOP_DUAL_P3_65_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCA)
#define REG_DVI_DTOP_DUAL_P3_65_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCB)
#define REG_DVI_DTOP_DUAL_P3_66_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCC)
#define REG_DVI_DTOP_DUAL_P3_66_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCD)
#define REG_DVI_DTOP_DUAL_P3_67_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCE)
#define REG_DVI_DTOP_DUAL_P3_67_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCF)
#define REG_DVI_DTOP_DUAL_P3_68_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD0)
#define REG_DVI_DTOP_DUAL_P3_68_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD1)
#define REG_DVI_DTOP_DUAL_P3_69_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD2)
#define REG_DVI_DTOP_DUAL_P3_69_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD3)
#define REG_DVI_DTOP_DUAL_P3_6A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD4)
#define REG_DVI_DTOP_DUAL_P3_6A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD5)
#define REG_DVI_DTOP_DUAL_P3_6B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD6)
#define REG_DVI_DTOP_DUAL_P3_6B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD7)
#define REG_DVI_DTOP_DUAL_P3_6C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD8)
#define REG_DVI_DTOP_DUAL_P3_6C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD9)
#define REG_DVI_DTOP_DUAL_P3_6D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDA)
#define REG_DVI_DTOP_DUAL_P3_6D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDB)
#define REG_DVI_DTOP_DUAL_P3_6E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDC)
#define REG_DVI_DTOP_DUAL_P3_6E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDD)
#define REG_DVI_DTOP_DUAL_P3_6F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDE)
#define REG_DVI_DTOP_DUAL_P3_6F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDF)
#define REG_DVI_DTOP_DUAL_P3_70_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE0)
#define REG_DVI_DTOP_DUAL_P3_70_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE1)
#define REG_DVI_DTOP_DUAL_P3_71_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE2)
#define REG_DVI_DTOP_DUAL_P3_71_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE3)
#define REG_DVI_DTOP_DUAL_P3_72_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE4)
#define REG_DVI_DTOP_DUAL_P3_72_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE5)
#define REG_DVI_DTOP_DUAL_P3_73_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE6)
#define REG_DVI_DTOP_DUAL_P3_73_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE7)
#define REG_DVI_DTOP_DUAL_P3_74_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE8)
#define REG_DVI_DTOP_DUAL_P3_74_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE9)
#define REG_DVI_DTOP_DUAL_P3_75_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEA)
#define REG_DVI_DTOP_DUAL_P3_75_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEB)
#define REG_DVI_DTOP_DUAL_P3_76_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEC)
#define REG_DVI_DTOP_DUAL_P3_76_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xED)
#define REG_DVI_DTOP_DUAL_P3_77_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEE)
#define REG_DVI_DTOP_DUAL_P3_77_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEF)
#define REG_DVI_DTOP_DUAL_P3_78_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF0)
#define REG_DVI_DTOP_DUAL_P3_78_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF1)
#define REG_DVI_DTOP_DUAL_P3_79_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF2)
#define REG_DVI_DTOP_DUAL_P3_79_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF3)
#define REG_DVI_DTOP_DUAL_P3_7A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF4)
#define REG_DVI_DTOP_DUAL_P3_7A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF5)
#define REG_DVI_DTOP_DUAL_P3_7B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF6)
#define REG_DVI_DTOP_DUAL_P3_7B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF7)
#define REG_DVI_DTOP_DUAL_P3_7C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF8)
#define REG_DVI_DTOP_DUAL_P3_7C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF9)
#define REG_DVI_DTOP_DUAL_P3_7D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFA)
#define REG_DVI_DTOP_DUAL_P3_7D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFB)
#define REG_DVI_DTOP_DUAL_P3_7E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFC)
#define REG_DVI_DTOP_DUAL_P3_7E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFD)
#define REG_DVI_DTOP_DUAL_P3_7F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFE)
#define REG_DVI_DTOP_DUAL_P3_7F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFF)

// DVI_RSV_DUAL_P3
#define REG_DVI_RSV_DUAL_P3_00_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
#define REG_DVI_RSV_DUAL_P3_00_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
#define REG_DVI_RSV_DUAL_P3_01_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
#define REG_DVI_RSV_DUAL_P3_01_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
#define REG_DVI_RSV_DUAL_P3_02_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
#define REG_DVI_RSV_DUAL_P3_02_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
#define REG_DVI_RSV_DUAL_P3_03_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
#define REG_DVI_RSV_DUAL_P3_03_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
#define REG_DVI_RSV_DUAL_P3_04_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
#define REG_DVI_RSV_DUAL_P3_04_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
#define REG_DVI_RSV_DUAL_P3_05_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0A)
#define REG_DVI_RSV_DUAL_P3_05_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0B)
#define REG_DVI_RSV_DUAL_P3_06_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0C)
#define REG_DVI_RSV_DUAL_P3_06_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0D)
#define REG_DVI_RSV_DUAL_P3_07_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0E)
#define REG_DVI_RSV_DUAL_P3_07_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0F)
#define REG_DVI_RSV_DUAL_P3_08_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x10)
#define REG_DVI_RSV_DUAL_P3_08_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x11)
#define REG_DVI_RSV_DUAL_P3_09_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x12)
#define REG_DVI_RSV_DUAL_P3_09_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x13)
#define REG_DVI_RSV_DUAL_P3_0A_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x14)
#define REG_DVI_RSV_DUAL_P3_0A_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x15)
#define REG_DVI_RSV_DUAL_P3_0B_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x16)
#define REG_DVI_RSV_DUAL_P3_0B_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x17)
#define REG_DVI_RSV_DUAL_P3_0C_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x18)
#define REG_DVI_RSV_DUAL_P3_0C_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x19)
#define REG_DVI_RSV_DUAL_P3_0D_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1A)
#define REG_DVI_RSV_DUAL_P3_0D_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1B)
#define REG_DVI_RSV_DUAL_P3_0E_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1C)
#define REG_DVI_RSV_DUAL_P3_0E_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1D)
#define REG_DVI_RSV_DUAL_P3_0F_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1E)
#define REG_DVI_RSV_DUAL_P3_0F_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1F)
#define REG_DVI_RSV_DUAL_P3_10_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x20)
#define REG_DVI_RSV_DUAL_P3_10_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x21)
#define REG_DVI_RSV_DUAL_P3_11_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x22)
#define REG_DVI_RSV_DUAL_P3_11_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x23)
#define REG_DVI_RSV_DUAL_P3_12_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x24)
#define REG_DVI_RSV_DUAL_P3_12_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x25)
#define REG_DVI_RSV_DUAL_P3_13_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x26)
#define REG_DVI_RSV_DUAL_P3_13_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x27)
#define REG_DVI_RSV_DUAL_P3_14_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x28)
#define REG_DVI_RSV_DUAL_P3_14_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x29)
#define REG_DVI_RSV_DUAL_P3_15_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2A)
#define REG_DVI_RSV_DUAL_P3_15_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2B)
#define REG_DVI_RSV_DUAL_P3_16_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2C)
#define REG_DVI_RSV_DUAL_P3_16_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2D)
#define REG_DVI_RSV_DUAL_P3_17_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2E)
#define REG_DVI_RSV_DUAL_P3_17_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2F)
#define REG_DVI_RSV_DUAL_P3_18_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x30)
#define REG_DVI_RSV_DUAL_P3_18_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x31)
#define REG_DVI_RSV_DUAL_P3_19_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x32)
#define REG_DVI_RSV_DUAL_P3_19_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x33)
#define REG_DVI_RSV_DUAL_P3_1A_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x34)
#define REG_DVI_RSV_DUAL_P3_1A_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x35)
#define REG_DVI_RSV_DUAL_P3_1B_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x36)
#define REG_DVI_RSV_DUAL_P3_1B_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x37)
#define REG_DVI_RSV_DUAL_P3_1C_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x38)
#define REG_DVI_RSV_DUAL_P3_1C_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x39)
#define REG_DVI_RSV_DUAL_P3_1D_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3A)
#define REG_DVI_RSV_DUAL_P3_1D_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3B)
#define REG_DVI_RSV_DUAL_P3_1E_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3C)
#define REG_DVI_RSV_DUAL_P3_1E_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3D)
#define REG_DVI_RSV_DUAL_P3_1F_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3E)
#define REG_DVI_RSV_DUAL_P3_1F_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3F)

// HDCP_DUAL_P3
#define REG_HDCP_DUAL_P3_00_L       (REG_HDCP_DUAL_P3_BASE + 0x00)
#define REG_HDCP_DUAL_P3_00_H       (REG_HDCP_DUAL_P3_BASE + 0x01)
#define REG_HDCP_DUAL_P3_01_L       (REG_HDCP_DUAL_P3_BASE + 0x02)
#define REG_HDCP_DUAL_P3_01_H       (REG_HDCP_DUAL_P3_BASE + 0x03)
#define REG_HDCP_DUAL_P3_02_L       (REG_HDCP_DUAL_P3_BASE + 0x04)
#define REG_HDCP_DUAL_P3_02_H       (REG_HDCP_DUAL_P3_BASE + 0x05)
#define REG_HDCP_DUAL_P3_03_L       (REG_HDCP_DUAL_P3_BASE + 0x06)
#define REG_HDCP_DUAL_P3_03_H       (REG_HDCP_DUAL_P3_BASE + 0x07)
#define REG_HDCP_DUAL_P3_04_L       (REG_HDCP_DUAL_P3_BASE + 0x08)
#define REG_HDCP_DUAL_P3_04_H       (REG_HDCP_DUAL_P3_BASE + 0x09)
#define REG_HDCP_DUAL_P3_05_L       (REG_HDCP_DUAL_P3_BASE + 0x0A)
#define REG_HDCP_DUAL_P3_05_H       (REG_HDCP_DUAL_P3_BASE + 0x0B)
#define REG_HDCP_DUAL_P3_06_L       (REG_HDCP_DUAL_P3_BASE + 0x0C)
#define REG_HDCP_DUAL_P3_06_H       (REG_HDCP_DUAL_P3_BASE + 0x0D)
#define REG_HDCP_DUAL_P3_07_L       (REG_HDCP_DUAL_P3_BASE + 0x0E)
#define REG_HDCP_DUAL_P3_07_H       (REG_HDCP_DUAL_P3_BASE + 0x0F)
#define REG_HDCP_DUAL_P3_08_L       (REG_HDCP_DUAL_P3_BASE + 0x10)
#define REG_HDCP_DUAL_P3_08_H       (REG_HDCP_DUAL_P3_BASE + 0x11)
#define REG_HDCP_DUAL_P3_09_L       (REG_HDCP_DUAL_P3_BASE + 0x12)
#define REG_HDCP_DUAL_P3_09_H       (REG_HDCP_DUAL_P3_BASE + 0x13)
#define REG_HDCP_DUAL_P3_0A_L       (REG_HDCP_DUAL_P3_BASE + 0x14)
#define REG_HDCP_DUAL_P3_0A_H       (REG_HDCP_DUAL_P3_BASE + 0x15)
#define REG_HDCP_DUAL_P3_0B_L       (REG_HDCP_DUAL_P3_BASE + 0x16)
#define REG_HDCP_DUAL_P3_0B_H       (REG_HDCP_DUAL_P3_BASE + 0x17)
#define REG_HDCP_DUAL_P3_0C_L       (REG_HDCP_DUAL_P3_BASE + 0x18)
#define REG_HDCP_DUAL_P3_0C_H       (REG_HDCP_DUAL_P3_BASE + 0x19)
#define REG_HDCP_DUAL_P3_0D_L       (REG_HDCP_DUAL_P3_BASE + 0x1A)
#define REG_HDCP_DUAL_P3_0D_H       (REG_HDCP_DUAL_P3_BASE + 0x1B)
#define REG_HDCP_DUAL_P3_0E_L       (REG_HDCP_DUAL_P3_BASE + 0x1C)
#define REG_HDCP_DUAL_P3_0E_H       (REG_HDCP_DUAL_P3_BASE + 0x1D)
#define REG_HDCP_DUAL_P3_0F_L       (REG_HDCP_DUAL_P3_BASE + 0x1E)
#define REG_HDCP_DUAL_P3_0F_H       (REG_HDCP_DUAL_P3_BASE + 0x1F)
#define REG_HDCP_DUAL_P3_10_L       (REG_HDCP_DUAL_P3_BASE + 0x20)
#define REG_HDCP_DUAL_P3_10_H       (REG_HDCP_DUAL_P3_BASE + 0x21)
#define REG_HDCP_DUAL_P3_11_L       (REG_HDCP_DUAL_P3_BASE + 0x22)
#define REG_HDCP_DUAL_P3_11_H       (REG_HDCP_DUAL_P3_BASE + 0x23)
#define REG_HDCP_DUAL_P3_12_L       (REG_HDCP_DUAL_P3_BASE + 0x24)
#define REG_HDCP_DUAL_P3_12_H       (REG_HDCP_DUAL_P3_BASE + 0x25)
#define REG_HDCP_DUAL_P3_13_L       (REG_HDCP_DUAL_P3_BASE + 0x26)
#define REG_HDCP_DUAL_P3_13_H       (REG_HDCP_DUAL_P3_BASE + 0x27)
#define REG_HDCP_DUAL_P3_14_L       (REG_HDCP_DUAL_P3_BASE + 0x28)
#define REG_HDCP_DUAL_P3_14_H       (REG_HDCP_DUAL_P3_BASE + 0x29)
#define REG_HDCP_DUAL_P3_15_L       (REG_HDCP_DUAL_P3_BASE + 0x2A)
#define REG_HDCP_DUAL_P3_15_H       (REG_HDCP_DUAL_P3_BASE + 0x2B)
#define REG_HDCP_DUAL_P3_16_L       (REG_HDCP_DUAL_P3_BASE + 0x2C)
#define REG_HDCP_DUAL_P3_16_H       (REG_HDCP_DUAL_P3_BASE + 0x2D)
#define REG_HDCP_DUAL_P3_17_L       (REG_HDCP_DUAL_P3_BASE + 0x2E)
#define REG_HDCP_DUAL_P3_17_H       (REG_HDCP_DUAL_P3_BASE + 0x2F)
#define REG_HDCP_DUAL_P3_18_L       (REG_HDCP_DUAL_P3_BASE + 0x30)
#define REG_HDCP_DUAL_P3_18_H       (REG_HDCP_DUAL_P3_BASE + 0x31)
#define REG_HDCP_DUAL_P3_19_L       (REG_HDCP_DUAL_P3_BASE + 0x32)
#define REG_HDCP_DUAL_P3_19_H       (REG_HDCP_DUAL_P3_BASE + 0x33)
#define REG_HDCP_DUAL_P3_1A_L       (REG_HDCP_DUAL_P3_BASE + 0x34)
#define REG_HDCP_DUAL_P3_1A_H       (REG_HDCP_DUAL_P3_BASE + 0x35)
#define REG_HDCP_DUAL_P3_1B_L       (REG_HDCP_DUAL_P3_BASE + 0x36)
#define REG_HDCP_DUAL_P3_1B_H       (REG_HDCP_DUAL_P3_BASE + 0x37)
#define REG_HDCP_DUAL_P3_1C_L       (REG_HDCP_DUAL_P3_BASE + 0x38)
#define REG_HDCP_DUAL_P3_1C_H       (REG_HDCP_DUAL_P3_BASE + 0x39)
#define REG_HDCP_DUAL_P3_1D_L       (REG_HDCP_DUAL_P3_BASE + 0x3A)
#define REG_HDCP_DUAL_P3_1D_H       (REG_HDCP_DUAL_P3_BASE + 0x3B)
#define REG_HDCP_DUAL_P3_1E_L       (REG_HDCP_DUAL_P3_BASE + 0x3C)
#define REG_HDCP_DUAL_P3_1E_H       (REG_HDCP_DUAL_P3_BASE + 0x3D)
#define REG_HDCP_DUAL_P3_1F_L       (REG_HDCP_DUAL_P3_BASE + 0x3E)
#define REG_HDCP_DUAL_P3_1F_H       (REG_HDCP_DUAL_P3_BASE + 0x3F)
#define REG_HDCP_DUAL_P3_20_L       (REG_HDCP_DUAL_P3_BASE + 0x40)
#define REG_HDCP_DUAL_P3_20_H       (REG_HDCP_DUAL_P3_BASE + 0x41)
#define REG_HDCP_DUAL_P3_21_L       (REG_HDCP_DUAL_P3_BASE + 0x42)
#define REG_HDCP_DUAL_P3_21_H       (REG_HDCP_DUAL_P3_BASE + 0x43)
#define REG_HDCP_DUAL_P3_22_L       (REG_HDCP_DUAL_P3_BASE + 0x44)
#define REG_HDCP_DUAL_P3_22_H       (REG_HDCP_DUAL_P3_BASE + 0x45)
#define REG_HDCP_DUAL_P3_23_L       (REG_HDCP_DUAL_P3_BASE + 0x46)
#define REG_HDCP_DUAL_P3_23_H       (REG_HDCP_DUAL_P3_BASE + 0x47)
#define REG_HDCP_DUAL_P3_24_L       (REG_HDCP_DUAL_P3_BASE + 0x48)
#define REG_HDCP_DUAL_P3_24_H       (REG_HDCP_DUAL_P3_BASE + 0x49)
#define REG_HDCP_DUAL_P3_25_L       (REG_HDCP_DUAL_P3_BASE + 0x4A)
#define REG_HDCP_DUAL_P3_25_H       (REG_HDCP_DUAL_P3_BASE + 0x4B)
#define REG_HDCP_DUAL_P3_26_L       (REG_HDCP_DUAL_P3_BASE + 0x4C)
#define REG_HDCP_DUAL_P3_26_H       (REG_HDCP_DUAL_P3_BASE + 0x4D)
#define REG_HDCP_DUAL_P3_27_L       (REG_HDCP_DUAL_P3_BASE + 0x4E)
#define REG_HDCP_DUAL_P3_27_H       (REG_HDCP_DUAL_P3_BASE + 0x4F)
#define REG_HDCP_DUAL_P3_28_L       (REG_HDCP_DUAL_P3_BASE + 0x50)
#define REG_HDCP_DUAL_P3_28_H       (REG_HDCP_DUAL_P3_BASE + 0x51)
#define REG_HDCP_DUAL_P3_29_L       (REG_HDCP_DUAL_P3_BASE + 0x52)
#define REG_HDCP_DUAL_P3_29_H       (REG_HDCP_DUAL_P3_BASE + 0x53)
#define REG_HDCP_DUAL_P3_2A_L       (REG_HDCP_DUAL_P3_BASE + 0x54)
#define REG_HDCP_DUAL_P3_2A_H       (REG_HDCP_DUAL_P3_BASE + 0x55)
#define REG_HDCP_DUAL_P3_2B_L       (REG_HDCP_DUAL_P3_BASE + 0x56)
#define REG_HDCP_DUAL_P3_2B_H       (REG_HDCP_DUAL_P3_BASE + 0x57)
#define REG_HDCP_DUAL_P3_2C_L       (REG_HDCP_DUAL_P3_BASE + 0x58)
#define REG_HDCP_DUAL_P3_2C_H       (REG_HDCP_DUAL_P3_BASE + 0x59)
#define REG_HDCP_DUAL_P3_2D_L       (REG_HDCP_DUAL_P3_BASE + 0x5A)
#define REG_HDCP_DUAL_P3_2D_H       (REG_HDCP_DUAL_P3_BASE + 0x5B)
#define REG_HDCP_DUAL_P3_2E_L       (REG_HDCP_DUAL_P3_BASE + 0x5C)
#define REG_HDCP_DUAL_P3_2E_H       (REG_HDCP_DUAL_P3_BASE + 0x5D)
#define REG_HDCP_DUAL_P3_2F_L       (REG_HDCP_DUAL_P3_BASE + 0x5E)
#define REG_HDCP_DUAL_P3_2F_H       (REG_HDCP_DUAL_P3_BASE + 0x5F)
#define REG_HDCP_DUAL_P3_30_L       (REG_HDCP_DUAL_P3_BASE + 0x60)
#define REG_HDCP_DUAL_P3_30_H       (REG_HDCP_DUAL_P3_BASE + 0x61)
#define REG_HDCP_DUAL_P3_31_L       (REG_HDCP_DUAL_P3_BASE + 0x62)
#define REG_HDCP_DUAL_P3_31_H       (REG_HDCP_DUAL_P3_BASE + 0x63)
#define REG_HDCP_DUAL_P3_32_L       (REG_HDCP_DUAL_P3_BASE + 0x64)
#define REG_HDCP_DUAL_P3_32_H       (REG_HDCP_DUAL_P3_BASE + 0x65)
#define REG_HDCP_DUAL_P3_33_L       (REG_HDCP_DUAL_P3_BASE + 0x66)
#define REG_HDCP_DUAL_P3_33_H       (REG_HDCP_DUAL_P3_BASE + 0x67)
#define REG_HDCP_DUAL_P3_34_L       (REG_HDCP_DUAL_P3_BASE + 0x68)
#define REG_HDCP_DUAL_P3_34_H       (REG_HDCP_DUAL_P3_BASE + 0x69)
#define REG_HDCP_DUAL_P3_35_L       (REG_HDCP_DUAL_P3_BASE + 0x6A)
#define REG_HDCP_DUAL_P3_35_H       (REG_HDCP_DUAL_P3_BASE + 0x6B)
#define REG_HDCP_DUAL_P3_36_L       (REG_HDCP_DUAL_P3_BASE + 0x6C)
#define REG_HDCP_DUAL_P3_36_H       (REG_HDCP_DUAL_P3_BASE + 0x6D)
#define REG_HDCP_DUAL_P3_37_L       (REG_HDCP_DUAL_P3_BASE + 0x6E)
#define REG_HDCP_DUAL_P3_37_H       (REG_HDCP_DUAL_P3_BASE + 0x6F)
#define REG_HDCP_DUAL_P3_38_L       (REG_HDCP_DUAL_P3_BASE + 0x70)
#define REG_HDCP_DUAL_P3_38_H       (REG_HDCP_DUAL_P3_BASE + 0x71)
#define REG_HDCP_DUAL_P3_39_L       (REG_HDCP_DUAL_P3_BASE + 0x72)
#define REG_HDCP_DUAL_P3_39_H       (REG_HDCP_DUAL_P3_BASE + 0x73)
#define REG_HDCP_DUAL_P3_3A_L       (REG_HDCP_DUAL_P3_BASE + 0x74)
#define REG_HDCP_DUAL_P3_3A_H       (REG_HDCP_DUAL_P3_BASE + 0x75)
#define REG_HDCP_DUAL_P3_3B_L       (REG_HDCP_DUAL_P3_BASE + 0x76)
#define REG_HDCP_DUAL_P3_3B_H       (REG_HDCP_DUAL_P3_BASE + 0x77)
#define REG_HDCP_DUAL_P3_3C_L       (REG_HDCP_DUAL_P3_BASE + 0x78)
#define REG_HDCP_DUAL_P3_3C_H       (REG_HDCP_DUAL_P3_BASE + 0x79)
#define REG_HDCP_DUAL_P3_3D_L       (REG_HDCP_DUAL_P3_BASE + 0x7A)
#define REG_HDCP_DUAL_P3_3D_H       (REG_HDCP_DUAL_P3_BASE + 0x7B)
#define REG_HDCP_DUAL_P3_3E_L       (REG_HDCP_DUAL_P3_BASE + 0x7C)
#define REG_HDCP_DUAL_P3_3E_H       (REG_HDCP_DUAL_P3_BASE + 0x7D)
#define REG_HDCP_DUAL_P3_3F_L       (REG_HDCP_DUAL_P3_BASE + 0x7E)
#define REG_HDCP_DUAL_P3_3F_H       (REG_HDCP_DUAL_P3_BASE + 0x7F)
#define REG_HDCP_DUAL_P3_40_L       (REG_HDCP_DUAL_P3_BASE + 0x80)
#define REG_HDCP_DUAL_P3_40_H       (REG_HDCP_DUAL_P3_BASE + 0x81)
#define REG_HDCP_DUAL_P3_41_L       (REG_HDCP_DUAL_P3_BASE + 0x82)
#define REG_HDCP_DUAL_P3_41_H       (REG_HDCP_DUAL_P3_BASE + 0x83)
#define REG_HDCP_DUAL_P3_42_L       (REG_HDCP_DUAL_P3_BASE + 0x84)
#define REG_HDCP_DUAL_P3_42_H       (REG_HDCP_DUAL_P3_BASE + 0x85)
#define REG_HDCP_DUAL_P3_43_L       (REG_HDCP_DUAL_P3_BASE + 0x86)
#define REG_HDCP_DUAL_P3_43_H       (REG_HDCP_DUAL_P3_BASE + 0x87)
#define REG_HDCP_DUAL_P3_44_L       (REG_HDCP_DUAL_P3_BASE + 0x88)
#define REG_HDCP_DUAL_P3_44_H       (REG_HDCP_DUAL_P3_BASE + 0x89)
#define REG_HDCP_DUAL_P3_45_L       (REG_HDCP_DUAL_P3_BASE + 0x8A)
#define REG_HDCP_DUAL_P3_45_H       (REG_HDCP_DUAL_P3_BASE + 0x8B)
#define REG_HDCP_DUAL_P3_46_L       (REG_HDCP_DUAL_P3_BASE + 0x8C)
#define REG_HDCP_DUAL_P3_46_H       (REG_HDCP_DUAL_P3_BASE + 0x8D)
#define REG_HDCP_DUAL_P3_47_L       (REG_HDCP_DUAL_P3_BASE + 0x8E)
#define REG_HDCP_DUAL_P3_47_H       (REG_HDCP_DUAL_P3_BASE + 0x8F)
#define REG_HDCP_DUAL_P3_48_L       (REG_HDCP_DUAL_P3_BASE + 0x90)
#define REG_HDCP_DUAL_P3_48_H       (REG_HDCP_DUAL_P3_BASE + 0x91)
#define REG_HDCP_DUAL_P3_49_L       (REG_HDCP_DUAL_P3_BASE + 0x92)
#define REG_HDCP_DUAL_P3_49_H       (REG_HDCP_DUAL_P3_BASE + 0x93)
#define REG_HDCP_DUAL_P3_4A_L       (REG_HDCP_DUAL_P3_BASE + 0x94)
#define REG_HDCP_DUAL_P3_4A_H       (REG_HDCP_DUAL_P3_BASE + 0x95)
#define REG_HDCP_DUAL_P3_4B_L       (REG_HDCP_DUAL_P3_BASE + 0x96)
#define REG_HDCP_DUAL_P3_4B_H       (REG_HDCP_DUAL_P3_BASE + 0x97)
#define REG_HDCP_DUAL_P3_4C_L       (REG_HDCP_DUAL_P3_BASE + 0x98)
#define REG_HDCP_DUAL_P3_4C_H       (REG_HDCP_DUAL_P3_BASE + 0x99)
#define REG_HDCP_DUAL_P3_4D_L       (REG_HDCP_DUAL_P3_BASE + 0x9A)
#define REG_HDCP_DUAL_P3_4D_H       (REG_HDCP_DUAL_P3_BASE + 0x9B)
#define REG_HDCP_DUAL_P3_4E_L       (REG_HDCP_DUAL_P3_BASE + 0x9C)
#define REG_HDCP_DUAL_P3_4E_H       (REG_HDCP_DUAL_P3_BASE + 0x9D)
#define REG_HDCP_DUAL_P3_4F_L       (REG_HDCP_DUAL_P3_BASE + 0x9E)
#define REG_HDCP_DUAL_P3_4F_H       (REG_HDCP_DUAL_P3_BASE + 0x9F)
#define REG_HDCP_DUAL_P3_50_L       (REG_HDCP_DUAL_P3_BASE + 0xA0)
#define REG_HDCP_DUAL_P3_50_H       (REG_HDCP_DUAL_P3_BASE + 0xA1)
#define REG_HDCP_DUAL_P3_51_L       (REG_HDCP_DUAL_P3_BASE + 0xA2)
#define REG_HDCP_DUAL_P3_51_H       (REG_HDCP_DUAL_P3_BASE + 0xA3)
#define REG_HDCP_DUAL_P3_52_L       (REG_HDCP_DUAL_P3_BASE + 0xA4)
#define REG_HDCP_DUAL_P3_52_H       (REG_HDCP_DUAL_P3_BASE + 0xA5)
#define REG_HDCP_DUAL_P3_53_L       (REG_HDCP_DUAL_P3_BASE + 0xA6)
#define REG_HDCP_DUAL_P3_53_H       (REG_HDCP_DUAL_P3_BASE + 0xA7)
#define REG_HDCP_DUAL_P3_54_L       (REG_HDCP_DUAL_P3_BASE + 0xA8)
#define REG_HDCP_DUAL_P3_54_H       (REG_HDCP_DUAL_P3_BASE + 0xA9)
#define REG_HDCP_DUAL_P3_55_L       (REG_HDCP_DUAL_P3_BASE + 0xAA)
#define REG_HDCP_DUAL_P3_55_H       (REG_HDCP_DUAL_P3_BASE + 0xAB)
#define REG_HDCP_DUAL_P3_56_L       (REG_HDCP_DUAL_P3_BASE + 0xAC)
#define REG_HDCP_DUAL_P3_56_H       (REG_HDCP_DUAL_P3_BASE + 0xAD)
#define REG_HDCP_DUAL_P3_57_L       (REG_HDCP_DUAL_P3_BASE + 0xAE)
#define REG_HDCP_DUAL_P3_57_H       (REG_HDCP_DUAL_P3_BASE + 0xAF)
#define REG_HDCP_DUAL_P3_58_L       (REG_HDCP_DUAL_P3_BASE + 0xB0)
#define REG_HDCP_DUAL_P3_58_H       (REG_HDCP_DUAL_P3_BASE + 0xB1)
#define REG_HDCP_DUAL_P3_59_L       (REG_HDCP_DUAL_P3_BASE + 0xB2)
#define REG_HDCP_DUAL_P3_59_H       (REG_HDCP_DUAL_P3_BASE + 0xB3)
#define REG_HDCP_DUAL_P3_5A_L       (REG_HDCP_DUAL_P3_BASE + 0xB4)
#define REG_HDCP_DUAL_P3_5A_H       (REG_HDCP_DUAL_P3_BASE + 0xB5)
#define REG_HDCP_DUAL_P3_5B_L       (REG_HDCP_DUAL_P3_BASE + 0xB6)
#define REG_HDCP_DUAL_P3_5B_H       (REG_HDCP_DUAL_P3_BASE + 0xB7)
#define REG_HDCP_DUAL_P3_5C_L       (REG_HDCP_DUAL_P3_BASE + 0xB8)
#define REG_HDCP_DUAL_P3_5C_H       (REG_HDCP_DUAL_P3_BASE + 0xB9)
#define REG_HDCP_DUAL_P3_5D_L       (REG_HDCP_DUAL_P3_BASE + 0xBA)
#define REG_HDCP_DUAL_P3_5D_H       (REG_HDCP_DUAL_P3_BASE + 0xBB)
#define REG_HDCP_DUAL_P3_5E_L       (REG_HDCP_DUAL_P3_BASE + 0xBC)
#define REG_HDCP_DUAL_P3_5E_H       (REG_HDCP_DUAL_P3_BASE + 0xBD)
#define REG_HDCP_DUAL_P3_5F_L       (REG_HDCP_DUAL_P3_BASE + 0xBE)
#define REG_HDCP_DUAL_P3_5F_H       (REG_HDCP_DUAL_P3_BASE + 0xBF)
#define REG_HDCP_DUAL_P3_60_L       (REG_HDCP_DUAL_P3_BASE + 0xC0)
#define REG_HDCP_DUAL_P3_60_H       (REG_HDCP_DUAL_P3_BASE + 0xC1)
#define REG_HDCP_DUAL_P3_61_L       (REG_HDCP_DUAL_P3_BASE + 0xC2)
#define REG_HDCP_DUAL_P3_61_H       (REG_HDCP_DUAL_P3_BASE + 0xC3)
#define REG_HDCP_DUAL_P3_62_L       (REG_HDCP_DUAL_P3_BASE + 0xC4)
#define REG_HDCP_DUAL_P3_62_H       (REG_HDCP_DUAL_P3_BASE + 0xC5)
#define REG_HDCP_DUAL_P3_63_L       (REG_HDCP_DUAL_P3_BASE + 0xC6)
#define REG_HDCP_DUAL_P3_63_H       (REG_HDCP_DUAL_P3_BASE + 0xC7)
#define REG_HDCP_DUAL_P3_64_L       (REG_HDCP_DUAL_P3_BASE + 0xC8)
#define REG_HDCP_DUAL_P3_64_H       (REG_HDCP_DUAL_P3_BASE + 0xC9)
#define REG_HDCP_DUAL_P3_65_L       (REG_HDCP_DUAL_P3_BASE + 0xCA)
#define REG_HDCP_DUAL_P3_65_H       (REG_HDCP_DUAL_P3_BASE + 0xCB)
#define REG_HDCP_DUAL_P3_66_L       (REG_HDCP_DUAL_P3_BASE + 0xCC)
#define REG_HDCP_DUAL_P3_66_H       (REG_HDCP_DUAL_P3_BASE + 0xCD)
#define REG_HDCP_DUAL_P3_67_L       (REG_HDCP_DUAL_P3_BASE + 0xCE)
#define REG_HDCP_DUAL_P3_67_H       (REG_HDCP_DUAL_P3_BASE + 0xCF)
#define REG_HDCP_DUAL_P3_68_L       (REG_HDCP_DUAL_P3_BASE + 0xD0)
#define REG_HDCP_DUAL_P3_68_H       (REG_HDCP_DUAL_P3_BASE + 0xD1)

//=============================================================

// HDMI_DUAL_0
#define REG_HDMI_DUAL_0_00_L       (REG_HDMI_DUAL_0_BASE + 0x00)
#define REG_HDMI_DUAL_0_00_H       (REG_HDMI_DUAL_0_BASE + 0x01)
#define REG_HDMI_DUAL_0_01_L       (REG_HDMI_DUAL_0_BASE + 0x02)
#define REG_HDMI_DUAL_0_01_H       (REG_HDMI_DUAL_0_BASE + 0x03)
#define REG_HDMI_DUAL_0_02_L       (REG_HDMI_DUAL_0_BASE + 0x04)
#define REG_HDMI_DUAL_0_02_H       (REG_HDMI_DUAL_0_BASE + 0x05)
#define REG_HDMI_DUAL_0_03_L       (REG_HDMI_DUAL_0_BASE + 0x06)
#define REG_HDMI_DUAL_0_03_H       (REG_HDMI_DUAL_0_BASE + 0x07)
#define REG_HDMI_DUAL_0_04_L       (REG_HDMI_DUAL_0_BASE + 0x08)
#define REG_HDMI_DUAL_0_04_H       (REG_HDMI_DUAL_0_BASE + 0x09)
#define REG_HDMI_DUAL_0_05_L       (REG_HDMI_DUAL_0_BASE + 0x0A)
#define REG_HDMI_DUAL_0_05_H       (REG_HDMI_DUAL_0_BASE + 0x0B)
#define REG_HDMI_DUAL_0_06_L       (REG_HDMI_DUAL_0_BASE + 0x0C)
#define REG_HDMI_DUAL_0_06_H       (REG_HDMI_DUAL_0_BASE + 0x0D)
#define REG_HDMI_DUAL_0_07_L       (REG_HDMI_DUAL_0_BASE + 0x0E)
#define REG_HDMI_DUAL_0_07_H       (REG_HDMI_DUAL_0_BASE + 0x0F)
#define REG_HDMI_DUAL_0_08_L       (REG_HDMI_DUAL_0_BASE + 0x10)
#define REG_HDMI_DUAL_0_08_H       (REG_HDMI_DUAL_0_BASE + 0x11)
#define REG_HDMI_DUAL_0_09_L       (REG_HDMI_DUAL_0_BASE + 0x12)
#define REG_HDMI_DUAL_0_09_H       (REG_HDMI_DUAL_0_BASE + 0x13)
#define REG_HDMI_DUAL_0_0A_L       (REG_HDMI_DUAL_0_BASE + 0x14)
#define REG_HDMI_DUAL_0_0A_H       (REG_HDMI_DUAL_0_BASE + 0x15)
#define REG_HDMI_DUAL_0_0B_L       (REG_HDMI_DUAL_0_BASE + 0x16)
#define REG_HDMI_DUAL_0_0B_H       (REG_HDMI_DUAL_0_BASE + 0x17)
#define REG_HDMI_DUAL_0_0C_L       (REG_HDMI_DUAL_0_BASE + 0x18)
#define REG_HDMI_DUAL_0_0C_H       (REG_HDMI_DUAL_0_BASE + 0x19)
#define REG_HDMI_DUAL_0_0D_L       (REG_HDMI_DUAL_0_BASE + 0x1A)
#define REG_HDMI_DUAL_0_0D_H       (REG_HDMI_DUAL_0_BASE + 0x1B)
#define REG_HDMI_DUAL_0_0E_L       (REG_HDMI_DUAL_0_BASE + 0x1C)
#define REG_HDMI_DUAL_0_0E_H       (REG_HDMI_DUAL_0_BASE + 0x1D)
#define REG_HDMI_DUAL_0_0F_L       (REG_HDMI_DUAL_0_BASE + 0x1E)
#define REG_HDMI_DUAL_0_0F_H       (REG_HDMI_DUAL_0_BASE + 0x1F)
#define REG_HDMI_DUAL_0_10_L       (REG_HDMI_DUAL_0_BASE + 0x20)
#define REG_HDMI_DUAL_0_10_H       (REG_HDMI_DUAL_0_BASE + 0x21)
#define REG_HDMI_DUAL_0_11_L       (REG_HDMI_DUAL_0_BASE + 0x22)
#define REG_HDMI_DUAL_0_11_H       (REG_HDMI_DUAL_0_BASE + 0x23)
#define REG_HDMI_DUAL_0_12_L       (REG_HDMI_DUAL_0_BASE + 0x24)
#define REG_HDMI_DUAL_0_12_H       (REG_HDMI_DUAL_0_BASE + 0x25)
#define REG_HDMI_DUAL_0_13_L       (REG_HDMI_DUAL_0_BASE + 0x26)
#define REG_HDMI_DUAL_0_13_H       (REG_HDMI_DUAL_0_BASE + 0x27)
#define REG_HDMI_DUAL_0_14_L       (REG_HDMI_DUAL_0_BASE + 0x28)
#define REG_HDMI_DUAL_0_14_H       (REG_HDMI_DUAL_0_BASE + 0x29)
#define REG_HDMI_DUAL_0_15_L       (REG_HDMI_DUAL_0_BASE + 0x2A)
#define REG_HDMI_DUAL_0_15_H       (REG_HDMI_DUAL_0_BASE + 0x2B)
#define REG_HDMI_DUAL_0_16_L       (REG_HDMI_DUAL_0_BASE + 0x2C)
#define REG_HDMI_DUAL_0_16_H       (REG_HDMI_DUAL_0_BASE + 0x2D)
#define REG_HDMI_DUAL_0_17_L       (REG_HDMI_DUAL_0_BASE + 0x2E)
#define REG_HDMI_DUAL_0_17_H       (REG_HDMI_DUAL_0_BASE + 0x2F)
#define REG_HDMI_DUAL_0_18_L       (REG_HDMI_DUAL_0_BASE + 0x30)
#define REG_HDMI_DUAL_0_18_H       (REG_HDMI_DUAL_0_BASE + 0x31)
#define REG_HDMI_DUAL_0_19_L       (REG_HDMI_DUAL_0_BASE + 0x32)
#define REG_HDMI_DUAL_0_19_H       (REG_HDMI_DUAL_0_BASE + 0x33)
#define REG_HDMI_DUAL_0_1A_L       (REG_HDMI_DUAL_0_BASE + 0x34)
#define REG_HDMI_DUAL_0_1A_H       (REG_HDMI_DUAL_0_BASE + 0x35)
#define REG_HDMI_DUAL_0_1B_L       (REG_HDMI_DUAL_0_BASE + 0x36)
#define REG_HDMI_DUAL_0_1B_H       (REG_HDMI_DUAL_0_BASE + 0x37)
#define REG_HDMI_DUAL_0_1C_L       (REG_HDMI_DUAL_0_BASE + 0x38)
#define REG_HDMI_DUAL_0_1C_H       (REG_HDMI_DUAL_0_BASE + 0x39)
#define REG_HDMI_DUAL_0_1D_L       (REG_HDMI_DUAL_0_BASE + 0x3A)
#define REG_HDMI_DUAL_0_1D_H       (REG_HDMI_DUAL_0_BASE + 0x3B)
#define REG_HDMI_DUAL_0_1E_L       (REG_HDMI_DUAL_0_BASE + 0x3C)
#define REG_HDMI_DUAL_0_1E_H       (REG_HDMI_DUAL_0_BASE + 0x3D)
#define REG_HDMI_DUAL_0_1F_L       (REG_HDMI_DUAL_0_BASE + 0x3E)
#define REG_HDMI_DUAL_0_1F_H       (REG_HDMI_DUAL_0_BASE + 0x3F)
#define REG_HDMI_DUAL_0_20_L       (REG_HDMI_DUAL_0_BASE + 0x40)
#define REG_HDMI_DUAL_0_20_H       (REG_HDMI_DUAL_0_BASE + 0x41)
#define REG_HDMI_DUAL_0_21_L       (REG_HDMI_DUAL_0_BASE + 0x42)
#define REG_HDMI_DUAL_0_21_H       (REG_HDMI_DUAL_0_BASE + 0x43)
#define REG_HDMI_DUAL_0_22_L       (REG_HDMI_DUAL_0_BASE + 0x44)
#define REG_HDMI_DUAL_0_22_H       (REG_HDMI_DUAL_0_BASE + 0x45)
#define REG_HDMI_DUAL_0_23_L       (REG_HDMI_DUAL_0_BASE + 0x46)
#define REG_HDMI_DUAL_0_23_H       (REG_HDMI_DUAL_0_BASE + 0x47)
#define REG_HDMI_DUAL_0_24_L       (REG_HDMI_DUAL_0_BASE + 0x48)
#define REG_HDMI_DUAL_0_24_H       (REG_HDMI_DUAL_0_BASE + 0x49)
#define REG_HDMI_DUAL_0_25_L       (REG_HDMI_DUAL_0_BASE + 0x4A)
#define REG_HDMI_DUAL_0_25_H       (REG_HDMI_DUAL_0_BASE + 0x4B)
#define REG_HDMI_DUAL_0_26_L       (REG_HDMI_DUAL_0_BASE + 0x4C)
#define REG_HDMI_DUAL_0_26_H       (REG_HDMI_DUAL_0_BASE + 0x4D)
#define REG_HDMI_DUAL_0_27_L       (REG_HDMI_DUAL_0_BASE + 0x4E)
#define REG_HDMI_DUAL_0_27_H       (REG_HDMI_DUAL_0_BASE + 0x4F)
#define REG_HDMI_DUAL_0_28_L       (REG_HDMI_DUAL_0_BASE + 0x50)
#define REG_HDMI_DUAL_0_28_H       (REG_HDMI_DUAL_0_BASE + 0x51)
#define REG_HDMI_DUAL_0_29_L       (REG_HDMI_DUAL_0_BASE + 0x52)
#define REG_HDMI_DUAL_0_29_H       (REG_HDMI_DUAL_0_BASE + 0x53)
#define REG_HDMI_DUAL_0_2A_L       (REG_HDMI_DUAL_0_BASE + 0x54)
#define REG_HDMI_DUAL_0_2A_H       (REG_HDMI_DUAL_0_BASE + 0x55)
#define REG_HDMI_DUAL_0_2B_L       (REG_HDMI_DUAL_0_BASE + 0x56)
#define REG_HDMI_DUAL_0_2B_H       (REG_HDMI_DUAL_0_BASE + 0x57)
#define REG_HDMI_DUAL_0_2C_L       (REG_HDMI_DUAL_0_BASE + 0x58)
#define REG_HDMI_DUAL_0_2C_H       (REG_HDMI_DUAL_0_BASE + 0x59)
#define REG_HDMI_DUAL_0_2D_L       (REG_HDMI_DUAL_0_BASE + 0x5A)
#define REG_HDMI_DUAL_0_2D_H       (REG_HDMI_DUAL_0_BASE + 0x5B)
#define REG_HDMI_DUAL_0_2E_L       (REG_HDMI_DUAL_0_BASE + 0x5C)
#define REG_HDMI_DUAL_0_2E_H       (REG_HDMI_DUAL_0_BASE + 0x5D)
#define REG_HDMI_DUAL_0_2F_L       (REG_HDMI_DUAL_0_BASE + 0x5E)
#define REG_HDMI_DUAL_0_2F_H       (REG_HDMI_DUAL_0_BASE + 0x5F)
#define REG_HDMI_DUAL_0_30_L       (REG_HDMI_DUAL_0_BASE + 0x60)
#define REG_HDMI_DUAL_0_30_H       (REG_HDMI_DUAL_0_BASE + 0x61)
#define REG_HDMI_DUAL_0_31_L       (REG_HDMI_DUAL_0_BASE + 0x62)
#define REG_HDMI_DUAL_0_31_H       (REG_HDMI_DUAL_0_BASE + 0x63)
#define REG_HDMI_DUAL_0_32_L       (REG_HDMI_DUAL_0_BASE + 0x64)
#define REG_HDMI_DUAL_0_32_H       (REG_HDMI_DUAL_0_BASE + 0x65)
#define REG_HDMI_DUAL_0_33_L       (REG_HDMI_DUAL_0_BASE + 0x66)
#define REG_HDMI_DUAL_0_33_H       (REG_HDMI_DUAL_0_BASE + 0x67)
#define REG_HDMI_DUAL_0_34_L       (REG_HDMI_DUAL_0_BASE + 0x68)
#define REG_HDMI_DUAL_0_34_H       (REG_HDMI_DUAL_0_BASE + 0x69)
#define REG_HDMI_DUAL_0_35_L       (REG_HDMI_DUAL_0_BASE + 0x6A)
#define REG_HDMI_DUAL_0_35_H       (REG_HDMI_DUAL_0_BASE + 0x6B)
#define REG_HDMI_DUAL_0_36_L       (REG_HDMI_DUAL_0_BASE + 0x6C)
#define REG_HDMI_DUAL_0_36_H       (REG_HDMI_DUAL_0_BASE + 0x6D)
#define REG_HDMI_DUAL_0_37_L       (REG_HDMI_DUAL_0_BASE + 0x6E)
#define REG_HDMI_DUAL_0_37_H       (REG_HDMI_DUAL_0_BASE + 0x6F)
#define REG_HDMI_DUAL_0_38_L       (REG_HDMI_DUAL_0_BASE + 0x70)
#define REG_HDMI_DUAL_0_38_H       (REG_HDMI_DUAL_0_BASE + 0x71)
#define REG_HDMI_DUAL_0_39_L       (REG_HDMI_DUAL_0_BASE + 0x72)
#define REG_HDMI_DUAL_0_39_H       (REG_HDMI_DUAL_0_BASE + 0x73)
#define REG_HDMI_DUAL_0_3A_L       (REG_HDMI_DUAL_0_BASE + 0x74)
#define REG_HDMI_DUAL_0_3A_H       (REG_HDMI_DUAL_0_BASE + 0x75)
#define REG_HDMI_DUAL_0_3B_L       (REG_HDMI_DUAL_0_BASE + 0x76)
#define REG_HDMI_DUAL_0_3B_H       (REG_HDMI_DUAL_0_BASE + 0x77)
#define REG_HDMI_DUAL_0_3C_L       (REG_HDMI_DUAL_0_BASE + 0x78)
#define REG_HDMI_DUAL_0_3C_H       (REG_HDMI_DUAL_0_BASE + 0x79)
#define REG_HDMI_DUAL_0_3D_L       (REG_HDMI_DUAL_0_BASE + 0x7A)
#define REG_HDMI_DUAL_0_3D_H       (REG_HDMI_DUAL_0_BASE + 0x7B)
#define REG_HDMI_DUAL_0_3E_L       (REG_HDMI_DUAL_0_BASE + 0x7C)
#define REG_HDMI_DUAL_0_3E_H       (REG_HDMI_DUAL_0_BASE + 0x7D)
#define REG_HDMI_DUAL_0_3F_L       (REG_HDMI_DUAL_0_BASE + 0x7E)
#define REG_HDMI_DUAL_0_3F_H       (REG_HDMI_DUAL_0_BASE + 0x7F)
#define REG_HDMI_DUAL_0_40_L       (REG_HDMI_DUAL_0_BASE + 0x80)
#define REG_HDMI_DUAL_0_40_H       (REG_HDMI_DUAL_0_BASE + 0x81)
#define REG_HDMI_DUAL_0_41_L       (REG_HDMI_DUAL_0_BASE + 0x82)
#define REG_HDMI_DUAL_0_41_H       (REG_HDMI_DUAL_0_BASE + 0x83)
#define REG_HDMI_DUAL_0_42_L       (REG_HDMI_DUAL_0_BASE + 0x84)
#define REG_HDMI_DUAL_0_42_H       (REG_HDMI_DUAL_0_BASE + 0x85)
#define REG_HDMI_DUAL_0_43_L       (REG_HDMI_DUAL_0_BASE + 0x86)
#define REG_HDMI_DUAL_0_43_H       (REG_HDMI_DUAL_0_BASE + 0x87)
#define REG_HDMI_DUAL_0_44_L       (REG_HDMI_DUAL_0_BASE + 0x88)
#define REG_HDMI_DUAL_0_44_H       (REG_HDMI_DUAL_0_BASE + 0x89)
#define REG_HDMI_DUAL_0_45_L       (REG_HDMI_DUAL_0_BASE + 0x8A)
#define REG_HDMI_DUAL_0_45_H       (REG_HDMI_DUAL_0_BASE + 0x8B)
#define REG_HDMI_DUAL_0_46_L       (REG_HDMI_DUAL_0_BASE + 0x8C)
#define REG_HDMI_DUAL_0_46_H       (REG_HDMI_DUAL_0_BASE + 0x8D)
#define REG_HDMI_DUAL_0_47_L       (REG_HDMI_DUAL_0_BASE + 0x8E)
#define REG_HDMI_DUAL_0_47_H       (REG_HDMI_DUAL_0_BASE + 0x8F)
#define REG_HDMI_DUAL_0_48_L       (REG_HDMI_DUAL_0_BASE + 0x90)
#define REG_HDMI_DUAL_0_48_H       (REG_HDMI_DUAL_0_BASE + 0x91)
#define REG_HDMI_DUAL_0_49_L       (REG_HDMI_DUAL_0_BASE + 0x92)
#define REG_HDMI_DUAL_0_49_H       (REG_HDMI_DUAL_0_BASE + 0x93)
#define REG_HDMI_DUAL_0_4A_L       (REG_HDMI_DUAL_0_BASE + 0x94)
#define REG_HDMI_DUAL_0_4A_H       (REG_HDMI_DUAL_0_BASE + 0x95)
#define REG_HDMI_DUAL_0_4B_L       (REG_HDMI_DUAL_0_BASE + 0x96)
#define REG_HDMI_DUAL_0_4B_H       (REG_HDMI_DUAL_0_BASE + 0x97)
#define REG_HDMI_DUAL_0_4C_L       (REG_HDMI_DUAL_0_BASE + 0x98)
#define REG_HDMI_DUAL_0_4C_H       (REG_HDMI_DUAL_0_BASE + 0x99)
#define REG_HDMI_DUAL_0_4D_L       (REG_HDMI_DUAL_0_BASE + 0x9A)
#define REG_HDMI_DUAL_0_4D_H       (REG_HDMI_DUAL_0_BASE + 0x9B)
#define REG_HDMI_DUAL_0_4E_L       (REG_HDMI_DUAL_0_BASE + 0x9C)
#define REG_HDMI_DUAL_0_4E_H       (REG_HDMI_DUAL_0_BASE + 0x9D)
#define REG_HDMI_DUAL_0_4F_L       (REG_HDMI_DUAL_0_BASE + 0x9E)
#define REG_HDMI_DUAL_0_4F_H       (REG_HDMI_DUAL_0_BASE + 0x9F)
#define REG_HDMI_DUAL_0_50_L       (REG_HDMI_DUAL_0_BASE + 0xA0)
#define REG_HDMI_DUAL_0_50_H       (REG_HDMI_DUAL_0_BASE + 0xA1)
#define REG_HDMI_DUAL_0_51_L       (REG_HDMI_DUAL_0_BASE + 0xA2)
#define REG_HDMI_DUAL_0_51_H       (REG_HDMI_DUAL_0_BASE + 0xA3)
#define REG_HDMI_DUAL_0_52_L       (REG_HDMI_DUAL_0_BASE + 0xA4)
#define REG_HDMI_DUAL_0_52_H       (REG_HDMI_DUAL_0_BASE + 0xA5)
#define REG_HDMI_DUAL_0_53_L       (REG_HDMI_DUAL_0_BASE + 0xA6)
#define REG_HDMI_DUAL_0_53_H       (REG_HDMI_DUAL_0_BASE + 0xA7)
#define REG_HDMI_DUAL_0_54_L       (REG_HDMI_DUAL_0_BASE + 0xA8)
#define REG_HDMI_DUAL_0_54_H       (REG_HDMI_DUAL_0_BASE + 0xA9)
#define REG_HDMI_DUAL_0_55_L       (REG_HDMI_DUAL_0_BASE + 0xAA)
#define REG_HDMI_DUAL_0_55_H       (REG_HDMI_DUAL_0_BASE + 0xAB)
#define REG_HDMI_DUAL_0_56_L       (REG_HDMI_DUAL_0_BASE + 0xAC)
#define REG_HDMI_DUAL_0_56_H       (REG_HDMI_DUAL_0_BASE + 0xAD)
#define REG_HDMI_DUAL_0_57_L       (REG_HDMI_DUAL_0_BASE + 0xAE)
#define REG_HDMI_DUAL_0_57_H       (REG_HDMI_DUAL_0_BASE + 0xAF)
#define REG_HDMI_DUAL_0_58_L       (REG_HDMI_DUAL_0_BASE + 0xB0)
#define REG_HDMI_DUAL_0_58_H       (REG_HDMI_DUAL_0_BASE + 0xB1)
#define REG_HDMI_DUAL_0_59_L       (REG_HDMI_DUAL_0_BASE + 0xB2)
#define REG_HDMI_DUAL_0_59_H       (REG_HDMI_DUAL_0_BASE + 0xB3)
#define REG_HDMI_DUAL_0_5A_L       (REG_HDMI_DUAL_0_BASE + 0xB4)
#define REG_HDMI_DUAL_0_5A_H       (REG_HDMI_DUAL_0_BASE + 0xB5)
#define REG_HDMI_DUAL_0_5B_L       (REG_HDMI_DUAL_0_BASE + 0xB6)
#define REG_HDMI_DUAL_0_5B_H       (REG_HDMI_DUAL_0_BASE + 0xB7)
#define REG_HDMI_DUAL_0_5C_L       (REG_HDMI_DUAL_0_BASE + 0xB8)
#define REG_HDMI_DUAL_0_5C_H       (REG_HDMI_DUAL_0_BASE + 0xB9)
#define REG_HDMI_DUAL_0_5D_L       (REG_HDMI_DUAL_0_BASE + 0xBA)
#define REG_HDMI_DUAL_0_5D_H       (REG_HDMI_DUAL_0_BASE + 0xBB)
#define REG_HDMI_DUAL_0_5E_L       (REG_HDMI_DUAL_0_BASE + 0xBC)
#define REG_HDMI_DUAL_0_5E_H       (REG_HDMI_DUAL_0_BASE + 0xBD)
#define REG_HDMI_DUAL_0_5F_L       (REG_HDMI_DUAL_0_BASE + 0xBE)
#define REG_HDMI_DUAL_0_5F_H       (REG_HDMI_DUAL_0_BASE + 0xBF)
#define REG_HDMI_DUAL_0_60_L       (REG_HDMI_DUAL_0_BASE + 0xC0)
#define REG_HDMI_DUAL_0_60_H       (REG_HDMI_DUAL_0_BASE + 0xC1)
#define REG_HDMI_DUAL_0_61_L       (REG_HDMI_DUAL_0_BASE + 0xC2)
#define REG_HDMI_DUAL_0_61_H       (REG_HDMI_DUAL_0_BASE + 0xC3)
#define REG_HDMI_DUAL_0_62_L       (REG_HDMI_DUAL_0_BASE + 0xC4)
#define REG_HDMI_DUAL_0_62_H       (REG_HDMI_DUAL_0_BASE + 0xC5)
#define REG_HDMI_DUAL_0_63_L       (REG_HDMI_DUAL_0_BASE + 0xC6)
#define REG_HDMI_DUAL_0_63_H       (REG_HDMI_DUAL_0_BASE + 0xC7)
#define REG_HDMI_DUAL_0_64_L       (REG_HDMI_DUAL_0_BASE + 0xC8)
#define REG_HDMI_DUAL_0_64_H       (REG_HDMI_DUAL_0_BASE + 0xC9)
#define REG_HDMI_DUAL_0_65_L       (REG_HDMI_DUAL_0_BASE + 0xCA)
#define REG_HDMI_DUAL_0_65_H       (REG_HDMI_DUAL_0_BASE + 0xCB)
#define REG_HDMI_DUAL_0_66_L       (REG_HDMI_DUAL_0_BASE + 0xCC)
#define REG_HDMI_DUAL_0_66_H       (REG_HDMI_DUAL_0_BASE + 0xCD)
#define REG_HDMI_DUAL_0_67_L       (REG_HDMI_DUAL_0_BASE + 0xCE)
#define REG_HDMI_DUAL_0_67_H       (REG_HDMI_DUAL_0_BASE + 0xCF)
#define REG_HDMI_DUAL_0_68_L       (REG_HDMI_DUAL_0_BASE + 0xD0)
#define REG_HDMI_DUAL_0_68_H       (REG_HDMI_DUAL_0_BASE + 0xD1)
#define REG_HDMI_DUAL_0_69_L       (REG_HDMI_DUAL_0_BASE + 0xD2)
#define REG_HDMI_DUAL_0_69_H       (REG_HDMI_DUAL_0_BASE + 0xD3)
#define REG_HDMI_DUAL_0_6A_L       (REG_HDMI_DUAL_0_BASE + 0xD4)
#define REG_HDMI_DUAL_0_6A_H       (REG_HDMI_DUAL_0_BASE + 0xD5)
#define REG_HDMI_DUAL_0_6B_L       (REG_HDMI_DUAL_0_BASE + 0xD6)
#define REG_HDMI_DUAL_0_6B_H       (REG_HDMI_DUAL_0_BASE + 0xD7)
#define REG_HDMI_DUAL_0_6C_L       (REG_HDMI_DUAL_0_BASE + 0xD8)
#define REG_HDMI_DUAL_0_6C_H       (REG_HDMI_DUAL_0_BASE + 0xD9)
#define REG_HDMI_DUAL_0_6D_L       (REG_HDMI_DUAL_0_BASE + 0xDA)
#define REG_HDMI_DUAL_0_6D_H       (REG_HDMI_DUAL_0_BASE + 0xDB)
#define REG_HDMI_DUAL_0_6E_L       (REG_HDMI_DUAL_0_BASE + 0xDC)
#define REG_HDMI_DUAL_0_6E_H       (REG_HDMI_DUAL_0_BASE + 0xDD)
#define REG_HDMI_DUAL_0_6F_L       (REG_HDMI_DUAL_0_BASE + 0xDE)
#define REG_HDMI_DUAL_0_6F_H       (REG_HDMI_DUAL_0_BASE + 0xDF)
#define REG_HDMI_DUAL_0_70_L       (REG_HDMI_DUAL_0_BASE + 0xE0)
#define REG_HDMI_DUAL_0_70_H       (REG_HDMI_DUAL_0_BASE + 0xE1)
#define REG_HDMI_DUAL_0_71_L       (REG_HDMI_DUAL_0_BASE + 0xE2)
#define REG_HDMI_DUAL_0_71_H       (REG_HDMI_DUAL_0_BASE + 0xE3)
#define REG_HDMI_DUAL_0_72_L       (REG_HDMI_DUAL_0_BASE + 0xE4)
#define REG_HDMI_DUAL_0_72_H       (REG_HDMI_DUAL_0_BASE + 0xE5)
#define REG_HDMI_DUAL_0_73_L       (REG_HDMI_DUAL_0_BASE + 0xE6)
#define REG_HDMI_DUAL_0_73_H       (REG_HDMI_DUAL_0_BASE + 0xE7)
#define REG_HDMI_DUAL_0_74_L       (REG_HDMI_DUAL_0_BASE + 0xE8)
#define REG_HDMI_DUAL_0_74_H       (REG_HDMI_DUAL_0_BASE + 0xE9)
#define REG_HDMI_DUAL_0_75_L       (REG_HDMI_DUAL_0_BASE + 0xEA)
#define REG_HDMI_DUAL_0_75_H       (REG_HDMI_DUAL_0_BASE + 0xEB)
#define REG_HDMI_DUAL_0_76_L       (REG_HDMI_DUAL_0_BASE + 0xEC)
#define REG_HDMI_DUAL_0_76_H       (REG_HDMI_DUAL_0_BASE + 0xED)
#define REG_HDMI_DUAL_0_77_L       (REG_HDMI_DUAL_0_BASE + 0xEE)
#define REG_HDMI_DUAL_0_77_H       (REG_HDMI_DUAL_0_BASE + 0xEF)
#define REG_HDMI_DUAL_0_78_L       (REG_HDMI_DUAL_0_BASE + 0xF0)
#define REG_HDMI_DUAL_0_78_H       (REG_HDMI_DUAL_0_BASE + 0xF1)
#define REG_HDMI_DUAL_0_79_L       (REG_HDMI_DUAL_0_BASE + 0xF2)
#define REG_HDMI_DUAL_0_79_H       (REG_HDMI_DUAL_0_BASE + 0xF3)
#define REG_HDMI_DUAL_0_7A_L       (REG_HDMI_DUAL_0_BASE + 0xF4)
#define REG_HDMI_DUAL_0_7A_H       (REG_HDMI_DUAL_0_BASE + 0xF5)
#define REG_HDMI_DUAL_0_7B_L       (REG_HDMI_DUAL_0_BASE + 0xF6)
#define REG_HDMI_DUAL_0_7B_H       (REG_HDMI_DUAL_0_BASE + 0xF7)
#define REG_HDMI_DUAL_0_7C_L       (REG_HDMI_DUAL_0_BASE + 0xF8)
#define REG_HDMI_DUAL_0_7C_H       (REG_HDMI_DUAL_0_BASE + 0xF9)
#define REG_HDMI_DUAL_0_7D_L       (REG_HDMI_DUAL_0_BASE + 0xFA)
#define REG_HDMI_DUAL_0_7D_H       (REG_HDMI_DUAL_0_BASE + 0xFB)
#define REG_HDMI_DUAL_0_7E_L       (REG_HDMI_DUAL_0_BASE + 0xFC)
#define REG_HDMI_DUAL_0_7E_H       (REG_HDMI_DUAL_0_BASE + 0xFD)
#define REG_HDMI_DUAL_0_7F_L       (REG_HDMI_DUAL_0_BASE + 0xFE)
#define REG_HDMI_DUAL_0_7F_H       (REG_HDMI_DUAL_0_BASE + 0xFF)

// HDMI2_DUAL_0
#define REG_HDMI2_DUAL_0_00_L       (REG_HDMI2_DUAL_0_BASE + 0x00)
#define REG_HDMI2_DUAL_0_00_H       (REG_HDMI2_DUAL_0_BASE + 0x01)
#define REG_HDMI2_DUAL_0_01_L       (REG_HDMI2_DUAL_0_BASE + 0x02)
#define REG_HDMI2_DUAL_0_01_H       (REG_HDMI2_DUAL_0_BASE + 0x03)
#define REG_HDMI2_DUAL_0_02_L       (REG_HDMI2_DUAL_0_BASE + 0x04)
#define REG_HDMI2_DUAL_0_02_H       (REG_HDMI2_DUAL_0_BASE + 0x05)
#define REG_HDMI2_DUAL_0_03_L       (REG_HDMI2_DUAL_0_BASE + 0x06)
#define REG_HDMI2_DUAL_0_03_H       (REG_HDMI2_DUAL_0_BASE + 0x07)
#define REG_HDMI2_DUAL_0_04_L       (REG_HDMI2_DUAL_0_BASE + 0x08)
#define REG_HDMI2_DUAL_0_04_H       (REG_HDMI2_DUAL_0_BASE + 0x09)
#define REG_HDMI2_DUAL_0_05_L       (REG_HDMI2_DUAL_0_BASE + 0x0A)
#define REG_HDMI2_DUAL_0_05_H       (REG_HDMI2_DUAL_0_BASE + 0x0B)
#define REG_HDMI2_DUAL_0_06_L       (REG_HDMI2_DUAL_0_BASE + 0x0C)
#define REG_HDMI2_DUAL_0_06_H       (REG_HDMI2_DUAL_0_BASE + 0x0D)
#define REG_HDMI2_DUAL_0_07_L       (REG_HDMI2_DUAL_0_BASE + 0x0E)
#define REG_HDMI2_DUAL_0_07_H       (REG_HDMI2_DUAL_0_BASE + 0x0F)
#define REG_HDMI2_DUAL_0_08_L       (REG_HDMI2_DUAL_0_BASE + 0x10)
#define REG_HDMI2_DUAL_0_08_H       (REG_HDMI2_DUAL_0_BASE + 0x11)
#define REG_HDMI2_DUAL_0_09_L       (REG_HDMI2_DUAL_0_BASE + 0x12)
#define REG_HDMI2_DUAL_0_09_H       (REG_HDMI2_DUAL_0_BASE + 0x13)
#define REG_HDMI2_DUAL_0_0A_L       (REG_HDMI2_DUAL_0_BASE + 0x14)
#define REG_HDMI2_DUAL_0_0A_H       (REG_HDMI2_DUAL_0_BASE + 0x15)
#define REG_HDMI2_DUAL_0_0B_L       (REG_HDMI2_DUAL_0_BASE + 0x16)
#define REG_HDMI2_DUAL_0_0B_H       (REG_HDMI2_DUAL_0_BASE + 0x17)
#define REG_HDMI2_DUAL_0_0C_L       (REG_HDMI2_DUAL_0_BASE + 0x18)
#define REG_HDMI2_DUAL_0_0C_H       (REG_HDMI2_DUAL_0_BASE + 0x19)
#define REG_HDMI2_DUAL_0_0D_L       (REG_HDMI2_DUAL_0_BASE + 0x1A)
#define REG_HDMI2_DUAL_0_0D_H       (REG_HDMI2_DUAL_0_BASE + 0x1B)
#define REG_HDMI2_DUAL_0_0E_L       (REG_HDMI2_DUAL_0_BASE + 0x1C)
#define REG_HDMI2_DUAL_0_0E_H       (REG_HDMI2_DUAL_0_BASE + 0x1D)
#define REG_HDMI2_DUAL_0_0F_L       (REG_HDMI2_DUAL_0_BASE + 0x1E)
#define REG_HDMI2_DUAL_0_0F_H       (REG_HDMI2_DUAL_0_BASE + 0x1F)
#define REG_HDMI2_DUAL_0_10_L       (REG_HDMI2_DUAL_0_BASE + 0x20)
#define REG_HDMI2_DUAL_0_10_H       (REG_HDMI2_DUAL_0_BASE + 0x21)
#define REG_HDMI2_DUAL_0_11_L       (REG_HDMI2_DUAL_0_BASE + 0x22)
#define REG_HDMI2_DUAL_0_11_H       (REG_HDMI2_DUAL_0_BASE + 0x23)
#define REG_HDMI2_DUAL_0_12_L       (REG_HDMI2_DUAL_0_BASE + 0x24)
#define REG_HDMI2_DUAL_0_12_H       (REG_HDMI2_DUAL_0_BASE + 0x25)
#define REG_HDMI2_DUAL_0_13_L       (REG_HDMI2_DUAL_0_BASE + 0x26)
#define REG_HDMI2_DUAL_0_13_H       (REG_HDMI2_DUAL_0_BASE + 0x27)
#define REG_HDMI2_DUAL_0_14_L       (REG_HDMI2_DUAL_0_BASE + 0x28)
#define REG_HDMI2_DUAL_0_14_H       (REG_HDMI2_DUAL_0_BASE + 0x29)
#define REG_HDMI2_DUAL_0_15_L       (REG_HDMI2_DUAL_0_BASE + 0x2A)
#define REG_HDMI2_DUAL_0_15_H       (REG_HDMI2_DUAL_0_BASE + 0x2B)
#define REG_HDMI2_DUAL_0_16_L       (REG_HDMI2_DUAL_0_BASE + 0x2C)
#define REG_HDMI2_DUAL_0_16_H       (REG_HDMI2_DUAL_0_BASE + 0x2D)
#define REG_HDMI2_DUAL_0_17_L       (REG_HDMI2_DUAL_0_BASE + 0x2E)
#define REG_HDMI2_DUAL_0_17_H       (REG_HDMI2_DUAL_0_BASE + 0x2F)
#define REG_HDMI2_DUAL_0_18_L       (REG_HDMI2_DUAL_0_BASE + 0x30)
#define REG_HDMI2_DUAL_0_18_H       (REG_HDMI2_DUAL_0_BASE + 0x31)
#define REG_HDMI2_DUAL_0_19_L       (REG_HDMI2_DUAL_0_BASE + 0x32)
#define REG_HDMI2_DUAL_0_19_H       (REG_HDMI2_DUAL_0_BASE + 0x33)
#define REG_HDMI2_DUAL_0_1A_L       (REG_HDMI2_DUAL_0_BASE + 0x34)
#define REG_HDMI2_DUAL_0_1A_H       (REG_HDMI2_DUAL_0_BASE + 0x35)
#define REG_HDMI2_DUAL_0_1B_L       (REG_HDMI2_DUAL_0_BASE + 0x36)
#define REG_HDMI2_DUAL_0_1B_H       (REG_HDMI2_DUAL_0_BASE + 0x37)
#define REG_HDMI2_DUAL_0_1C_L       (REG_HDMI2_DUAL_0_BASE + 0x38)
#define REG_HDMI2_DUAL_0_1C_H       (REG_HDMI2_DUAL_0_BASE + 0x39)
#define REG_HDMI2_DUAL_0_1D_L       (REG_HDMI2_DUAL_0_BASE + 0x3A)
#define REG_HDMI2_DUAL_0_1D_H       (REG_HDMI2_DUAL_0_BASE + 0x3B)
#define REG_HDMI2_DUAL_0_1E_L       (REG_HDMI2_DUAL_0_BASE + 0x3C)
#define REG_HDMI2_DUAL_0_1E_H       (REG_HDMI2_DUAL_0_BASE + 0x3D)
#define REG_HDMI2_DUAL_0_1F_L       (REG_HDMI2_DUAL_0_BASE + 0x3E)
#define REG_HDMI2_DUAL_0_1F_H       (REG_HDMI2_DUAL_0_BASE + 0x3F)
#define REG_HDMI2_DUAL_0_20_L       (REG_HDMI2_DUAL_0_BASE + 0x40)
#define REG_HDMI2_DUAL_0_20_H       (REG_HDMI2_DUAL_0_BASE + 0x41)
#define REG_HDMI2_DUAL_0_21_L       (REG_HDMI2_DUAL_0_BASE + 0x42)
#define REG_HDMI2_DUAL_0_21_H       (REG_HDMI2_DUAL_0_BASE + 0x43)
#define REG_HDMI2_DUAL_0_22_L       (REG_HDMI2_DUAL_0_BASE + 0x44)
#define REG_HDMI2_DUAL_0_22_H       (REG_HDMI2_DUAL_0_BASE + 0x45)
#define REG_HDMI2_DUAL_0_23_L       (REG_HDMI2_DUAL_0_BASE + 0x46)
#define REG_HDMI2_DUAL_0_23_H       (REG_HDMI2_DUAL_0_BASE + 0x47)
#define REG_HDMI2_DUAL_0_24_L       (REG_HDMI2_DUAL_0_BASE + 0x48)
#define REG_HDMI2_DUAL_0_24_H       (REG_HDMI2_DUAL_0_BASE + 0x49)
#define REG_HDMI2_DUAL_0_25_L       (REG_HDMI2_DUAL_0_BASE + 0x4A)
#define REG_HDMI2_DUAL_0_25_H       (REG_HDMI2_DUAL_0_BASE + 0x4B)
#define REG_HDMI2_DUAL_0_26_L       (REG_HDMI2_DUAL_0_BASE + 0x4C)
#define REG_HDMI2_DUAL_0_26_H       (REG_HDMI2_DUAL_0_BASE + 0x4D)
#define REG_HDMI2_DUAL_0_27_L       (REG_HDMI2_DUAL_0_BASE + 0x4E)
#define REG_HDMI2_DUAL_0_27_H       (REG_HDMI2_DUAL_0_BASE + 0x4F)
#define REG_HDMI2_DUAL_0_28_L       (REG_HDMI2_DUAL_0_BASE + 0x50)
#define REG_HDMI2_DUAL_0_28_H       (REG_HDMI2_DUAL_0_BASE + 0x51)
#define REG_HDMI2_DUAL_0_29_L       (REG_HDMI2_DUAL_0_BASE + 0x52)
#define REG_HDMI2_DUAL_0_29_H       (REG_HDMI2_DUAL_0_BASE + 0x53)
#define REG_HDMI2_DUAL_0_2A_L       (REG_HDMI2_DUAL_0_BASE + 0x54)
#define REG_HDMI2_DUAL_0_2A_H       (REG_HDMI2_DUAL_0_BASE + 0x55)
#define REG_HDMI2_DUAL_0_2B_L       (REG_HDMI2_DUAL_0_BASE + 0x56)
#define REG_HDMI2_DUAL_0_2B_H       (REG_HDMI2_DUAL_0_BASE + 0x57)
#define REG_HDMI2_DUAL_0_2C_L       (REG_HDMI2_DUAL_0_BASE + 0x58)
#define REG_HDMI2_DUAL_0_2C_H       (REG_HDMI2_DUAL_0_BASE + 0x59)
#define REG_HDMI2_DUAL_0_2D_L       (REG_HDMI2_DUAL_0_BASE + 0x5A)
#define REG_HDMI2_DUAL_0_2D_H       (REG_HDMI2_DUAL_0_BASE + 0x5B)
#define REG_HDMI2_DUAL_0_2E_L       (REG_HDMI2_DUAL_0_BASE + 0x5C)
#define REG_HDMI2_DUAL_0_2E_H       (REG_HDMI2_DUAL_0_BASE + 0x5D)
#define REG_HDMI2_DUAL_0_2F_L       (REG_HDMI2_DUAL_0_BASE + 0x5E)
#define REG_HDMI2_DUAL_0_2F_H       (REG_HDMI2_DUAL_0_BASE + 0x5F)
#define REG_HDMI2_DUAL_0_30_L       (REG_HDMI2_DUAL_0_BASE + 0x60)
#define REG_HDMI2_DUAL_0_30_H       (REG_HDMI2_DUAL_0_BASE + 0x61)
#define REG_HDMI2_DUAL_0_31_L       (REG_HDMI2_DUAL_0_BASE + 0x62)
#define REG_HDMI2_DUAL_0_31_H       (REG_HDMI2_DUAL_0_BASE + 0x63)
#define REG_HDMI2_DUAL_0_32_L       (REG_HDMI2_DUAL_0_BASE + 0x64)
#define REG_HDMI2_DUAL_0_32_H       (REG_HDMI2_DUAL_0_BASE + 0x65)
#define REG_HDMI2_DUAL_0_33_L       (REG_HDMI2_DUAL_0_BASE + 0x66)
#define REG_HDMI2_DUAL_0_33_H       (REG_HDMI2_DUAL_0_BASE + 0x67)
#define REG_HDMI2_DUAL_0_34_L       (REG_HDMI2_DUAL_0_BASE + 0x68)
#define REG_HDMI2_DUAL_0_34_H       (REG_HDMI2_DUAL_0_BASE + 0x69)
#define REG_HDMI2_DUAL_0_35_L       (REG_HDMI2_DUAL_0_BASE + 0x6A)
#define REG_HDMI2_DUAL_0_35_H       (REG_HDMI2_DUAL_0_BASE + 0x6B)
#define REG_HDMI2_DUAL_0_36_L       (REG_HDMI2_DUAL_0_BASE + 0x6C)
#define REG_HDMI2_DUAL_0_36_H       (REG_HDMI2_DUAL_0_BASE + 0x6D)
#define REG_HDMI2_DUAL_0_37_L       (REG_HDMI2_DUAL_0_BASE + 0x6E)
#define REG_HDMI2_DUAL_0_37_H       (REG_HDMI2_DUAL_0_BASE + 0x6F)
#define REG_HDMI2_DUAL_0_38_L       (REG_HDMI2_DUAL_0_BASE + 0x70)
#define REG_HDMI2_DUAL_0_38_H       (REG_HDMI2_DUAL_0_BASE + 0x71)
#define REG_HDMI2_DUAL_0_39_L       (REG_HDMI2_DUAL_0_BASE + 0x72)
#define REG_HDMI2_DUAL_0_39_H       (REG_HDMI2_DUAL_0_BASE + 0x73)
#define REG_HDMI2_DUAL_0_3A_L       (REG_HDMI2_DUAL_0_BASE + 0x74)
#define REG_HDMI2_DUAL_0_3A_H       (REG_HDMI2_DUAL_0_BASE + 0x75)
#define REG_HDMI2_DUAL_0_3B_L       (REG_HDMI2_DUAL_0_BASE + 0x76)
#define REG_HDMI2_DUAL_0_3B_H       (REG_HDMI2_DUAL_0_BASE + 0x77)
#define REG_HDMI2_DUAL_0_3C_L       (REG_HDMI2_DUAL_0_BASE + 0x78)
#define REG_HDMI2_DUAL_0_3C_H       (REG_HDMI2_DUAL_0_BASE + 0x79)
#define REG_HDMI2_DUAL_0_3D_L       (REG_HDMI2_DUAL_0_BASE + 0x7A)
#define REG_HDMI2_DUAL_0_3D_H       (REG_HDMI2_DUAL_0_BASE + 0x7B)
#define REG_HDMI2_DUAL_0_3E_L       (REG_HDMI2_DUAL_0_BASE + 0x7C)
#define REG_HDMI2_DUAL_0_3E_H       (REG_HDMI2_DUAL_0_BASE + 0x7D)
#define REG_HDMI2_DUAL_0_3F_L       (REG_HDMI2_DUAL_0_BASE + 0x7E)
#define REG_HDMI2_DUAL_0_3F_H       (REG_HDMI2_DUAL_0_BASE + 0x7F)
#define REG_HDMI2_DUAL_0_40_L       (REG_HDMI2_DUAL_0_BASE + 0x80)
#define REG_HDMI2_DUAL_0_40_H       (REG_HDMI2_DUAL_0_BASE + 0x81)
#define REG_HDMI2_DUAL_0_41_L       (REG_HDMI2_DUAL_0_BASE + 0x82)
#define REG_HDMI2_DUAL_0_41_H       (REG_HDMI2_DUAL_0_BASE + 0x83)
#define REG_HDMI2_DUAL_0_42_L       (REG_HDMI2_DUAL_0_BASE + 0x84)
#define REG_HDMI2_DUAL_0_42_H       (REG_HDMI2_DUAL_0_BASE + 0x85)
#define REG_HDMI2_DUAL_0_43_L       (REG_HDMI2_DUAL_0_BASE + 0x86)
#define REG_HDMI2_DUAL_0_43_H       (REG_HDMI2_DUAL_0_BASE + 0x87)
#define REG_HDMI2_DUAL_0_44_L       (REG_HDMI2_DUAL_0_BASE + 0x88)
#define REG_HDMI2_DUAL_0_44_H       (REG_HDMI2_DUAL_0_BASE + 0x89)
#define REG_HDMI2_DUAL_0_45_L       (REG_HDMI2_DUAL_0_BASE + 0x8A)
#define REG_HDMI2_DUAL_0_45_H       (REG_HDMI2_DUAL_0_BASE + 0x8B)
#define REG_HDMI2_DUAL_0_46_L       (REG_HDMI2_DUAL_0_BASE + 0x8C)
#define REG_HDMI2_DUAL_0_46_H       (REG_HDMI2_DUAL_0_BASE + 0x8D)
#define REG_HDMI2_DUAL_0_47_L       (REG_HDMI2_DUAL_0_BASE + 0x8E)
#define REG_HDMI2_DUAL_0_47_H       (REG_HDMI2_DUAL_0_BASE + 0x8F)
#define REG_HDMI2_DUAL_0_48_L       (REG_HDMI2_DUAL_0_BASE + 0x90)
#define REG_HDMI2_DUAL_0_48_H       (REG_HDMI2_DUAL_0_BASE + 0x91)
#define REG_HDMI2_DUAL_0_49_L       (REG_HDMI2_DUAL_0_BASE + 0x92)
#define REG_HDMI2_DUAL_0_49_H       (REG_HDMI2_DUAL_0_BASE + 0x93)
#define REG_HDMI2_DUAL_0_4A_L       (REG_HDMI2_DUAL_0_BASE + 0x94)
#define REG_HDMI2_DUAL_0_4A_H       (REG_HDMI2_DUAL_0_BASE + 0x95)
#define REG_HDMI2_DUAL_0_4B_L       (REG_HDMI2_DUAL_0_BASE + 0x96)
#define REG_HDMI2_DUAL_0_4B_H       (REG_HDMI2_DUAL_0_BASE + 0x97)
#define REG_HDMI2_DUAL_0_4C_L       (REG_HDMI2_DUAL_0_BASE + 0x98)
#define REG_HDMI2_DUAL_0_4C_H       (REG_HDMI2_DUAL_0_BASE + 0x99)
#define REG_HDMI2_DUAL_0_4D_L       (REG_HDMI2_DUAL_0_BASE + 0x9A)
#define REG_HDMI2_DUAL_0_4D_H       (REG_HDMI2_DUAL_0_BASE + 0x9B)
#define REG_HDMI2_DUAL_0_4E_L       (REG_HDMI2_DUAL_0_BASE + 0x9C)
#define REG_HDMI2_DUAL_0_4E_H       (REG_HDMI2_DUAL_0_BASE + 0x9D)
#define REG_HDMI2_DUAL_0_4F_L       (REG_HDMI2_DUAL_0_BASE + 0x9E)
#define REG_HDMI2_DUAL_0_4F_H       (REG_HDMI2_DUAL_0_BASE + 0x9F)
#define REG_HDMI2_DUAL_0_50_L       (REG_HDMI2_DUAL_0_BASE + 0xA0)
#define REG_HDMI2_DUAL_0_50_H       (REG_HDMI2_DUAL_0_BASE + 0xA1)
#define REG_HDMI2_DUAL_0_51_L       (REG_HDMI2_DUAL_0_BASE + 0xA2)
#define REG_HDMI2_DUAL_0_51_H       (REG_HDMI2_DUAL_0_BASE + 0xA3)
#define REG_HDMI2_DUAL_0_52_L       (REG_HDMI2_DUAL_0_BASE + 0xA4)
#define REG_HDMI2_DUAL_0_52_H       (REG_HDMI2_DUAL_0_BASE + 0xA5)
#define REG_HDMI2_DUAL_0_53_L       (REG_HDMI2_DUAL_0_BASE + 0xA6)
#define REG_HDMI2_DUAL_0_53_H       (REG_HDMI2_DUAL_0_BASE + 0xA7)
#define REG_HDMI2_DUAL_0_54_L       (REG_HDMI2_DUAL_0_BASE + 0xA8)
#define REG_HDMI2_DUAL_0_54_H       (REG_HDMI2_DUAL_0_BASE + 0xA9)
#define REG_HDMI2_DUAL_0_55_L       (REG_HDMI2_DUAL_0_BASE + 0xAA)
#define REG_HDMI2_DUAL_0_55_H       (REG_HDMI2_DUAL_0_BASE + 0xAB)
#define REG_HDMI2_DUAL_0_56_L       (REG_HDMI2_DUAL_0_BASE + 0xAC)
#define REG_HDMI2_DUAL_0_56_H       (REG_HDMI2_DUAL_0_BASE + 0xAD)
#define REG_HDMI2_DUAL_0_57_L       (REG_HDMI2_DUAL_0_BASE + 0xAE)
#define REG_HDMI2_DUAL_0_57_H       (REG_HDMI2_DUAL_0_BASE + 0xAF)
#define REG_HDMI2_DUAL_0_58_L       (REG_HDMI2_DUAL_0_BASE + 0xB0)
#define REG_HDMI2_DUAL_0_58_H       (REG_HDMI2_DUAL_0_BASE + 0xB1)
#define REG_HDMI2_DUAL_0_59_L       (REG_HDMI2_DUAL_0_BASE + 0xB2)
#define REG_HDMI2_DUAL_0_59_H       (REG_HDMI2_DUAL_0_BASE + 0xB3)
#define REG_HDMI2_DUAL_0_5A_L       (REG_HDMI2_DUAL_0_BASE + 0xB4)
#define REG_HDMI2_DUAL_0_5A_H       (REG_HDMI2_DUAL_0_BASE + 0xB5)
#define REG_HDMI2_DUAL_0_5B_L       (REG_HDMI2_DUAL_0_BASE + 0xB6)
#define REG_HDMI2_DUAL_0_5B_H       (REG_HDMI2_DUAL_0_BASE + 0xB7)
#define REG_HDMI2_DUAL_0_5C_L       (REG_HDMI2_DUAL_0_BASE + 0xB8)
#define REG_HDMI2_DUAL_0_5C_H       (REG_HDMI2_DUAL_0_BASE + 0xB9)
#define REG_HDMI2_DUAL_0_5D_L       (REG_HDMI2_DUAL_0_BASE + 0xBA)
#define REG_HDMI2_DUAL_0_5D_H       (REG_HDMI2_DUAL_0_BASE + 0xBB)
#define REG_HDMI2_DUAL_0_5E_L       (REG_HDMI2_DUAL_0_BASE + 0xBC)
#define REG_HDMI2_DUAL_0_5E_H       (REG_HDMI2_DUAL_0_BASE + 0xBD)
#define REG_HDMI2_DUAL_0_5F_L       (REG_HDMI2_DUAL_0_BASE + 0xBE)
#define REG_HDMI2_DUAL_0_5F_H       (REG_HDMI2_DUAL_0_BASE + 0xBF)
#define REG_HDMI2_DUAL_0_60_L       (REG_HDMI2_DUAL_0_BASE + 0xC0)
#define REG_HDMI2_DUAL_0_60_H       (REG_HDMI2_DUAL_0_BASE + 0xC1)
#define REG_HDMI2_DUAL_0_61_L       (REG_HDMI2_DUAL_0_BASE + 0xC2)
#define REG_HDMI2_DUAL_0_61_H       (REG_HDMI2_DUAL_0_BASE + 0xC3)
#define REG_HDMI2_DUAL_0_62_L       (REG_HDMI2_DUAL_0_BASE + 0xC4)
#define REG_HDMI2_DUAL_0_62_H       (REG_HDMI2_DUAL_0_BASE + 0xC5)
#define REG_HDMI2_DUAL_0_63_L       (REG_HDMI2_DUAL_0_BASE + 0xC6)
#define REG_HDMI2_DUAL_0_63_H       (REG_HDMI2_DUAL_0_BASE + 0xC7)
#define REG_HDMI2_DUAL_0_64_L       (REG_HDMI2_DUAL_0_BASE + 0xC8)
#define REG_HDMI2_DUAL_0_64_H       (REG_HDMI2_DUAL_0_BASE + 0xC9)
#define REG_HDMI2_DUAL_0_65_L       (REG_HDMI2_DUAL_0_BASE + 0xCA)
#define REG_HDMI2_DUAL_0_65_H       (REG_HDMI2_DUAL_0_BASE + 0xCB)
#define REG_HDMI2_DUAL_0_66_L       (REG_HDMI2_DUAL_0_BASE + 0xCC)
#define REG_HDMI2_DUAL_0_66_H       (REG_HDMI2_DUAL_0_BASE + 0xCD)
#define REG_HDMI2_DUAL_0_67_L       (REG_HDMI2_DUAL_0_BASE + 0xCE)
#define REG_HDMI2_DUAL_0_67_H       (REG_HDMI2_DUAL_0_BASE + 0xCF)
#define REG_HDMI2_DUAL_0_68_L       (REG_HDMI2_DUAL_0_BASE + 0xD0)
#define REG_HDMI2_DUAL_0_68_H       (REG_HDMI2_DUAL_0_BASE + 0xD1)
#define REG_HDMI2_DUAL_0_69_L       (REG_HDMI2_DUAL_0_BASE + 0xD2)
#define REG_HDMI2_DUAL_0_69_H       (REG_HDMI2_DUAL_0_BASE + 0xD3)
#define REG_HDMI2_DUAL_0_6A_L       (REG_HDMI2_DUAL_0_BASE + 0xD4)
#define REG_HDMI2_DUAL_0_6A_H       (REG_HDMI2_DUAL_0_BASE + 0xD5)
#define REG_HDMI2_DUAL_0_6B_L       (REG_HDMI2_DUAL_0_BASE + 0xD6)
#define REG_HDMI2_DUAL_0_6B_H       (REG_HDMI2_DUAL_0_BASE + 0xD7)
#define REG_HDMI2_DUAL_0_6C_L       (REG_HDMI2_DUAL_0_BASE + 0xD8)
#define REG_HDMI2_DUAL_0_6C_H       (REG_HDMI2_DUAL_0_BASE + 0xD9)
#define REG_HDMI2_DUAL_0_6D_L       (REG_HDMI2_DUAL_0_BASE + 0xDA)
#define REG_HDMI2_DUAL_0_6D_H       (REG_HDMI2_DUAL_0_BASE + 0xDB)
#define REG_HDMI2_DUAL_0_6E_L       (REG_HDMI2_DUAL_0_BASE + 0xDC)
#define REG_HDMI2_DUAL_0_6E_H       (REG_HDMI2_DUAL_0_BASE + 0xDD)
#define REG_HDMI2_DUAL_0_6F_L       (REG_HDMI2_DUAL_0_BASE + 0xDE)
#define REG_HDMI2_DUAL_0_6F_H       (REG_HDMI2_DUAL_0_BASE + 0xDF)
#define REG_HDMI2_DUAL_0_70_L       (REG_HDMI2_DUAL_0_BASE + 0xE0)
#define REG_HDMI2_DUAL_0_70_H       (REG_HDMI2_DUAL_0_BASE + 0xE1)
#define REG_HDMI2_DUAL_0_71_L       (REG_HDMI2_DUAL_0_BASE + 0xE2)
#define REG_HDMI2_DUAL_0_71_H       (REG_HDMI2_DUAL_0_BASE + 0xE3)
#define REG_HDMI2_DUAL_0_72_L       (REG_HDMI2_DUAL_0_BASE + 0xE4)
#define REG_HDMI2_DUAL_0_72_H       (REG_HDMI2_DUAL_0_BASE + 0xE5)
#define REG_HDMI2_DUAL_0_73_L       (REG_HDMI2_DUAL_0_BASE + 0xE6)
#define REG_HDMI2_DUAL_0_73_H       (REG_HDMI2_DUAL_0_BASE + 0xE7)
#define REG_HDMI2_DUAL_0_74_L       (REG_HDMI2_DUAL_0_BASE + 0xE8)
#define REG_HDMI2_DUAL_0_74_H       (REG_HDMI2_DUAL_0_BASE + 0xE9)
#define REG_HDMI2_DUAL_0_75_L       (REG_HDMI2_DUAL_0_BASE + 0xEA)
#define REG_HDMI2_DUAL_0_75_H       (REG_HDMI2_DUAL_0_BASE + 0xEB)
#define REG_HDMI2_DUAL_0_76_L       (REG_HDMI2_DUAL_0_BASE + 0xEC)
#define REG_HDMI2_DUAL_0_76_H       (REG_HDMI2_DUAL_0_BASE + 0xED)
#define REG_HDMI2_DUAL_0_77_L       (REG_HDMI2_DUAL_0_BASE + 0xEE)
#define REG_HDMI2_DUAL_0_77_H       (REG_HDMI2_DUAL_0_BASE + 0xEF)
#define REG_HDMI2_DUAL_0_78_L       (REG_HDMI2_DUAL_0_BASE + 0xF0)
#define REG_HDMI2_DUAL_0_78_H       (REG_HDMI2_DUAL_0_BASE + 0xF1)
#define REG_HDMI2_DUAL_0_79_L       (REG_HDMI2_DUAL_0_BASE + 0xF2)
#define REG_HDMI2_DUAL_0_79_H       (REG_HDMI2_DUAL_0_BASE + 0xF3)
#define REG_HDMI2_DUAL_0_7A_L       (REG_HDMI2_DUAL_0_BASE + 0xF4)
#define REG_HDMI2_DUAL_0_7A_H       (REG_HDMI2_DUAL_0_BASE + 0xF5)
#define REG_HDMI2_DUAL_0_7B_L       (REG_HDMI2_DUAL_0_BASE + 0xF6)
#define REG_HDMI2_DUAL_0_7B_H       (REG_HDMI2_DUAL_0_BASE + 0xF7)
#define REG_HDMI2_DUAL_0_7C_L       (REG_HDMI2_DUAL_0_BASE + 0xF8)
#define REG_HDMI2_DUAL_0_7C_H       (REG_HDMI2_DUAL_0_BASE + 0xF9)
#define REG_HDMI2_DUAL_0_7D_L       (REG_HDMI2_DUAL_0_BASE + 0xFA)
#define REG_HDMI2_DUAL_0_7D_H       (REG_HDMI2_DUAL_0_BASE + 0xFB)
#define REG_HDMI2_DUAL_0_7E_L       (REG_HDMI2_DUAL_0_BASE + 0xFC)
#define REG_HDMI2_DUAL_0_7E_H       (REG_HDMI2_DUAL_0_BASE + 0xFD)
#define REG_HDMI2_DUAL_0_7F_L       (REG_HDMI2_DUAL_0_BASE + 0xFE)
#define REG_HDMI2_DUAL_0_7F_H       (REG_HDMI2_DUAL_0_BASE + 0xFF)

// HDMI3_DUAL_0
#define REG_HDMI3_DUAL_0_00_L       (REG_HDMI3_DUAL_0_BASE + 0x00)
#define REG_HDMI3_DUAL_0_00_H       (REG_HDMI3_DUAL_0_BASE + 0x01)
#define REG_HDMI3_DUAL_0_01_L       (REG_HDMI3_DUAL_0_BASE + 0x02)
#define REG_HDMI3_DUAL_0_01_H       (REG_HDMI3_DUAL_0_BASE + 0x03)
#define REG_HDMI3_DUAL_0_02_L       (REG_HDMI3_DUAL_0_BASE + 0x04)
#define REG_HDMI3_DUAL_0_02_H       (REG_HDMI3_DUAL_0_BASE + 0x05)
#define REG_HDMI3_DUAL_0_03_L       (REG_HDMI3_DUAL_0_BASE + 0x06)
#define REG_HDMI3_DUAL_0_03_H       (REG_HDMI3_DUAL_0_BASE + 0x07)
#define REG_HDMI3_DUAL_0_04_L       (REG_HDMI3_DUAL_0_BASE + 0x08)
#define REG_HDMI3_DUAL_0_04_H       (REG_HDMI3_DUAL_0_BASE + 0x09)
#define REG_HDMI3_DUAL_0_05_L       (REG_HDMI3_DUAL_0_BASE + 0x0A)
#define REG_HDMI3_DUAL_0_05_H       (REG_HDMI3_DUAL_0_BASE + 0x0B)
#define REG_HDMI3_DUAL_0_06_L       (REG_HDMI3_DUAL_0_BASE + 0x0C)
#define REG_HDMI3_DUAL_0_06_H       (REG_HDMI3_DUAL_0_BASE + 0x0D)
#define REG_HDMI3_DUAL_0_07_L       (REG_HDMI3_DUAL_0_BASE + 0x0E)
#define REG_HDMI3_DUAL_0_07_H       (REG_HDMI3_DUAL_0_BASE + 0x0F)
#define REG_HDMI3_DUAL_0_08_L       (REG_HDMI3_DUAL_0_BASE + 0x10)
#define REG_HDMI3_DUAL_0_08_H       (REG_HDMI3_DUAL_0_BASE + 0x11)
#define REG_HDMI3_DUAL_0_09_L       (REG_HDMI3_DUAL_0_BASE + 0x12)
#define REG_HDMI3_DUAL_0_09_H       (REG_HDMI3_DUAL_0_BASE + 0x13)
#define REG_HDMI3_DUAL_0_0A_L       (REG_HDMI3_DUAL_0_BASE + 0x14)
#define REG_HDMI3_DUAL_0_0A_H       (REG_HDMI3_DUAL_0_BASE + 0x15)
#define REG_HDMI3_DUAL_0_0B_L       (REG_HDMI3_DUAL_0_BASE + 0x16)
#define REG_HDMI3_DUAL_0_0B_H       (REG_HDMI3_DUAL_0_BASE + 0x17)
#define REG_HDMI3_DUAL_0_0C_L       (REG_HDMI3_DUAL_0_BASE + 0x18)
#define REG_HDMI3_DUAL_0_0C_H       (REG_HDMI3_DUAL_0_BASE + 0x19)
#define REG_HDMI3_DUAL_0_0D_L       (REG_HDMI3_DUAL_0_BASE + 0x1A)
#define REG_HDMI3_DUAL_0_0D_H       (REG_HDMI3_DUAL_0_BASE + 0x1B)
#define REG_HDMI3_DUAL_0_0E_L       (REG_HDMI3_DUAL_0_BASE + 0x1C)
#define REG_HDMI3_DUAL_0_0E_H       (REG_HDMI3_DUAL_0_BASE + 0x1D)
#define REG_HDMI3_DUAL_0_0F_L       (REG_HDMI3_DUAL_0_BASE + 0x1E)
#define REG_HDMI3_DUAL_0_0F_H       (REG_HDMI3_DUAL_0_BASE + 0x1F)
#define REG_HDMI3_DUAL_0_10_L       (REG_HDMI3_DUAL_0_BASE + 0x20)
#define REG_HDMI3_DUAL_0_10_H       (REG_HDMI3_DUAL_0_BASE + 0x21)
#define REG_HDMI3_DUAL_0_11_L       (REG_HDMI3_DUAL_0_BASE + 0x22)
#define REG_HDMI3_DUAL_0_11_H       (REG_HDMI3_DUAL_0_BASE + 0x23)
#define REG_HDMI3_DUAL_0_12_L       (REG_HDMI3_DUAL_0_BASE + 0x24)
#define REG_HDMI3_DUAL_0_12_H       (REG_HDMI3_DUAL_0_BASE + 0x25)
#define REG_HDMI3_DUAL_0_13_L       (REG_HDMI3_DUAL_0_BASE + 0x26)
#define REG_HDMI3_DUAL_0_13_H       (REG_HDMI3_DUAL_0_BASE + 0x27)
#define REG_HDMI3_DUAL_0_14_L       (REG_HDMI3_DUAL_0_BASE + 0x28)
#define REG_HDMI3_DUAL_0_14_H       (REG_HDMI3_DUAL_0_BASE + 0x29)
#define REG_HDMI3_DUAL_0_15_L       (REG_HDMI3_DUAL_0_BASE + 0x2A)
#define REG_HDMI3_DUAL_0_15_H       (REG_HDMI3_DUAL_0_BASE + 0x2B)
#define REG_HDMI3_DUAL_0_16_L       (REG_HDMI3_DUAL_0_BASE + 0x2C)
#define REG_HDMI3_DUAL_0_16_H       (REG_HDMI3_DUAL_0_BASE + 0x2D)
#define REG_HDMI3_DUAL_0_17_L       (REG_HDMI3_DUAL_0_BASE + 0x2E)
#define REG_HDMI3_DUAL_0_17_H       (REG_HDMI3_DUAL_0_BASE + 0x2F)
#define REG_HDMI3_DUAL_0_18_L       (REG_HDMI3_DUAL_0_BASE + 0x30)
#define REG_HDMI3_DUAL_0_18_H       (REG_HDMI3_DUAL_0_BASE + 0x31)
#define REG_HDMI3_DUAL_0_19_L       (REG_HDMI3_DUAL_0_BASE + 0x32)
#define REG_HDMI3_DUAL_0_19_H       (REG_HDMI3_DUAL_0_BASE + 0x33)
#define REG_HDMI3_DUAL_0_1A_L       (REG_HDMI3_DUAL_0_BASE + 0x34)
#define REG_HDMI3_DUAL_0_1A_H       (REG_HDMI3_DUAL_0_BASE + 0x35)
#define REG_HDMI3_DUAL_0_1B_L       (REG_HDMI3_DUAL_0_BASE + 0x36)
#define REG_HDMI3_DUAL_0_1B_H       (REG_HDMI3_DUAL_0_BASE + 0x37)
#define REG_HDMI3_DUAL_0_1C_L       (REG_HDMI3_DUAL_0_BASE + 0x38)
#define REG_HDMI3_DUAL_0_1C_H       (REG_HDMI3_DUAL_0_BASE + 0x39)
#define REG_HDMI3_DUAL_0_1D_L       (REG_HDMI3_DUAL_0_BASE + 0x3A)
#define REG_HDMI3_DUAL_0_1D_H       (REG_HDMI3_DUAL_0_BASE + 0x3B)
#define REG_HDMI3_DUAL_0_1E_L       (REG_HDMI3_DUAL_0_BASE + 0x3C)
#define REG_HDMI3_DUAL_0_1E_H       (REG_HDMI3_DUAL_0_BASE + 0x3D)
#define REG_HDMI3_DUAL_0_1F_L       (REG_HDMI3_DUAL_0_BASE + 0x3E)
#define REG_HDMI3_DUAL_0_1F_H       (REG_HDMI3_DUAL_0_BASE + 0x3F)
#define REG_HDMI3_DUAL_0_20_L       (REG_HDMI3_DUAL_0_BASE + 0x40)
#define REG_HDMI3_DUAL_0_20_H       (REG_HDMI3_DUAL_0_BASE + 0x41)
#define REG_HDMI3_DUAL_0_21_L       (REG_HDMI3_DUAL_0_BASE + 0x42)
#define REG_HDMI3_DUAL_0_21_H       (REG_HDMI3_DUAL_0_BASE + 0x43)
#define REG_HDMI3_DUAL_0_22_L       (REG_HDMI3_DUAL_0_BASE + 0x44)
#define REG_HDMI3_DUAL_0_22_H       (REG_HDMI3_DUAL_0_BASE + 0x45)
#define REG_HDMI3_DUAL_0_23_L       (REG_HDMI3_DUAL_0_BASE + 0x46)
#define REG_HDMI3_DUAL_0_23_H       (REG_HDMI3_DUAL_0_BASE + 0x47)
#define REG_HDMI3_DUAL_0_24_L       (REG_HDMI3_DUAL_0_BASE + 0x48)
#define REG_HDMI3_DUAL_0_24_H       (REG_HDMI3_DUAL_0_BASE + 0x49)
#define REG_HDMI3_DUAL_0_25_L       (REG_HDMI3_DUAL_0_BASE + 0x4A)
#define REG_HDMI3_DUAL_0_25_H       (REG_HDMI3_DUAL_0_BASE + 0x4B)
#define REG_HDMI3_DUAL_0_26_L       (REG_HDMI3_DUAL_0_BASE + 0x4C)
#define REG_HDMI3_DUAL_0_26_H       (REG_HDMI3_DUAL_0_BASE + 0x4D)
#define REG_HDMI3_DUAL_0_27_L       (REG_HDMI3_DUAL_0_BASE + 0x4E)
#define REG_HDMI3_DUAL_0_27_H       (REG_HDMI3_DUAL_0_BASE + 0x4F)
#define REG_HDMI3_DUAL_0_28_L       (REG_HDMI3_DUAL_0_BASE + 0x50)
#define REG_HDMI3_DUAL_0_28_H       (REG_HDMI3_DUAL_0_BASE + 0x51)
#define REG_HDMI3_DUAL_0_29_L       (REG_HDMI3_DUAL_0_BASE + 0x52)
#define REG_HDMI3_DUAL_0_29_H       (REG_HDMI3_DUAL_0_BASE + 0x53)
#define REG_HDMI3_DUAL_0_2A_L       (REG_HDMI3_DUAL_0_BASE + 0x54)
#define REG_HDMI3_DUAL_0_2A_H       (REG_HDMI3_DUAL_0_BASE + 0x55)
#define REG_HDMI3_DUAL_0_2B_L       (REG_HDMI3_DUAL_0_BASE + 0x56)
#define REG_HDMI3_DUAL_0_2B_H       (REG_HDMI3_DUAL_0_BASE + 0x57)
#define REG_HDMI3_DUAL_0_2C_L       (REG_HDMI3_DUAL_0_BASE + 0x58)
#define REG_HDMI3_DUAL_0_2C_H       (REG_HDMI3_DUAL_0_BASE + 0x59)
#define REG_HDMI3_DUAL_0_2D_L       (REG_HDMI3_DUAL_0_BASE + 0x5A)
#define REG_HDMI3_DUAL_0_2D_H       (REG_HDMI3_DUAL_0_BASE + 0x5B)
#define REG_HDMI3_DUAL_0_2E_L       (REG_HDMI3_DUAL_0_BASE + 0x5C)
#define REG_HDMI3_DUAL_0_2E_H       (REG_HDMI3_DUAL_0_BASE + 0x5D)
#define REG_HDMI3_DUAL_0_2F_L       (REG_HDMI3_DUAL_0_BASE + 0x5E)
#define REG_HDMI3_DUAL_0_2F_H       (REG_HDMI3_DUAL_0_BASE + 0x5F)
#define REG_HDMI3_DUAL_0_30_L       (REG_HDMI3_DUAL_0_BASE + 0x60)
#define REG_HDMI3_DUAL_0_30_H       (REG_HDMI3_DUAL_0_BASE + 0x61)
#define REG_HDMI3_DUAL_0_31_L       (REG_HDMI3_DUAL_0_BASE + 0x62)
#define REG_HDMI3_DUAL_0_31_H       (REG_HDMI3_DUAL_0_BASE + 0x63)
#define REG_HDMI3_DUAL_0_32_L       (REG_HDMI3_DUAL_0_BASE + 0x64)
#define REG_HDMI3_DUAL_0_32_H       (REG_HDMI3_DUAL_0_BASE + 0x65)
#define REG_HDMI3_DUAL_0_33_L       (REG_HDMI3_DUAL_0_BASE + 0x66)
#define REG_HDMI3_DUAL_0_33_H       (REG_HDMI3_DUAL_0_BASE + 0x67)
#define REG_HDMI3_DUAL_0_34_L       (REG_HDMI3_DUAL_0_BASE + 0x68)
#define REG_HDMI3_DUAL_0_34_H       (REG_HDMI3_DUAL_0_BASE + 0x69)
#define REG_HDMI3_DUAL_0_35_L       (REG_HDMI3_DUAL_0_BASE + 0x6A)
#define REG_HDMI3_DUAL_0_35_H       (REG_HDMI3_DUAL_0_BASE + 0x6B)
#define REG_HDMI3_DUAL_0_36_L       (REG_HDMI3_DUAL_0_BASE + 0x6C)
#define REG_HDMI3_DUAL_0_36_H       (REG_HDMI3_DUAL_0_BASE + 0x6D)
#define REG_HDMI3_DUAL_0_37_L       (REG_HDMI3_DUAL_0_BASE + 0x6E)
#define REG_HDMI3_DUAL_0_37_H       (REG_HDMI3_DUAL_0_BASE + 0x6F)
#define REG_HDMI3_DUAL_0_38_L       (REG_HDMI3_DUAL_0_BASE + 0x70)
#define REG_HDMI3_DUAL_0_38_H       (REG_HDMI3_DUAL_0_BASE + 0x71)
#define REG_HDMI3_DUAL_0_39_L       (REG_HDMI3_DUAL_0_BASE + 0x72)
#define REG_HDMI3_DUAL_0_39_H       (REG_HDMI3_DUAL_0_BASE + 0x73)
#define REG_HDMI3_DUAL_0_3A_L       (REG_HDMI3_DUAL_0_BASE + 0x74)
#define REG_HDMI3_DUAL_0_3A_H       (REG_HDMI3_DUAL_0_BASE + 0x75)
#define REG_HDMI3_DUAL_0_3B_L       (REG_HDMI3_DUAL_0_BASE + 0x76)
#define REG_HDMI3_DUAL_0_3B_H       (REG_HDMI3_DUAL_0_BASE + 0x77)
#define REG_HDMI3_DUAL_0_3C_L       (REG_HDMI3_DUAL_0_BASE + 0x78)
#define REG_HDMI3_DUAL_0_3C_H       (REG_HDMI3_DUAL_0_BASE + 0x79)
#define REG_HDMI3_DUAL_0_3D_L       (REG_HDMI3_DUAL_0_BASE + 0x7A)
#define REG_HDMI3_DUAL_0_3D_H       (REG_HDMI3_DUAL_0_BASE + 0x7B)
#define REG_HDMI3_DUAL_0_3E_L       (REG_HDMI3_DUAL_0_BASE + 0x7C)
#define REG_HDMI3_DUAL_0_3E_H       (REG_HDMI3_DUAL_0_BASE + 0x7D)
#define REG_HDMI3_DUAL_0_3F_L       (REG_HDMI3_DUAL_0_BASE + 0x7E)
#define REG_HDMI3_DUAL_0_3F_H       (REG_HDMI3_DUAL_0_BASE + 0x7F)
#define REG_HDMI3_DUAL_0_40_L       (REG_HDMI3_DUAL_0_BASE + 0x80)
#define REG_HDMI3_DUAL_0_40_H       (REG_HDMI3_DUAL_0_BASE + 0x81)
#define REG_HDMI3_DUAL_0_41_L       (REG_HDMI3_DUAL_0_BASE + 0x82)
#define REG_HDMI3_DUAL_0_41_H       (REG_HDMI3_DUAL_0_BASE + 0x83)
#define REG_HDMI3_DUAL_0_42_L       (REG_HDMI3_DUAL_0_BASE + 0x84)
#define REG_HDMI3_DUAL_0_42_H       (REG_HDMI3_DUAL_0_BASE + 0x85)
#define REG_HDMI3_DUAL_0_43_L       (REG_HDMI3_DUAL_0_BASE + 0x86)
#define REG_HDMI3_DUAL_0_43_H       (REG_HDMI3_DUAL_0_BASE + 0x87)
#define REG_HDMI3_DUAL_0_44_L       (REG_HDMI3_DUAL_0_BASE + 0x88)
#define REG_HDMI3_DUAL_0_44_H       (REG_HDMI3_DUAL_0_BASE + 0x89)
#define REG_HDMI3_DUAL_0_45_L       (REG_HDMI3_DUAL_0_BASE + 0x8A)
#define REG_HDMI3_DUAL_0_45_H       (REG_HDMI3_DUAL_0_BASE + 0x8B)
#define REG_HDMI3_DUAL_0_46_L       (REG_HDMI3_DUAL_0_BASE + 0x8C)
#define REG_HDMI3_DUAL_0_46_H       (REG_HDMI3_DUAL_0_BASE + 0x8D)
#define REG_HDMI3_DUAL_0_47_L       (REG_HDMI3_DUAL_0_BASE + 0x8E)
#define REG_HDMI3_DUAL_0_47_H       (REG_HDMI3_DUAL_0_BASE + 0x8F)
#define REG_HDMI3_DUAL_0_48_L       (REG_HDMI3_DUAL_0_BASE + 0x90)
#define REG_HDMI3_DUAL_0_48_H       (REG_HDMI3_DUAL_0_BASE + 0x91)
#define REG_HDMI3_DUAL_0_49_L       (REG_HDMI3_DUAL_0_BASE + 0x92)
#define REG_HDMI3_DUAL_0_49_H       (REG_HDMI3_DUAL_0_BASE + 0x93)
#define REG_HDMI3_DUAL_0_4A_L       (REG_HDMI3_DUAL_0_BASE + 0x94)
#define REG_HDMI3_DUAL_0_4A_H       (REG_HDMI3_DUAL_0_BASE + 0x95)
#define REG_HDMI3_DUAL_0_4B_L       (REG_HDMI3_DUAL_0_BASE + 0x96)
#define REG_HDMI3_DUAL_0_4B_H       (REG_HDMI3_DUAL_0_BASE + 0x97)
#define REG_HDMI3_DUAL_0_4C_L       (REG_HDMI3_DUAL_0_BASE + 0x98)
#define REG_HDMI3_DUAL_0_4C_H       (REG_HDMI3_DUAL_0_BASE + 0x99)
#define REG_HDMI3_DUAL_0_4D_L       (REG_HDMI3_DUAL_0_BASE + 0x9A)
#define REG_HDMI3_DUAL_0_4D_H       (REG_HDMI3_DUAL_0_BASE + 0x9B)
#define REG_HDMI3_DUAL_0_4E_L       (REG_HDMI3_DUAL_0_BASE + 0x9C)
#define REG_HDMI3_DUAL_0_4E_H       (REG_HDMI3_DUAL_0_BASE + 0x9D)
#define REG_HDMI3_DUAL_0_4F_L       (REG_HDMI3_DUAL_0_BASE + 0x9E)
#define REG_HDMI3_DUAL_0_4F_H       (REG_HDMI3_DUAL_0_BASE + 0x9F)
#define REG_HDMI3_DUAL_0_50_L       (REG_HDMI3_DUAL_0_BASE + 0xA0)
#define REG_HDMI3_DUAL_0_50_H       (REG_HDMI3_DUAL_0_BASE + 0xA1)
#define REG_HDMI3_DUAL_0_51_L       (REG_HDMI3_DUAL_0_BASE + 0xA2)
#define REG_HDMI3_DUAL_0_51_H       (REG_HDMI3_DUAL_0_BASE + 0xA3)
#define REG_HDMI3_DUAL_0_52_L       (REG_HDMI3_DUAL_0_BASE + 0xA4)
#define REG_HDMI3_DUAL_0_52_H       (REG_HDMI3_DUAL_0_BASE + 0xA5)
#define REG_HDMI3_DUAL_0_53_L       (REG_HDMI3_DUAL_0_BASE + 0xA6)
#define REG_HDMI3_DUAL_0_53_H       (REG_HDMI3_DUAL_0_BASE + 0xA7)
#define REG_HDMI3_DUAL_0_54_L       (REG_HDMI3_DUAL_0_BASE + 0xA8)
#define REG_HDMI3_DUAL_0_54_H       (REG_HDMI3_DUAL_0_BASE + 0xA9)
#define REG_HDMI3_DUAL_0_55_L       (REG_HDMI3_DUAL_0_BASE + 0xAA)
#define REG_HDMI3_DUAL_0_55_H       (REG_HDMI3_DUAL_0_BASE + 0xAB)
#define REG_HDMI3_DUAL_0_56_L       (REG_HDMI3_DUAL_0_BASE + 0xAC)
#define REG_HDMI3_DUAL_0_56_H       (REG_HDMI3_DUAL_0_BASE + 0xAD)
#define REG_HDMI3_DUAL_0_57_L       (REG_HDMI3_DUAL_0_BASE + 0xAE)
#define REG_HDMI3_DUAL_0_57_H       (REG_HDMI3_DUAL_0_BASE + 0xAF)
#define REG_HDMI3_DUAL_0_58_L       (REG_HDMI3_DUAL_0_BASE + 0xB0)
#define REG_HDMI3_DUAL_0_58_H       (REG_HDMI3_DUAL_0_BASE + 0xB1)
#define REG_HDMI3_DUAL_0_59_L       (REG_HDMI3_DUAL_0_BASE + 0xB2)
#define REG_HDMI3_DUAL_0_59_H       (REG_HDMI3_DUAL_0_BASE + 0xB3)
#define REG_HDMI3_DUAL_0_5A_L       (REG_HDMI3_DUAL_0_BASE + 0xB4)
#define REG_HDMI3_DUAL_0_5A_H       (REG_HDMI3_DUAL_0_BASE + 0xB5)
#define REG_HDMI3_DUAL_0_5B_L       (REG_HDMI3_DUAL_0_BASE + 0xB6)
#define REG_HDMI3_DUAL_0_5B_H       (REG_HDMI3_DUAL_0_BASE + 0xB7)
#define REG_HDMI3_DUAL_0_5C_L       (REG_HDMI3_DUAL_0_BASE + 0xB8)
#define REG_HDMI3_DUAL_0_5C_H       (REG_HDMI3_DUAL_0_BASE + 0xB9)
#define REG_HDMI3_DUAL_0_5D_L       (REG_HDMI3_DUAL_0_BASE + 0xBA)
#define REG_HDMI3_DUAL_0_5D_H       (REG_HDMI3_DUAL_0_BASE + 0xBB)
#define REG_HDMI3_DUAL_0_5E_L       (REG_HDMI3_DUAL_0_BASE + 0xBC)
#define REG_HDMI3_DUAL_0_5E_H       (REG_HDMI3_DUAL_0_BASE + 0xBD)
#define REG_HDMI3_DUAL_0_5F_L       (REG_HDMI3_DUAL_0_BASE + 0xBE)
#define REG_HDMI3_DUAL_0_5F_H       (REG_HDMI3_DUAL_0_BASE + 0xBF)
#define REG_HDMI3_DUAL_0_60_L       (REG_HDMI3_DUAL_0_BASE + 0xC0)
#define REG_HDMI3_DUAL_0_60_H       (REG_HDMI3_DUAL_0_BASE + 0xC1)
#define REG_HDMI3_DUAL_0_61_L       (REG_HDMI3_DUAL_0_BASE + 0xC2)
#define REG_HDMI3_DUAL_0_61_H       (REG_HDMI3_DUAL_0_BASE + 0xC3)
#define REG_HDMI3_DUAL_0_62_L       (REG_HDMI3_DUAL_0_BASE + 0xC4)
#define REG_HDMI3_DUAL_0_62_H       (REG_HDMI3_DUAL_0_BASE + 0xC5)
#define REG_HDMI3_DUAL_0_63_L       (REG_HDMI3_DUAL_0_BASE + 0xC6)
#define REG_HDMI3_DUAL_0_63_H       (REG_HDMI3_DUAL_0_BASE + 0xC7)
#define REG_HDMI3_DUAL_0_64_L       (REG_HDMI3_DUAL_0_BASE + 0xC8)
#define REG_HDMI3_DUAL_0_64_H       (REG_HDMI3_DUAL_0_BASE + 0xC9)
#define REG_HDMI3_DUAL_0_65_L       (REG_HDMI3_DUAL_0_BASE + 0xCA)
#define REG_HDMI3_DUAL_0_65_H       (REG_HDMI3_DUAL_0_BASE + 0xCB)
#define REG_HDMI3_DUAL_0_66_L       (REG_HDMI3_DUAL_0_BASE + 0xCC)
#define REG_HDMI3_DUAL_0_66_H       (REG_HDMI3_DUAL_0_BASE + 0xCD)
#define REG_HDMI3_DUAL_0_67_L       (REG_HDMI3_DUAL_0_BASE + 0xCE)
#define REG_HDMI3_DUAL_0_67_H       (REG_HDMI3_DUAL_0_BASE + 0xCF)
#define REG_HDMI3_DUAL_0_68_L       (REG_HDMI3_DUAL_0_BASE + 0xD0)
#define REG_HDMI3_DUAL_0_68_H       (REG_HDMI3_DUAL_0_BASE + 0xD1)
#define REG_HDMI3_DUAL_0_69_L       (REG_HDMI3_DUAL_0_BASE + 0xD2)
#define REG_HDMI3_DUAL_0_69_H       (REG_HDMI3_DUAL_0_BASE + 0xD3)
#define REG_HDMI3_DUAL_0_6A_L       (REG_HDMI3_DUAL_0_BASE + 0xD4)
#define REG_HDMI3_DUAL_0_6A_H       (REG_HDMI3_DUAL_0_BASE + 0xD5)
#define REG_HDMI3_DUAL_0_6B_L       (REG_HDMI3_DUAL_0_BASE + 0xD6)
#define REG_HDMI3_DUAL_0_6B_H       (REG_HDMI3_DUAL_0_BASE + 0xD7)
#define REG_HDMI3_DUAL_0_6C_L       (REG_HDMI3_DUAL_0_BASE + 0xD8)
#define REG_HDMI3_DUAL_0_6C_H       (REG_HDMI3_DUAL_0_BASE + 0xD9)
#define REG_HDMI3_DUAL_0_6D_L       (REG_HDMI3_DUAL_0_BASE + 0xDA)
#define REG_HDMI3_DUAL_0_6D_H       (REG_HDMI3_DUAL_0_BASE + 0xDB)
#define REG_HDMI3_DUAL_0_6E_L       (REG_HDMI3_DUAL_0_BASE + 0xDC)
#define REG_HDMI3_DUAL_0_6E_H       (REG_HDMI3_DUAL_0_BASE + 0xDD)
#define REG_HDMI3_DUAL_0_6F_L       (REG_HDMI3_DUAL_0_BASE + 0xDE)
#define REG_HDMI3_DUAL_0_6F_H       (REG_HDMI3_DUAL_0_BASE + 0xDF)
#define REG_HDMI3_DUAL_0_70_L       (REG_HDMI3_DUAL_0_BASE + 0xE0)
#define REG_HDMI3_DUAL_0_70_H       (REG_HDMI3_DUAL_0_BASE + 0xE1)
#define REG_HDMI3_DUAL_0_71_L       (REG_HDMI3_DUAL_0_BASE + 0xE2)
#define REG_HDMI3_DUAL_0_71_H       (REG_HDMI3_DUAL_0_BASE + 0xE3)
#define REG_HDMI3_DUAL_0_72_L       (REG_HDMI3_DUAL_0_BASE + 0xE4)
#define REG_HDMI3_DUAL_0_72_H       (REG_HDMI3_DUAL_0_BASE + 0xE5)
#define REG_HDMI3_DUAL_0_73_L       (REG_HDMI3_DUAL_0_BASE + 0xE6)
#define REG_HDMI3_DUAL_0_73_H       (REG_HDMI3_DUAL_0_BASE + 0xE7)
#define REG_HDMI3_DUAL_0_74_L       (REG_HDMI3_DUAL_0_BASE + 0xE8)
#define REG_HDMI3_DUAL_0_74_H       (REG_HDMI3_DUAL_0_BASE + 0xE9)
#define REG_HDMI3_DUAL_0_75_L       (REG_HDMI3_DUAL_0_BASE + 0xEA)
#define REG_HDMI3_DUAL_0_75_H       (REG_HDMI3_DUAL_0_BASE + 0xEB)
#define REG_HDMI3_DUAL_0_76_L       (REG_HDMI3_DUAL_0_BASE + 0xEC)
#define REG_HDMI3_DUAL_0_76_H       (REG_HDMI3_DUAL_0_BASE + 0xED)
#define REG_HDMI3_DUAL_0_77_L       (REG_HDMI3_DUAL_0_BASE + 0xEE)
#define REG_HDMI3_DUAL_0_77_H       (REG_HDMI3_DUAL_0_BASE + 0xEF)
#define REG_HDMI3_DUAL_0_78_L       (REG_HDMI3_DUAL_0_BASE + 0xF0)
#define REG_HDMI3_DUAL_0_78_H       (REG_HDMI3_DUAL_0_BASE + 0xF1)
#define REG_HDMI3_DUAL_0_79_L       (REG_HDMI3_DUAL_0_BASE + 0xF2)
#define REG_HDMI3_DUAL_0_79_H       (REG_HDMI3_DUAL_0_BASE + 0xF3)
#define REG_HDMI3_DUAL_0_7A_L       (REG_HDMI3_DUAL_0_BASE + 0xF4)
#define REG_HDMI3_DUAL_0_7A_H       (REG_HDMI3_DUAL_0_BASE + 0xF5)
#define REG_HDMI3_DUAL_0_7B_L       (REG_HDMI3_DUAL_0_BASE + 0xF6)
#define REG_HDMI3_DUAL_0_7B_H       (REG_HDMI3_DUAL_0_BASE + 0xF7)
#define REG_HDMI3_DUAL_0_7C_L       (REG_HDMI3_DUAL_0_BASE + 0xF8)
#define REG_HDMI3_DUAL_0_7C_H       (REG_HDMI3_DUAL_0_BASE + 0xF9)
#define REG_HDMI3_DUAL_0_7D_L       (REG_HDMI3_DUAL_0_BASE + 0xFA)
#define REG_HDMI3_DUAL_0_7D_H       (REG_HDMI3_DUAL_0_BASE + 0xFB)
#define REG_HDMI3_DUAL_0_7E_L       (REG_HDMI3_DUAL_0_BASE + 0xFC)
#define REG_HDMI3_DUAL_0_7E_H       (REG_HDMI3_DUAL_0_BASE + 0xFD)
#define REG_HDMI3_DUAL_0_7F_L       (REG_HDMI3_DUAL_0_BASE + 0xFE)
#define REG_HDMI3_DUAL_0_7F_H       (REG_HDMI3_DUAL_0_BASE + 0xFF)

// HDMI_DUAL_1
#define REG_HDMI_DUAL_1_00_L       (REG_HDMI_DUAL_1_BASE + 0x00)
#define REG_HDMI_DUAL_1_00_H       (REG_HDMI_DUAL_1_BASE + 0x01)
#define REG_HDMI_DUAL_1_01_L       (REG_HDMI_DUAL_1_BASE + 0x02)
#define REG_HDMI_DUAL_1_01_H       (REG_HDMI_DUAL_1_BASE + 0x03)
#define REG_HDMI_DUAL_1_02_L       (REG_HDMI_DUAL_1_BASE + 0x04)
#define REG_HDMI_DUAL_1_02_H       (REG_HDMI_DUAL_1_BASE + 0x05)
#define REG_HDMI_DUAL_1_03_L       (REG_HDMI_DUAL_1_BASE + 0x06)
#define REG_HDMI_DUAL_1_03_H       (REG_HDMI_DUAL_1_BASE + 0x07)
#define REG_HDMI_DUAL_1_04_L       (REG_HDMI_DUAL_1_BASE + 0x08)
#define REG_HDMI_DUAL_1_04_H       (REG_HDMI_DUAL_1_BASE + 0x09)
#define REG_HDMI_DUAL_1_05_L       (REG_HDMI_DUAL_1_BASE + 0x0A)
#define REG_HDMI_DUAL_1_05_H       (REG_HDMI_DUAL_1_BASE + 0x0B)
#define REG_HDMI_DUAL_1_06_L       (REG_HDMI_DUAL_1_BASE + 0x0C)
#define REG_HDMI_DUAL_1_06_H       (REG_HDMI_DUAL_1_BASE + 0x0D)
#define REG_HDMI_DUAL_1_07_L       (REG_HDMI_DUAL_1_BASE + 0x0E)
#define REG_HDMI_DUAL_1_07_H       (REG_HDMI_DUAL_1_BASE + 0x0F)
#define REG_HDMI_DUAL_1_08_L       (REG_HDMI_DUAL_1_BASE + 0x10)
#define REG_HDMI_DUAL_1_08_H       (REG_HDMI_DUAL_1_BASE + 0x11)
#define REG_HDMI_DUAL_1_09_L       (REG_HDMI_DUAL_1_BASE + 0x12)
#define REG_HDMI_DUAL_1_09_H       (REG_HDMI_DUAL_1_BASE + 0x13)
#define REG_HDMI_DUAL_1_0A_L       (REG_HDMI_DUAL_1_BASE + 0x14)
#define REG_HDMI_DUAL_1_0A_H       (REG_HDMI_DUAL_1_BASE + 0x15)
#define REG_HDMI_DUAL_1_0B_L       (REG_HDMI_DUAL_1_BASE + 0x16)
#define REG_HDMI_DUAL_1_0B_H       (REG_HDMI_DUAL_1_BASE + 0x17)
#define REG_HDMI_DUAL_1_0C_L       (REG_HDMI_DUAL_1_BASE + 0x18)
#define REG_HDMI_DUAL_1_0C_H       (REG_HDMI_DUAL_1_BASE + 0x19)
#define REG_HDMI_DUAL_1_0D_L       (REG_HDMI_DUAL_1_BASE + 0x1A)
#define REG_HDMI_DUAL_1_0D_H       (REG_HDMI_DUAL_1_BASE + 0x1B)
#define REG_HDMI_DUAL_1_0E_L       (REG_HDMI_DUAL_1_BASE + 0x1C)
#define REG_HDMI_DUAL_1_0E_H       (REG_HDMI_DUAL_1_BASE + 0x1D)
#define REG_HDMI_DUAL_1_0F_L       (REG_HDMI_DUAL_1_BASE + 0x1E)
#define REG_HDMI_DUAL_1_0F_H       (REG_HDMI_DUAL_1_BASE + 0x1F)
#define REG_HDMI_DUAL_1_10_L       (REG_HDMI_DUAL_1_BASE + 0x20)
#define REG_HDMI_DUAL_1_10_H       (REG_HDMI_DUAL_1_BASE + 0x21)
#define REG_HDMI_DUAL_1_11_L       (REG_HDMI_DUAL_1_BASE + 0x22)
#define REG_HDMI_DUAL_1_11_H       (REG_HDMI_DUAL_1_BASE + 0x23)
#define REG_HDMI_DUAL_1_12_L       (REG_HDMI_DUAL_1_BASE + 0x24)
#define REG_HDMI_DUAL_1_12_H       (REG_HDMI_DUAL_1_BASE + 0x25)
#define REG_HDMI_DUAL_1_13_L       (REG_HDMI_DUAL_1_BASE + 0x26)
#define REG_HDMI_DUAL_1_13_H       (REG_HDMI_DUAL_1_BASE + 0x27)
#define REG_HDMI_DUAL_1_14_L       (REG_HDMI_DUAL_1_BASE + 0x28)
#define REG_HDMI_DUAL_1_14_H       (REG_HDMI_DUAL_1_BASE + 0x29)
#define REG_HDMI_DUAL_1_15_L       (REG_HDMI_DUAL_1_BASE + 0x2A)
#define REG_HDMI_DUAL_1_15_H       (REG_HDMI_DUAL_1_BASE + 0x2B)
#define REG_HDMI_DUAL_1_16_L       (REG_HDMI_DUAL_1_BASE + 0x2C)
#define REG_HDMI_DUAL_1_16_H       (REG_HDMI_DUAL_1_BASE + 0x2D)
#define REG_HDMI_DUAL_1_17_L       (REG_HDMI_DUAL_1_BASE + 0x2E)
#define REG_HDMI_DUAL_1_17_H       (REG_HDMI_DUAL_1_BASE + 0x2F)
#define REG_HDMI_DUAL_1_18_L       (REG_HDMI_DUAL_1_BASE + 0x30)
#define REG_HDMI_DUAL_1_18_H       (REG_HDMI_DUAL_1_BASE + 0x31)
#define REG_HDMI_DUAL_1_19_L       (REG_HDMI_DUAL_1_BASE + 0x32)
#define REG_HDMI_DUAL_1_19_H       (REG_HDMI_DUAL_1_BASE + 0x33)
#define REG_HDMI_DUAL_1_1A_L       (REG_HDMI_DUAL_1_BASE + 0x34)
#define REG_HDMI_DUAL_1_1A_H       (REG_HDMI_DUAL_1_BASE + 0x35)
#define REG_HDMI_DUAL_1_1B_L       (REG_HDMI_DUAL_1_BASE + 0x36)
#define REG_HDMI_DUAL_1_1B_H       (REG_HDMI_DUAL_1_BASE + 0x37)
#define REG_HDMI_DUAL_1_1C_L       (REG_HDMI_DUAL_1_BASE + 0x38)
#define REG_HDMI_DUAL_1_1C_H       (REG_HDMI_DUAL_1_BASE + 0x39)
#define REG_HDMI_DUAL_1_1D_L       (REG_HDMI_DUAL_1_BASE + 0x3A)
#define REG_HDMI_DUAL_1_1D_H       (REG_HDMI_DUAL_1_BASE + 0x3B)
#define REG_HDMI_DUAL_1_1E_L       (REG_HDMI_DUAL_1_BASE + 0x3C)
#define REG_HDMI_DUAL_1_1E_H       (REG_HDMI_DUAL_1_BASE + 0x3D)
#define REG_HDMI_DUAL_1_1F_L       (REG_HDMI_DUAL_1_BASE + 0x3E)
#define REG_HDMI_DUAL_1_1F_H       (REG_HDMI_DUAL_1_BASE + 0x3F)
#define REG_HDMI_DUAL_1_20_L       (REG_HDMI_DUAL_1_BASE + 0x40)
#define REG_HDMI_DUAL_1_20_H       (REG_HDMI_DUAL_1_BASE + 0x41)
#define REG_HDMI_DUAL_1_21_L       (REG_HDMI_DUAL_1_BASE + 0x42)
#define REG_HDMI_DUAL_1_21_H       (REG_HDMI_DUAL_1_BASE + 0x43)
#define REG_HDMI_DUAL_1_22_L       (REG_HDMI_DUAL_1_BASE + 0x44)
#define REG_HDMI_DUAL_1_22_H       (REG_HDMI_DUAL_1_BASE + 0x45)
#define REG_HDMI_DUAL_1_23_L       (REG_HDMI_DUAL_1_BASE + 0x46)
#define REG_HDMI_DUAL_1_23_H       (REG_HDMI_DUAL_1_BASE + 0x47)
#define REG_HDMI_DUAL_1_24_L       (REG_HDMI_DUAL_1_BASE + 0x48)
#define REG_HDMI_DUAL_1_24_H       (REG_HDMI_DUAL_1_BASE + 0x49)
#define REG_HDMI_DUAL_1_25_L       (REG_HDMI_DUAL_1_BASE + 0x4A)
#define REG_HDMI_DUAL_1_25_H       (REG_HDMI_DUAL_1_BASE + 0x4B)
#define REG_HDMI_DUAL_1_26_L       (REG_HDMI_DUAL_1_BASE + 0x4C)
#define REG_HDMI_DUAL_1_26_H       (REG_HDMI_DUAL_1_BASE + 0x4D)
#define REG_HDMI_DUAL_1_27_L       (REG_HDMI_DUAL_1_BASE + 0x4E)
#define REG_HDMI_DUAL_1_27_H       (REG_HDMI_DUAL_1_BASE + 0x4F)
#define REG_HDMI_DUAL_1_28_L       (REG_HDMI_DUAL_1_BASE + 0x50)
#define REG_HDMI_DUAL_1_28_H       (REG_HDMI_DUAL_1_BASE + 0x51)
#define REG_HDMI_DUAL_1_29_L       (REG_HDMI_DUAL_1_BASE + 0x52)
#define REG_HDMI_DUAL_1_29_H       (REG_HDMI_DUAL_1_BASE + 0x53)
#define REG_HDMI_DUAL_1_2A_L       (REG_HDMI_DUAL_1_BASE + 0x54)
#define REG_HDMI_DUAL_1_2A_H       (REG_HDMI_DUAL_1_BASE + 0x55)
#define REG_HDMI_DUAL_1_2B_L       (REG_HDMI_DUAL_1_BASE + 0x56)
#define REG_HDMI_DUAL_1_2B_H       (REG_HDMI_DUAL_1_BASE + 0x57)
#define REG_HDMI_DUAL_1_2C_L       (REG_HDMI_DUAL_1_BASE + 0x58)
#define REG_HDMI_DUAL_1_2C_H       (REG_HDMI_DUAL_1_BASE + 0x59)
#define REG_HDMI_DUAL_1_2D_L       (REG_HDMI_DUAL_1_BASE + 0x5A)
#define REG_HDMI_DUAL_1_2D_H       (REG_HDMI_DUAL_1_BASE + 0x5B)
#define REG_HDMI_DUAL_1_2E_L       (REG_HDMI_DUAL_1_BASE + 0x5C)
#define REG_HDMI_DUAL_1_2E_H       (REG_HDMI_DUAL_1_BASE + 0x5D)
#define REG_HDMI_DUAL_1_2F_L       (REG_HDMI_DUAL_1_BASE + 0x5E)
#define REG_HDMI_DUAL_1_2F_H       (REG_HDMI_DUAL_1_BASE + 0x5F)
#define REG_HDMI_DUAL_1_30_L       (REG_HDMI_DUAL_1_BASE + 0x60)
#define REG_HDMI_DUAL_1_30_H       (REG_HDMI_DUAL_1_BASE + 0x61)
#define REG_HDMI_DUAL_1_31_L       (REG_HDMI_DUAL_1_BASE + 0x62)
#define REG_HDMI_DUAL_1_31_H       (REG_HDMI_DUAL_1_BASE + 0x63)
#define REG_HDMI_DUAL_1_32_L       (REG_HDMI_DUAL_1_BASE + 0x64)
#define REG_HDMI_DUAL_1_32_H       (REG_HDMI_DUAL_1_BASE + 0x65)
#define REG_HDMI_DUAL_1_33_L       (REG_HDMI_DUAL_1_BASE + 0x66)
#define REG_HDMI_DUAL_1_33_H       (REG_HDMI_DUAL_1_BASE + 0x67)
#define REG_HDMI_DUAL_1_34_L       (REG_HDMI_DUAL_1_BASE + 0x68)
#define REG_HDMI_DUAL_1_34_H       (REG_HDMI_DUAL_1_BASE + 0x69)
#define REG_HDMI_DUAL_1_35_L       (REG_HDMI_DUAL_1_BASE + 0x6A)
#define REG_HDMI_DUAL_1_35_H       (REG_HDMI_DUAL_1_BASE + 0x6B)
#define REG_HDMI_DUAL_1_36_L       (REG_HDMI_DUAL_1_BASE + 0x6C)
#define REG_HDMI_DUAL_1_36_H       (REG_HDMI_DUAL_1_BASE + 0x6D)
#define REG_HDMI_DUAL_1_37_L       (REG_HDMI_DUAL_1_BASE + 0x6E)
#define REG_HDMI_DUAL_1_37_H       (REG_HDMI_DUAL_1_BASE + 0x6F)
#define REG_HDMI_DUAL_1_38_L       (REG_HDMI_DUAL_1_BASE + 0x70)
#define REG_HDMI_DUAL_1_38_H       (REG_HDMI_DUAL_1_BASE + 0x71)
#define REG_HDMI_DUAL_1_39_L       (REG_HDMI_DUAL_1_BASE + 0x72)
#define REG_HDMI_DUAL_1_39_H       (REG_HDMI_DUAL_1_BASE + 0x73)
#define REG_HDMI_DUAL_1_3A_L       (REG_HDMI_DUAL_1_BASE + 0x74)
#define REG_HDMI_DUAL_1_3A_H       (REG_HDMI_DUAL_1_BASE + 0x75)
#define REG_HDMI_DUAL_1_3B_L       (REG_HDMI_DUAL_1_BASE + 0x76)
#define REG_HDMI_DUAL_1_3B_H       (REG_HDMI_DUAL_1_BASE + 0x77)
#define REG_HDMI_DUAL_1_3C_L       (REG_HDMI_DUAL_1_BASE + 0x78)
#define REG_HDMI_DUAL_1_3C_H       (REG_HDMI_DUAL_1_BASE + 0x79)
#define REG_HDMI_DUAL_1_3D_L       (REG_HDMI_DUAL_1_BASE + 0x7A)
#define REG_HDMI_DUAL_1_3D_H       (REG_HDMI_DUAL_1_BASE + 0x7B)
#define REG_HDMI_DUAL_1_3E_L       (REG_HDMI_DUAL_1_BASE + 0x7C)
#define REG_HDMI_DUAL_1_3E_H       (REG_HDMI_DUAL_1_BASE + 0x7D)
#define REG_HDMI_DUAL_1_3F_L       (REG_HDMI_DUAL_1_BASE + 0x7E)
#define REG_HDMI_DUAL_1_3F_H       (REG_HDMI_DUAL_1_BASE + 0x7F)
#define REG_HDMI_DUAL_1_40_L       (REG_HDMI_DUAL_1_BASE + 0x80)
#define REG_HDMI_DUAL_1_40_H       (REG_HDMI_DUAL_1_BASE + 0x81)
#define REG_HDMI_DUAL_1_41_L       (REG_HDMI_DUAL_1_BASE + 0x82)
#define REG_HDMI_DUAL_1_41_H       (REG_HDMI_DUAL_1_BASE + 0x83)
#define REG_HDMI_DUAL_1_42_L       (REG_HDMI_DUAL_1_BASE + 0x84)
#define REG_HDMI_DUAL_1_42_H       (REG_HDMI_DUAL_1_BASE + 0x85)
#define REG_HDMI_DUAL_1_43_L       (REG_HDMI_DUAL_1_BASE + 0x86)
#define REG_HDMI_DUAL_1_43_H       (REG_HDMI_DUAL_1_BASE + 0x87)
#define REG_HDMI_DUAL_1_44_L       (REG_HDMI_DUAL_1_BASE + 0x88)
#define REG_HDMI_DUAL_1_44_H       (REG_HDMI_DUAL_1_BASE + 0x89)
#define REG_HDMI_DUAL_1_45_L       (REG_HDMI_DUAL_1_BASE + 0x8A)
#define REG_HDMI_DUAL_1_45_H       (REG_HDMI_DUAL_1_BASE + 0x8B)
#define REG_HDMI_DUAL_1_46_L       (REG_HDMI_DUAL_1_BASE + 0x8C)
#define REG_HDMI_DUAL_1_46_H       (REG_HDMI_DUAL_1_BASE + 0x8D)
#define REG_HDMI_DUAL_1_47_L       (REG_HDMI_DUAL_1_BASE + 0x8E)
#define REG_HDMI_DUAL_1_47_H       (REG_HDMI_DUAL_1_BASE + 0x8F)
#define REG_HDMI_DUAL_1_48_L       (REG_HDMI_DUAL_1_BASE + 0x90)
#define REG_HDMI_DUAL_1_48_H       (REG_HDMI_DUAL_1_BASE + 0x91)
#define REG_HDMI_DUAL_1_49_L       (REG_HDMI_DUAL_1_BASE + 0x92)
#define REG_HDMI_DUAL_1_49_H       (REG_HDMI_DUAL_1_BASE + 0x93)
#define REG_HDMI_DUAL_1_4A_L       (REG_HDMI_DUAL_1_BASE + 0x94)
#define REG_HDMI_DUAL_1_4A_H       (REG_HDMI_DUAL_1_BASE + 0x95)
#define REG_HDMI_DUAL_1_4B_L       (REG_HDMI_DUAL_1_BASE + 0x96)
#define REG_HDMI_DUAL_1_4B_H       (REG_HDMI_DUAL_1_BASE + 0x97)
#define REG_HDMI_DUAL_1_4C_L       (REG_HDMI_DUAL_1_BASE + 0x98)
#define REG_HDMI_DUAL_1_4C_H       (REG_HDMI_DUAL_1_BASE + 0x99)
#define REG_HDMI_DUAL_1_4D_L       (REG_HDMI_DUAL_1_BASE + 0x9A)
#define REG_HDMI_DUAL_1_4D_H       (REG_HDMI_DUAL_1_BASE + 0x9B)
#define REG_HDMI_DUAL_1_4E_L       (REG_HDMI_DUAL_1_BASE + 0x9C)
#define REG_HDMI_DUAL_1_4E_H       (REG_HDMI_DUAL_1_BASE + 0x9D)
#define REG_HDMI_DUAL_1_4F_L       (REG_HDMI_DUAL_1_BASE + 0x9E)
#define REG_HDMI_DUAL_1_4F_H       (REG_HDMI_DUAL_1_BASE + 0x9F)
#define REG_HDMI_DUAL_1_50_L       (REG_HDMI_DUAL_1_BASE + 0xA0)
#define REG_HDMI_DUAL_1_50_H       (REG_HDMI_DUAL_1_BASE + 0xA1)
#define REG_HDMI_DUAL_1_51_L       (REG_HDMI_DUAL_1_BASE + 0xA2)
#define REG_HDMI_DUAL_1_51_H       (REG_HDMI_DUAL_1_BASE + 0xA3)
#define REG_HDMI_DUAL_1_52_L       (REG_HDMI_DUAL_1_BASE + 0xA4)
#define REG_HDMI_DUAL_1_52_H       (REG_HDMI_DUAL_1_BASE + 0xA5)
#define REG_HDMI_DUAL_1_53_L       (REG_HDMI_DUAL_1_BASE + 0xA6)
#define REG_HDMI_DUAL_1_53_H       (REG_HDMI_DUAL_1_BASE + 0xA7)
#define REG_HDMI_DUAL_1_54_L       (REG_HDMI_DUAL_1_BASE + 0xA8)
#define REG_HDMI_DUAL_1_54_H       (REG_HDMI_DUAL_1_BASE + 0xA9)
#define REG_HDMI_DUAL_1_55_L       (REG_HDMI_DUAL_1_BASE + 0xAA)
#define REG_HDMI_DUAL_1_55_H       (REG_HDMI_DUAL_1_BASE + 0xAB)
#define REG_HDMI_DUAL_1_56_L       (REG_HDMI_DUAL_1_BASE + 0xAC)
#define REG_HDMI_DUAL_1_56_H       (REG_HDMI_DUAL_1_BASE + 0xAD)
#define REG_HDMI_DUAL_1_57_L       (REG_HDMI_DUAL_1_BASE + 0xAE)
#define REG_HDMI_DUAL_1_57_H       (REG_HDMI_DUAL_1_BASE + 0xAF)
#define REG_HDMI_DUAL_1_58_L       (REG_HDMI_DUAL_1_BASE + 0xB0)
#define REG_HDMI_DUAL_1_58_H       (REG_HDMI_DUAL_1_BASE + 0xB1)
#define REG_HDMI_DUAL_1_59_L       (REG_HDMI_DUAL_1_BASE + 0xB2)
#define REG_HDMI_DUAL_1_59_H       (REG_HDMI_DUAL_1_BASE + 0xB3)
#define REG_HDMI_DUAL_1_5A_L       (REG_HDMI_DUAL_1_BASE + 0xB4)
#define REG_HDMI_DUAL_1_5A_H       (REG_HDMI_DUAL_1_BASE + 0xB5)
#define REG_HDMI_DUAL_1_5B_L       (REG_HDMI_DUAL_1_BASE + 0xB6)
#define REG_HDMI_DUAL_1_5B_H       (REG_HDMI_DUAL_1_BASE + 0xB7)
#define REG_HDMI_DUAL_1_5C_L       (REG_HDMI_DUAL_1_BASE + 0xB8)
#define REG_HDMI_DUAL_1_5C_H       (REG_HDMI_DUAL_1_BASE + 0xB9)
#define REG_HDMI_DUAL_1_5D_L       (REG_HDMI_DUAL_1_BASE + 0xBA)
#define REG_HDMI_DUAL_1_5D_H       (REG_HDMI_DUAL_1_BASE + 0xBB)
#define REG_HDMI_DUAL_1_5E_L       (REG_HDMI_DUAL_1_BASE + 0xBC)
#define REG_HDMI_DUAL_1_5E_H       (REG_HDMI_DUAL_1_BASE + 0xBD)
#define REG_HDMI_DUAL_1_5F_L       (REG_HDMI_DUAL_1_BASE + 0xBE)
#define REG_HDMI_DUAL_1_5F_H       (REG_HDMI_DUAL_1_BASE + 0xBF)
#define REG_HDMI_DUAL_1_60_L       (REG_HDMI_DUAL_1_BASE + 0xC0)
#define REG_HDMI_DUAL_1_60_H       (REG_HDMI_DUAL_1_BASE + 0xC1)
#define REG_HDMI_DUAL_1_61_L       (REG_HDMI_DUAL_1_BASE + 0xC2)
#define REG_HDMI_DUAL_1_61_H       (REG_HDMI_DUAL_1_BASE + 0xC3)
#define REG_HDMI_DUAL_1_62_L       (REG_HDMI_DUAL_1_BASE + 0xC4)
#define REG_HDMI_DUAL_1_62_H       (REG_HDMI_DUAL_1_BASE + 0xC5)
#define REG_HDMI_DUAL_1_63_L       (REG_HDMI_DUAL_1_BASE + 0xC6)
#define REG_HDMI_DUAL_1_63_H       (REG_HDMI_DUAL_1_BASE + 0xC7)
#define REG_HDMI_DUAL_1_64_L       (REG_HDMI_DUAL_1_BASE + 0xC8)
#define REG_HDMI_DUAL_1_64_H       (REG_HDMI_DUAL_1_BASE + 0xC9)
#define REG_HDMI_DUAL_1_65_L       (REG_HDMI_DUAL_1_BASE + 0xCA)
#define REG_HDMI_DUAL_1_65_H       (REG_HDMI_DUAL_1_BASE + 0xCB)
#define REG_HDMI_DUAL_1_66_L       (REG_HDMI_DUAL_1_BASE + 0xCC)
#define REG_HDMI_DUAL_1_66_H       (REG_HDMI_DUAL_1_BASE + 0xCD)
#define REG_HDMI_DUAL_1_67_L       (REG_HDMI_DUAL_1_BASE + 0xCE)
#define REG_HDMI_DUAL_1_67_H       (REG_HDMI_DUAL_1_BASE + 0xCF)
#define REG_HDMI_DUAL_1_68_L       (REG_HDMI_DUAL_1_BASE + 0xD0)
#define REG_HDMI_DUAL_1_68_H       (REG_HDMI_DUAL_1_BASE + 0xD1)
#define REG_HDMI_DUAL_1_69_L       (REG_HDMI_DUAL_1_BASE + 0xD2)
#define REG_HDMI_DUAL_1_69_H       (REG_HDMI_DUAL_1_BASE + 0xD3)
#define REG_HDMI_DUAL_1_6A_L       (REG_HDMI_DUAL_1_BASE + 0xD4)
#define REG_HDMI_DUAL_1_6A_H       (REG_HDMI_DUAL_1_BASE + 0xD5)
#define REG_HDMI_DUAL_1_6B_L       (REG_HDMI_DUAL_1_BASE + 0xD6)
#define REG_HDMI_DUAL_1_6B_H       (REG_HDMI_DUAL_1_BASE + 0xD7)
#define REG_HDMI_DUAL_1_6C_L       (REG_HDMI_DUAL_1_BASE + 0xD8)
#define REG_HDMI_DUAL_1_6C_H       (REG_HDMI_DUAL_1_BASE + 0xD9)
#define REG_HDMI_DUAL_1_6D_L       (REG_HDMI_DUAL_1_BASE + 0xDA)
#define REG_HDMI_DUAL_1_6D_H       (REG_HDMI_DUAL_1_BASE + 0xDB)
#define REG_HDMI_DUAL_1_6E_L       (REG_HDMI_DUAL_1_BASE + 0xDC)
#define REG_HDMI_DUAL_1_6E_H       (REG_HDMI_DUAL_1_BASE + 0xDD)
#define REG_HDMI_DUAL_1_6F_L       (REG_HDMI_DUAL_1_BASE + 0xDE)
#define REG_HDMI_DUAL_1_6F_H       (REG_HDMI_DUAL_1_BASE + 0xDF)
#define REG_HDMI_DUAL_1_70_L       (REG_HDMI_DUAL_1_BASE + 0xE0)
#define REG_HDMI_DUAL_1_70_H       (REG_HDMI_DUAL_1_BASE + 0xE1)
#define REG_HDMI_DUAL_1_71_L       (REG_HDMI_DUAL_1_BASE + 0xE2)
#define REG_HDMI_DUAL_1_71_H       (REG_HDMI_DUAL_1_BASE + 0xE3)
#define REG_HDMI_DUAL_1_72_L       (REG_HDMI_DUAL_1_BASE + 0xE4)
#define REG_HDMI_DUAL_1_72_H       (REG_HDMI_DUAL_1_BASE + 0xE5)
#define REG_HDMI_DUAL_1_73_L       (REG_HDMI_DUAL_1_BASE + 0xE6)
#define REG_HDMI_DUAL_1_73_H       (REG_HDMI_DUAL_1_BASE + 0xE7)
#define REG_HDMI_DUAL_1_74_L       (REG_HDMI_DUAL_1_BASE + 0xE8)
#define REG_HDMI_DUAL_1_74_H       (REG_HDMI_DUAL_1_BASE + 0xE9)
#define REG_HDMI_DUAL_1_75_L       (REG_HDMI_DUAL_1_BASE + 0xEA)
#define REG_HDMI_DUAL_1_75_H       (REG_HDMI_DUAL_1_BASE + 0xEB)
#define REG_HDMI_DUAL_1_76_L       (REG_HDMI_DUAL_1_BASE + 0xEC)
#define REG_HDMI_DUAL_1_76_H       (REG_HDMI_DUAL_1_BASE + 0xED)
#define REG_HDMI_DUAL_1_77_L       (REG_HDMI_DUAL_1_BASE + 0xEE)
#define REG_HDMI_DUAL_1_77_H       (REG_HDMI_DUAL_1_BASE + 0xEF)
#define REG_HDMI_DUAL_1_78_L       (REG_HDMI_DUAL_1_BASE + 0xF0)
#define REG_HDMI_DUAL_1_78_H       (REG_HDMI_DUAL_1_BASE + 0xF1)
#define REG_HDMI_DUAL_1_79_L       (REG_HDMI_DUAL_1_BASE + 0xF2)
#define REG_HDMI_DUAL_1_79_H       (REG_HDMI_DUAL_1_BASE + 0xF3)
#define REG_HDMI_DUAL_1_7A_L       (REG_HDMI_DUAL_1_BASE + 0xF4)
#define REG_HDMI_DUAL_1_7A_H       (REG_HDMI_DUAL_1_BASE + 0xF5)
#define REG_HDMI_DUAL_1_7B_L       (REG_HDMI_DUAL_1_BASE + 0xF6)
#define REG_HDMI_DUAL_1_7B_H       (REG_HDMI_DUAL_1_BASE + 0xF7)
#define REG_HDMI_DUAL_1_7C_L       (REG_HDMI_DUAL_1_BASE + 0xF8)
#define REG_HDMI_DUAL_1_7C_H       (REG_HDMI_DUAL_1_BASE + 0xF9)
#define REG_HDMI_DUAL_1_7D_L       (REG_HDMI_DUAL_1_BASE + 0xFA)
#define REG_HDMI_DUAL_1_7D_H       (REG_HDMI_DUAL_1_BASE + 0xFB)
#define REG_HDMI_DUAL_1_7E_L       (REG_HDMI_DUAL_1_BASE + 0xFC)
#define REG_HDMI_DUAL_1_7E_H       (REG_HDMI_DUAL_1_BASE + 0xFD)
#define REG_HDMI_DUAL_1_7F_L       (REG_HDMI_DUAL_1_BASE + 0xFE)
#define REG_HDMI_DUAL_1_7F_H       (REG_HDMI_DUAL_1_BASE + 0xFF)

// HDMI2_DUAL_1
#define REG_HDMI2_DUAL_1_00_L       (REG_HDMI2_DUAL_1_BASE + 0x00)
#define REG_HDMI2_DUAL_1_00_H       (REG_HDMI2_DUAL_1_BASE + 0x01)
#define REG_HDMI2_DUAL_1_01_L       (REG_HDMI2_DUAL_1_BASE + 0x02)
#define REG_HDMI2_DUAL_1_01_H       (REG_HDMI2_DUAL_1_BASE + 0x03)
#define REG_HDMI2_DUAL_1_02_L       (REG_HDMI2_DUAL_1_BASE + 0x04)
#define REG_HDMI2_DUAL_1_02_H       (REG_HDMI2_DUAL_1_BASE + 0x05)
#define REG_HDMI2_DUAL_1_03_L       (REG_HDMI2_DUAL_1_BASE + 0x06)
#define REG_HDMI2_DUAL_1_03_H       (REG_HDMI2_DUAL_1_BASE + 0x07)
#define REG_HDMI2_DUAL_1_04_L       (REG_HDMI2_DUAL_1_BASE + 0x08)
#define REG_HDMI2_DUAL_1_04_H       (REG_HDMI2_DUAL_1_BASE + 0x09)
#define REG_HDMI2_DUAL_1_05_L       (REG_HDMI2_DUAL_1_BASE + 0x0A)
#define REG_HDMI2_DUAL_1_05_H       (REG_HDMI2_DUAL_1_BASE + 0x0B)
#define REG_HDMI2_DUAL_1_06_L       (REG_HDMI2_DUAL_1_BASE + 0x0C)
#define REG_HDMI2_DUAL_1_06_H       (REG_HDMI2_DUAL_1_BASE + 0x0D)
#define REG_HDMI2_DUAL_1_07_L       (REG_HDMI2_DUAL_1_BASE + 0x0E)
#define REG_HDMI2_DUAL_1_07_H       (REG_HDMI2_DUAL_1_BASE + 0x0F)
#define REG_HDMI2_DUAL_1_08_L       (REG_HDMI2_DUAL_1_BASE + 0x10)
#define REG_HDMI2_DUAL_1_08_H       (REG_HDMI2_DUAL_1_BASE + 0x11)
#define REG_HDMI2_DUAL_1_09_L       (REG_HDMI2_DUAL_1_BASE + 0x12)
#define REG_HDMI2_DUAL_1_09_H       (REG_HDMI2_DUAL_1_BASE + 0x13)
#define REG_HDMI2_DUAL_1_0A_L       (REG_HDMI2_DUAL_1_BASE + 0x14)
#define REG_HDMI2_DUAL_1_0A_H       (REG_HDMI2_DUAL_1_BASE + 0x15)
#define REG_HDMI2_DUAL_1_0B_L       (REG_HDMI2_DUAL_1_BASE + 0x16)
#define REG_HDMI2_DUAL_1_0B_H       (REG_HDMI2_DUAL_1_BASE + 0x17)
#define REG_HDMI2_DUAL_1_0C_L       (REG_HDMI2_DUAL_1_BASE + 0x18)
#define REG_HDMI2_DUAL_1_0C_H       (REG_HDMI2_DUAL_1_BASE + 0x19)
#define REG_HDMI2_DUAL_1_0D_L       (REG_HDMI2_DUAL_1_BASE + 0x1A)
#define REG_HDMI2_DUAL_1_0D_H       (REG_HDMI2_DUAL_1_BASE + 0x1B)
#define REG_HDMI2_DUAL_1_0E_L       (REG_HDMI2_DUAL_1_BASE + 0x1C)
#define REG_HDMI2_DUAL_1_0E_H       (REG_HDMI2_DUAL_1_BASE + 0x1D)
#define REG_HDMI2_DUAL_1_0F_L       (REG_HDMI2_DUAL_1_BASE + 0x1E)
#define REG_HDMI2_DUAL_1_0F_H       (REG_HDMI2_DUAL_1_BASE + 0x1F)
#define REG_HDMI2_DUAL_1_10_L       (REG_HDMI2_DUAL_1_BASE + 0x20)
#define REG_HDMI2_DUAL_1_10_H       (REG_HDMI2_DUAL_1_BASE + 0x21)
#define REG_HDMI2_DUAL_1_11_L       (REG_HDMI2_DUAL_1_BASE + 0x22)
#define REG_HDMI2_DUAL_1_11_H       (REG_HDMI2_DUAL_1_BASE + 0x23)
#define REG_HDMI2_DUAL_1_12_L       (REG_HDMI2_DUAL_1_BASE + 0x24)
#define REG_HDMI2_DUAL_1_12_H       (REG_HDMI2_DUAL_1_BASE + 0x25)
#define REG_HDMI2_DUAL_1_13_L       (REG_HDMI2_DUAL_1_BASE + 0x26)
#define REG_HDMI2_DUAL_1_13_H       (REG_HDMI2_DUAL_1_BASE + 0x27)
#define REG_HDMI2_DUAL_1_14_L       (REG_HDMI2_DUAL_1_BASE + 0x28)
#define REG_HDMI2_DUAL_1_14_H       (REG_HDMI2_DUAL_1_BASE + 0x29)
#define REG_HDMI2_DUAL_1_15_L       (REG_HDMI2_DUAL_1_BASE + 0x2A)
#define REG_HDMI2_DUAL_1_15_H       (REG_HDMI2_DUAL_1_BASE + 0x2B)
#define REG_HDMI2_DUAL_1_16_L       (REG_HDMI2_DUAL_1_BASE + 0x2C)
#define REG_HDMI2_DUAL_1_16_H       (REG_HDMI2_DUAL_1_BASE + 0x2D)
#define REG_HDMI2_DUAL_1_17_L       (REG_HDMI2_DUAL_1_BASE + 0x2E)
#define REG_HDMI2_DUAL_1_17_H       (REG_HDMI2_DUAL_1_BASE + 0x2F)
#define REG_HDMI2_DUAL_1_18_L       (REG_HDMI2_DUAL_1_BASE + 0x30)
#define REG_HDMI2_DUAL_1_18_H       (REG_HDMI2_DUAL_1_BASE + 0x31)
#define REG_HDMI2_DUAL_1_19_L       (REG_HDMI2_DUAL_1_BASE + 0x32)
#define REG_HDMI2_DUAL_1_19_H       (REG_HDMI2_DUAL_1_BASE + 0x33)
#define REG_HDMI2_DUAL_1_1A_L       (REG_HDMI2_DUAL_1_BASE + 0x34)
#define REG_HDMI2_DUAL_1_1A_H       (REG_HDMI2_DUAL_1_BASE + 0x35)
#define REG_HDMI2_DUAL_1_1B_L       (REG_HDMI2_DUAL_1_BASE + 0x36)
#define REG_HDMI2_DUAL_1_1B_H       (REG_HDMI2_DUAL_1_BASE + 0x37)
#define REG_HDMI2_DUAL_1_1C_L       (REG_HDMI2_DUAL_1_BASE + 0x38)
#define REG_HDMI2_DUAL_1_1C_H       (REG_HDMI2_DUAL_1_BASE + 0x39)
#define REG_HDMI2_DUAL_1_1D_L       (REG_HDMI2_DUAL_1_BASE + 0x3A)
#define REG_HDMI2_DUAL_1_1D_H       (REG_HDMI2_DUAL_1_BASE + 0x3B)
#define REG_HDMI2_DUAL_1_1E_L       (REG_HDMI2_DUAL_1_BASE + 0x3C)
#define REG_HDMI2_DUAL_1_1E_H       (REG_HDMI2_DUAL_1_BASE + 0x3D)
#define REG_HDMI2_DUAL_1_1F_L       (REG_HDMI2_DUAL_1_BASE + 0x3E)
#define REG_HDMI2_DUAL_1_1F_H       (REG_HDMI2_DUAL_1_BASE + 0x3F)
#define REG_HDMI2_DUAL_1_20_L       (REG_HDMI2_DUAL_1_BASE + 0x40)
#define REG_HDMI2_DUAL_1_20_H       (REG_HDMI2_DUAL_1_BASE + 0x41)
#define REG_HDMI2_DUAL_1_21_L       (REG_HDMI2_DUAL_1_BASE + 0x42)
#define REG_HDMI2_DUAL_1_21_H       (REG_HDMI2_DUAL_1_BASE + 0x43)
#define REG_HDMI2_DUAL_1_22_L       (REG_HDMI2_DUAL_1_BASE + 0x44)
#define REG_HDMI2_DUAL_1_22_H       (REG_HDMI2_DUAL_1_BASE + 0x45)
#define REG_HDMI2_DUAL_1_23_L       (REG_HDMI2_DUAL_1_BASE + 0x46)
#define REG_HDMI2_DUAL_1_23_H       (REG_HDMI2_DUAL_1_BASE + 0x47)
#define REG_HDMI2_DUAL_1_24_L       (REG_HDMI2_DUAL_1_BASE + 0x48)
#define REG_HDMI2_DUAL_1_24_H       (REG_HDMI2_DUAL_1_BASE + 0x49)
#define REG_HDMI2_DUAL_1_25_L       (REG_HDMI2_DUAL_1_BASE + 0x4A)
#define REG_HDMI2_DUAL_1_25_H       (REG_HDMI2_DUAL_1_BASE + 0x4B)
#define REG_HDMI2_DUAL_1_26_L       (REG_HDMI2_DUAL_1_BASE + 0x4C)
#define REG_HDMI2_DUAL_1_26_H       (REG_HDMI2_DUAL_1_BASE + 0x4D)
#define REG_HDMI2_DUAL_1_27_L       (REG_HDMI2_DUAL_1_BASE + 0x4E)
#define REG_HDMI2_DUAL_1_27_H       (REG_HDMI2_DUAL_1_BASE + 0x4F)
#define REG_HDMI2_DUAL_1_28_L       (REG_HDMI2_DUAL_1_BASE + 0x50)
#define REG_HDMI2_DUAL_1_28_H       (REG_HDMI2_DUAL_1_BASE + 0x51)
#define REG_HDMI2_DUAL_1_29_L       (REG_HDMI2_DUAL_1_BASE + 0x52)
#define REG_HDMI2_DUAL_1_29_H       (REG_HDMI2_DUAL_1_BASE + 0x53)
#define REG_HDMI2_DUAL_1_2A_L       (REG_HDMI2_DUAL_1_BASE + 0x54)
#define REG_HDMI2_DUAL_1_2A_H       (REG_HDMI2_DUAL_1_BASE + 0x55)
#define REG_HDMI2_DUAL_1_2B_L       (REG_HDMI2_DUAL_1_BASE + 0x56)
#define REG_HDMI2_DUAL_1_2B_H       (REG_HDMI2_DUAL_1_BASE + 0x57)
#define REG_HDMI2_DUAL_1_2C_L       (REG_HDMI2_DUAL_1_BASE + 0x58)
#define REG_HDMI2_DUAL_1_2C_H       (REG_HDMI2_DUAL_1_BASE + 0x59)
#define REG_HDMI2_DUAL_1_2D_L       (REG_HDMI2_DUAL_1_BASE + 0x5A)
#define REG_HDMI2_DUAL_1_2D_H       (REG_HDMI2_DUAL_1_BASE + 0x5B)
#define REG_HDMI2_DUAL_1_2E_L       (REG_HDMI2_DUAL_1_BASE + 0x5C)
#define REG_HDMI2_DUAL_1_2E_H       (REG_HDMI2_DUAL_1_BASE + 0x5D)
#define REG_HDMI2_DUAL_1_2F_L       (REG_HDMI2_DUAL_1_BASE + 0x5E)
#define REG_HDMI2_DUAL_1_2F_H       (REG_HDMI2_DUAL_1_BASE + 0x5F)
#define REG_HDMI2_DUAL_1_30_L       (REG_HDMI2_DUAL_1_BASE + 0x60)
#define REG_HDMI2_DUAL_1_30_H       (REG_HDMI2_DUAL_1_BASE + 0x61)
#define REG_HDMI2_DUAL_1_31_L       (REG_HDMI2_DUAL_1_BASE + 0x62)
#define REG_HDMI2_DUAL_1_31_H       (REG_HDMI2_DUAL_1_BASE + 0x63)
#define REG_HDMI2_DUAL_1_32_L       (REG_HDMI2_DUAL_1_BASE + 0x64)
#define REG_HDMI2_DUAL_1_32_H       (REG_HDMI2_DUAL_1_BASE + 0x65)
#define REG_HDMI2_DUAL_1_33_L       (REG_HDMI2_DUAL_1_BASE + 0x66)
#define REG_HDMI2_DUAL_1_33_H       (REG_HDMI2_DUAL_1_BASE + 0x67)
#define REG_HDMI2_DUAL_1_34_L       (REG_HDMI2_DUAL_1_BASE + 0x68)
#define REG_HDMI2_DUAL_1_34_H       (REG_HDMI2_DUAL_1_BASE + 0x69)
#define REG_HDMI2_DUAL_1_35_L       (REG_HDMI2_DUAL_1_BASE + 0x6A)
#define REG_HDMI2_DUAL_1_35_H       (REG_HDMI2_DUAL_1_BASE + 0x6B)
#define REG_HDMI2_DUAL_1_36_L       (REG_HDMI2_DUAL_1_BASE + 0x6C)
#define REG_HDMI2_DUAL_1_36_H       (REG_HDMI2_DUAL_1_BASE + 0x6D)
#define REG_HDMI2_DUAL_1_37_L       (REG_HDMI2_DUAL_1_BASE + 0x6E)
#define REG_HDMI2_DUAL_1_37_H       (REG_HDMI2_DUAL_1_BASE + 0x6F)
#define REG_HDMI2_DUAL_1_38_L       (REG_HDMI2_DUAL_1_BASE + 0x70)
#define REG_HDMI2_DUAL_1_38_H       (REG_HDMI2_DUAL_1_BASE + 0x71)
#define REG_HDMI2_DUAL_1_39_L       (REG_HDMI2_DUAL_1_BASE + 0x72)
#define REG_HDMI2_DUAL_1_39_H       (REG_HDMI2_DUAL_1_BASE + 0x73)
#define REG_HDMI2_DUAL_1_3A_L       (REG_HDMI2_DUAL_1_BASE + 0x74)
#define REG_HDMI2_DUAL_1_3A_H       (REG_HDMI2_DUAL_1_BASE + 0x75)
#define REG_HDMI2_DUAL_1_3B_L       (REG_HDMI2_DUAL_1_BASE + 0x76)
#define REG_HDMI2_DUAL_1_3B_H       (REG_HDMI2_DUAL_1_BASE + 0x77)
#define REG_HDMI2_DUAL_1_3C_L       (REG_HDMI2_DUAL_1_BASE + 0x78)
#define REG_HDMI2_DUAL_1_3C_H       (REG_HDMI2_DUAL_1_BASE + 0x79)
#define REG_HDMI2_DUAL_1_3D_L       (REG_HDMI2_DUAL_1_BASE + 0x7A)
#define REG_HDMI2_DUAL_1_3D_H       (REG_HDMI2_DUAL_1_BASE + 0x7B)
#define REG_HDMI2_DUAL_1_3E_L       (REG_HDMI2_DUAL_1_BASE + 0x7C)
#define REG_HDMI2_DUAL_1_3E_H       (REG_HDMI2_DUAL_1_BASE + 0x7D)
#define REG_HDMI2_DUAL_1_3F_L       (REG_HDMI2_DUAL_1_BASE + 0x7E)
#define REG_HDMI2_DUAL_1_3F_H       (REG_HDMI2_DUAL_1_BASE + 0x7F)
#define REG_HDMI2_DUAL_1_40_L       (REG_HDMI2_DUAL_1_BASE + 0x80)
#define REG_HDMI2_DUAL_1_40_H       (REG_HDMI2_DUAL_1_BASE + 0x81)
#define REG_HDMI2_DUAL_1_41_L       (REG_HDMI2_DUAL_1_BASE + 0x82)
#define REG_HDMI2_DUAL_1_41_H       (REG_HDMI2_DUAL_1_BASE + 0x83)
#define REG_HDMI2_DUAL_1_42_L       (REG_HDMI2_DUAL_1_BASE + 0x84)
#define REG_HDMI2_DUAL_1_42_H       (REG_HDMI2_DUAL_1_BASE + 0x85)
#define REG_HDMI2_DUAL_1_43_L       (REG_HDMI2_DUAL_1_BASE + 0x86)
#define REG_HDMI2_DUAL_1_43_H       (REG_HDMI2_DUAL_1_BASE + 0x87)
#define REG_HDMI2_DUAL_1_44_L       (REG_HDMI2_DUAL_1_BASE + 0x88)
#define REG_HDMI2_DUAL_1_44_H       (REG_HDMI2_DUAL_1_BASE + 0x89)
#define REG_HDMI2_DUAL_1_45_L       (REG_HDMI2_DUAL_1_BASE + 0x8A)
#define REG_HDMI2_DUAL_1_45_H       (REG_HDMI2_DUAL_1_BASE + 0x8B)
#define REG_HDMI2_DUAL_1_46_L       (REG_HDMI2_DUAL_1_BASE + 0x8C)
#define REG_HDMI2_DUAL_1_46_H       (REG_HDMI2_DUAL_1_BASE + 0x8D)
#define REG_HDMI2_DUAL_1_47_L       (REG_HDMI2_DUAL_1_BASE + 0x8E)
#define REG_HDMI2_DUAL_1_47_H       (REG_HDMI2_DUAL_1_BASE + 0x8F)
#define REG_HDMI2_DUAL_1_48_L       (REG_HDMI2_DUAL_1_BASE + 0x90)
#define REG_HDMI2_DUAL_1_48_H       (REG_HDMI2_DUAL_1_BASE + 0x91)
#define REG_HDMI2_DUAL_1_49_L       (REG_HDMI2_DUAL_1_BASE + 0x92)
#define REG_HDMI2_DUAL_1_49_H       (REG_HDMI2_DUAL_1_BASE + 0x93)
#define REG_HDMI2_DUAL_1_4A_L       (REG_HDMI2_DUAL_1_BASE + 0x94)
#define REG_HDMI2_DUAL_1_4A_H       (REG_HDMI2_DUAL_1_BASE + 0x95)
#define REG_HDMI2_DUAL_1_4B_L       (REG_HDMI2_DUAL_1_BASE + 0x96)
#define REG_HDMI2_DUAL_1_4B_H       (REG_HDMI2_DUAL_1_BASE + 0x97)
#define REG_HDMI2_DUAL_1_4C_L       (REG_HDMI2_DUAL_1_BASE + 0x98)
#define REG_HDMI2_DUAL_1_4C_H       (REG_HDMI2_DUAL_1_BASE + 0x99)
#define REG_HDMI2_DUAL_1_4D_L       (REG_HDMI2_DUAL_1_BASE + 0x9A)
#define REG_HDMI2_DUAL_1_4D_H       (REG_HDMI2_DUAL_1_BASE + 0x9B)
#define REG_HDMI2_DUAL_1_4E_L       (REG_HDMI2_DUAL_1_BASE + 0x9C)
#define REG_HDMI2_DUAL_1_4E_H       (REG_HDMI2_DUAL_1_BASE + 0x9D)
#define REG_HDMI2_DUAL_1_4F_L       (REG_HDMI2_DUAL_1_BASE + 0x9E)
#define REG_HDMI2_DUAL_1_4F_H       (REG_HDMI2_DUAL_1_BASE + 0x9F)
#define REG_HDMI2_DUAL_1_50_L       (REG_HDMI2_DUAL_1_BASE + 0xA0)
#define REG_HDMI2_DUAL_1_50_H       (REG_HDMI2_DUAL_1_BASE + 0xA1)
#define REG_HDMI2_DUAL_1_51_L       (REG_HDMI2_DUAL_1_BASE + 0xA2)
#define REG_HDMI2_DUAL_1_51_H       (REG_HDMI2_DUAL_1_BASE + 0xA3)
#define REG_HDMI2_DUAL_1_52_L       (REG_HDMI2_DUAL_1_BASE + 0xA4)
#define REG_HDMI2_DUAL_1_52_H       (REG_HDMI2_DUAL_1_BASE + 0xA5)
#define REG_HDMI2_DUAL_1_53_L       (REG_HDMI2_DUAL_1_BASE + 0xA6)
#define REG_HDMI2_DUAL_1_53_H       (REG_HDMI2_DUAL_1_BASE + 0xA7)
#define REG_HDMI2_DUAL_1_54_L       (REG_HDMI2_DUAL_1_BASE + 0xA8)
#define REG_HDMI2_DUAL_1_54_H       (REG_HDMI2_DUAL_1_BASE + 0xA9)
#define REG_HDMI2_DUAL_1_55_L       (REG_HDMI2_DUAL_1_BASE + 0xAA)
#define REG_HDMI2_DUAL_1_55_H       (REG_HDMI2_DUAL_1_BASE + 0xAB)
#define REG_HDMI2_DUAL_1_56_L       (REG_HDMI2_DUAL_1_BASE + 0xAC)
#define REG_HDMI2_DUAL_1_56_H       (REG_HDMI2_DUAL_1_BASE + 0xAD)
#define REG_HDMI2_DUAL_1_57_L       (REG_HDMI2_DUAL_1_BASE + 0xAE)
#define REG_HDMI2_DUAL_1_57_H       (REG_HDMI2_DUAL_1_BASE + 0xAF)
#define REG_HDMI2_DUAL_1_58_L       (REG_HDMI2_DUAL_1_BASE + 0xB0)
#define REG_HDMI2_DUAL_1_58_H       (REG_HDMI2_DUAL_1_BASE + 0xB1)
#define REG_HDMI2_DUAL_1_59_L       (REG_HDMI2_DUAL_1_BASE + 0xB2)
#define REG_HDMI2_DUAL_1_59_H       (REG_HDMI2_DUAL_1_BASE + 0xB3)
#define REG_HDMI2_DUAL_1_5A_L       (REG_HDMI2_DUAL_1_BASE + 0xB4)
#define REG_HDMI2_DUAL_1_5A_H       (REG_HDMI2_DUAL_1_BASE + 0xB5)
#define REG_HDMI2_DUAL_1_5B_L       (REG_HDMI2_DUAL_1_BASE + 0xB6)
#define REG_HDMI2_DUAL_1_5B_H       (REG_HDMI2_DUAL_1_BASE + 0xB7)
#define REG_HDMI2_DUAL_1_5C_L       (REG_HDMI2_DUAL_1_BASE + 0xB8)
#define REG_HDMI2_DUAL_1_5C_H       (REG_HDMI2_DUAL_1_BASE + 0xB9)
#define REG_HDMI2_DUAL_1_5D_L       (REG_HDMI2_DUAL_1_BASE + 0xBA)
#define REG_HDMI2_DUAL_1_5D_H       (REG_HDMI2_DUAL_1_BASE + 0xBB)
#define REG_HDMI2_DUAL_1_5E_L       (REG_HDMI2_DUAL_1_BASE + 0xBC)
#define REG_HDMI2_DUAL_1_5E_H       (REG_HDMI2_DUAL_1_BASE + 0xBD)
#define REG_HDMI2_DUAL_1_5F_L       (REG_HDMI2_DUAL_1_BASE + 0xBE)
#define REG_HDMI2_DUAL_1_5F_H       (REG_HDMI2_DUAL_1_BASE + 0xBF)
#define REG_HDMI2_DUAL_1_60_L       (REG_HDMI2_DUAL_1_BASE + 0xC0)
#define REG_HDMI2_DUAL_1_60_H       (REG_HDMI2_DUAL_1_BASE + 0xC1)
#define REG_HDMI2_DUAL_1_61_L       (REG_HDMI2_DUAL_1_BASE + 0xC2)
#define REG_HDMI2_DUAL_1_61_H       (REG_HDMI2_DUAL_1_BASE + 0xC3)
#define REG_HDMI2_DUAL_1_62_L       (REG_HDMI2_DUAL_1_BASE + 0xC4)
#define REG_HDMI2_DUAL_1_62_H       (REG_HDMI2_DUAL_1_BASE + 0xC5)
#define REG_HDMI2_DUAL_1_63_L       (REG_HDMI2_DUAL_1_BASE + 0xC6)
#define REG_HDMI2_DUAL_1_63_H       (REG_HDMI2_DUAL_1_BASE + 0xC7)
#define REG_HDMI2_DUAL_1_64_L       (REG_HDMI2_DUAL_1_BASE + 0xC8)
#define REG_HDMI2_DUAL_1_64_H       (REG_HDMI2_DUAL_1_BASE + 0xC9)
#define REG_HDMI2_DUAL_1_65_L       (REG_HDMI2_DUAL_1_BASE + 0xCA)
#define REG_HDMI2_DUAL_1_65_H       (REG_HDMI2_DUAL_1_BASE + 0xCB)
#define REG_HDMI2_DUAL_1_66_L       (REG_HDMI2_DUAL_1_BASE + 0xCC)
#define REG_HDMI2_DUAL_1_66_H       (REG_HDMI2_DUAL_1_BASE + 0xCD)
#define REG_HDMI2_DUAL_1_67_L       (REG_HDMI2_DUAL_1_BASE + 0xCE)
#define REG_HDMI2_DUAL_1_67_H       (REG_HDMI2_DUAL_1_BASE + 0xCF)
#define REG_HDMI2_DUAL_1_68_L       (REG_HDMI2_DUAL_1_BASE + 0xD0)
#define REG_HDMI2_DUAL_1_68_H       (REG_HDMI2_DUAL_1_BASE + 0xD1)
#define REG_HDMI2_DUAL_1_69_L       (REG_HDMI2_DUAL_1_BASE + 0xD2)
#define REG_HDMI2_DUAL_1_69_H       (REG_HDMI2_DUAL_1_BASE + 0xD3)
#define REG_HDMI2_DUAL_1_6A_L       (REG_HDMI2_DUAL_1_BASE + 0xD4)
#define REG_HDMI2_DUAL_1_6A_H       (REG_HDMI2_DUAL_1_BASE + 0xD5)
#define REG_HDMI2_DUAL_1_6B_L       (REG_HDMI2_DUAL_1_BASE + 0xD6)
#define REG_HDMI2_DUAL_1_6B_H       (REG_HDMI2_DUAL_1_BASE + 0xD7)
#define REG_HDMI2_DUAL_1_6C_L       (REG_HDMI2_DUAL_1_BASE + 0xD8)
#define REG_HDMI2_DUAL_1_6C_H       (REG_HDMI2_DUAL_1_BASE + 0xD9)
#define REG_HDMI2_DUAL_1_6D_L       (REG_HDMI2_DUAL_1_BASE + 0xDA)
#define REG_HDMI2_DUAL_1_6D_H       (REG_HDMI2_DUAL_1_BASE + 0xDB)
#define REG_HDMI2_DUAL_1_6E_L       (REG_HDMI2_DUAL_1_BASE + 0xDC)
#define REG_HDMI2_DUAL_1_6E_H       (REG_HDMI2_DUAL_1_BASE + 0xDD)
#define REG_HDMI2_DUAL_1_6F_L       (REG_HDMI2_DUAL_1_BASE + 0xDE)
#define REG_HDMI2_DUAL_1_6F_H       (REG_HDMI2_DUAL_1_BASE + 0xDF)
#define REG_HDMI2_DUAL_1_70_L       (REG_HDMI2_DUAL_1_BASE + 0xE0)
#define REG_HDMI2_DUAL_1_70_H       (REG_HDMI2_DUAL_1_BASE + 0xE1)
#define REG_HDMI2_DUAL_1_71_L       (REG_HDMI2_DUAL_1_BASE + 0xE2)
#define REG_HDMI2_DUAL_1_71_H       (REG_HDMI2_DUAL_1_BASE + 0xE3)
#define REG_HDMI2_DUAL_1_72_L       (REG_HDMI2_DUAL_1_BASE + 0xE4)
#define REG_HDMI2_DUAL_1_72_H       (REG_HDMI2_DUAL_1_BASE + 0xE5)
#define REG_HDMI2_DUAL_1_73_L       (REG_HDMI2_DUAL_1_BASE + 0xE6)
#define REG_HDMI2_DUAL_1_73_H       (REG_HDMI2_DUAL_1_BASE + 0xE7)
#define REG_HDMI2_DUAL_1_74_L       (REG_HDMI2_DUAL_1_BASE + 0xE8)
#define REG_HDMI2_DUAL_1_74_H       (REG_HDMI2_DUAL_1_BASE + 0xE9)
#define REG_HDMI2_DUAL_1_75_L       (REG_HDMI2_DUAL_1_BASE + 0xEA)
#define REG_HDMI2_DUAL_1_75_H       (REG_HDMI2_DUAL_1_BASE + 0xEB)
#define REG_HDMI2_DUAL_1_76_L       (REG_HDMI2_DUAL_1_BASE + 0xEC)
#define REG_HDMI2_DUAL_1_76_H       (REG_HDMI2_DUAL_1_BASE + 0xED)
#define REG_HDMI2_DUAL_1_77_L       (REG_HDMI2_DUAL_1_BASE + 0xEE)
#define REG_HDMI2_DUAL_1_77_H       (REG_HDMI2_DUAL_1_BASE + 0xEF)
#define REG_HDMI2_DUAL_1_78_L       (REG_HDMI2_DUAL_1_BASE + 0xF0)
#define REG_HDMI2_DUAL_1_78_H       (REG_HDMI2_DUAL_1_BASE + 0xF1)
#define REG_HDMI2_DUAL_1_79_L       (REG_HDMI2_DUAL_1_BASE + 0xF2)
#define REG_HDMI2_DUAL_1_79_H       (REG_HDMI2_DUAL_1_BASE + 0xF3)
#define REG_HDMI2_DUAL_1_7A_L       (REG_HDMI2_DUAL_1_BASE + 0xF4)
#define REG_HDMI2_DUAL_1_7A_H       (REG_HDMI2_DUAL_1_BASE + 0xF5)
#define REG_HDMI2_DUAL_1_7B_L       (REG_HDMI2_DUAL_1_BASE + 0xF6)
#define REG_HDMI2_DUAL_1_7B_H       (REG_HDMI2_DUAL_1_BASE + 0xF7)
#define REG_HDMI2_DUAL_1_7C_L       (REG_HDMI2_DUAL_1_BASE + 0xF8)
#define REG_HDMI2_DUAL_1_7C_H       (REG_HDMI2_DUAL_1_BASE + 0xF9)
#define REG_HDMI2_DUAL_1_7D_L       (REG_HDMI2_DUAL_1_BASE + 0xFA)
#define REG_HDMI2_DUAL_1_7D_H       (REG_HDMI2_DUAL_1_BASE + 0xFB)
#define REG_HDMI2_DUAL_1_7E_L       (REG_HDMI2_DUAL_1_BASE + 0xFC)
#define REG_HDMI2_DUAL_1_7E_H       (REG_HDMI2_DUAL_1_BASE + 0xFD)
#define REG_HDMI2_DUAL_1_7F_L       (REG_HDMI2_DUAL_1_BASE + 0xFE)
#define REG_HDMI2_DUAL_1_7F_H       (REG_HDMI2_DUAL_1_BASE + 0xFF)

// HDMI3_DUAL_1
#define REG_HDMI3_DUAL_1_00_L       (REG_HDMI3_DUAL_1_BASE + 0x00)
#define REG_HDMI3_DUAL_1_00_H       (REG_HDMI3_DUAL_1_BASE + 0x01)
#define REG_HDMI3_DUAL_1_01_L       (REG_HDMI3_DUAL_1_BASE + 0x02)
#define REG_HDMI3_DUAL_1_01_H       (REG_HDMI3_DUAL_1_BASE + 0x03)
#define REG_HDMI3_DUAL_1_02_L       (REG_HDMI3_DUAL_1_BASE + 0x04)
#define REG_HDMI3_DUAL_1_02_H       (REG_HDMI3_DUAL_1_BASE + 0x05)
#define REG_HDMI3_DUAL_1_03_L       (REG_HDMI3_DUAL_1_BASE + 0x06)
#define REG_HDMI3_DUAL_1_03_H       (REG_HDMI3_DUAL_1_BASE + 0x07)
#define REG_HDMI3_DUAL_1_04_L       (REG_HDMI3_DUAL_1_BASE + 0x08)
#define REG_HDMI3_DUAL_1_04_H       (REG_HDMI3_DUAL_1_BASE + 0x09)
#define REG_HDMI3_DUAL_1_05_L       (REG_HDMI3_DUAL_1_BASE + 0x0A)
#define REG_HDMI3_DUAL_1_05_H       (REG_HDMI3_DUAL_1_BASE + 0x0B)
#define REG_HDMI3_DUAL_1_06_L       (REG_HDMI3_DUAL_1_BASE + 0x0C)
#define REG_HDMI3_DUAL_1_06_H       (REG_HDMI3_DUAL_1_BASE + 0x0D)
#define REG_HDMI3_DUAL_1_07_L       (REG_HDMI3_DUAL_1_BASE + 0x0E)
#define REG_HDMI3_DUAL_1_07_H       (REG_HDMI3_DUAL_1_BASE + 0x0F)
#define REG_HDMI3_DUAL_1_08_L       (REG_HDMI3_DUAL_1_BASE + 0x10)
#define REG_HDMI3_DUAL_1_08_H       (REG_HDMI3_DUAL_1_BASE + 0x11)
#define REG_HDMI3_DUAL_1_09_L       (REG_HDMI3_DUAL_1_BASE + 0x12)
#define REG_HDMI3_DUAL_1_09_H       (REG_HDMI3_DUAL_1_BASE + 0x13)
#define REG_HDMI3_DUAL_1_0A_L       (REG_HDMI3_DUAL_1_BASE + 0x14)
#define REG_HDMI3_DUAL_1_0A_H       (REG_HDMI3_DUAL_1_BASE + 0x15)
#define REG_HDMI3_DUAL_1_0B_L       (REG_HDMI3_DUAL_1_BASE + 0x16)
#define REG_HDMI3_DUAL_1_0B_H       (REG_HDMI3_DUAL_1_BASE + 0x17)
#define REG_HDMI3_DUAL_1_0C_L       (REG_HDMI3_DUAL_1_BASE + 0x18)
#define REG_HDMI3_DUAL_1_0C_H       (REG_HDMI3_DUAL_1_BASE + 0x19)
#define REG_HDMI3_DUAL_1_0D_L       (REG_HDMI3_DUAL_1_BASE + 0x1A)
#define REG_HDMI3_DUAL_1_0D_H       (REG_HDMI3_DUAL_1_BASE + 0x1B)
#define REG_HDMI3_DUAL_1_0E_L       (REG_HDMI3_DUAL_1_BASE + 0x1C)
#define REG_HDMI3_DUAL_1_0E_H       (REG_HDMI3_DUAL_1_BASE + 0x1D)
#define REG_HDMI3_DUAL_1_0F_L       (REG_HDMI3_DUAL_1_BASE + 0x1E)
#define REG_HDMI3_DUAL_1_0F_H       (REG_HDMI3_DUAL_1_BASE + 0x1F)
#define REG_HDMI3_DUAL_1_10_L       (REG_HDMI3_DUAL_1_BASE + 0x20)
#define REG_HDMI3_DUAL_1_10_H       (REG_HDMI3_DUAL_1_BASE + 0x21)
#define REG_HDMI3_DUAL_1_11_L       (REG_HDMI3_DUAL_1_BASE + 0x22)
#define REG_HDMI3_DUAL_1_11_H       (REG_HDMI3_DUAL_1_BASE + 0x23)
#define REG_HDMI3_DUAL_1_12_L       (REG_HDMI3_DUAL_1_BASE + 0x24)
#define REG_HDMI3_DUAL_1_12_H       (REG_HDMI3_DUAL_1_BASE + 0x25)
#define REG_HDMI3_DUAL_1_13_L       (REG_HDMI3_DUAL_1_BASE + 0x26)
#define REG_HDMI3_DUAL_1_13_H       (REG_HDMI3_DUAL_1_BASE + 0x27)
#define REG_HDMI3_DUAL_1_14_L       (REG_HDMI3_DUAL_1_BASE + 0x28)
#define REG_HDMI3_DUAL_1_14_H       (REG_HDMI3_DUAL_1_BASE + 0x29)
#define REG_HDMI3_DUAL_1_15_L       (REG_HDMI3_DUAL_1_BASE + 0x2A)
#define REG_HDMI3_DUAL_1_15_H       (REG_HDMI3_DUAL_1_BASE + 0x2B)
#define REG_HDMI3_DUAL_1_16_L       (REG_HDMI3_DUAL_1_BASE + 0x2C)
#define REG_HDMI3_DUAL_1_16_H       (REG_HDMI3_DUAL_1_BASE + 0x2D)
#define REG_HDMI3_DUAL_1_17_L       (REG_HDMI3_DUAL_1_BASE + 0x2E)
#define REG_HDMI3_DUAL_1_17_H       (REG_HDMI3_DUAL_1_BASE + 0x2F)
#define REG_HDMI3_DUAL_1_18_L       (REG_HDMI3_DUAL_1_BASE + 0x30)
#define REG_HDMI3_DUAL_1_18_H       (REG_HDMI3_DUAL_1_BASE + 0x31)
#define REG_HDMI3_DUAL_1_19_L       (REG_HDMI3_DUAL_1_BASE + 0x32)
#define REG_HDMI3_DUAL_1_19_H       (REG_HDMI3_DUAL_1_BASE + 0x33)
#define REG_HDMI3_DUAL_1_1A_L       (REG_HDMI3_DUAL_1_BASE + 0x34)
#define REG_HDMI3_DUAL_1_1A_H       (REG_HDMI3_DUAL_1_BASE + 0x35)
#define REG_HDMI3_DUAL_1_1B_L       (REG_HDMI3_DUAL_1_BASE + 0x36)
#define REG_HDMI3_DUAL_1_1B_H       (REG_HDMI3_DUAL_1_BASE + 0x37)
#define REG_HDMI3_DUAL_1_1C_L       (REG_HDMI3_DUAL_1_BASE + 0x38)
#define REG_HDMI3_DUAL_1_1C_H       (REG_HDMI3_DUAL_1_BASE + 0x39)
#define REG_HDMI3_DUAL_1_1D_L       (REG_HDMI3_DUAL_1_BASE + 0x3A)
#define REG_HDMI3_DUAL_1_1D_H       (REG_HDMI3_DUAL_1_BASE + 0x3B)
#define REG_HDMI3_DUAL_1_1E_L       (REG_HDMI3_DUAL_1_BASE + 0x3C)
#define REG_HDMI3_DUAL_1_1E_H       (REG_HDMI3_DUAL_1_BASE + 0x3D)
#define REG_HDMI3_DUAL_1_1F_L       (REG_HDMI3_DUAL_1_BASE + 0x3E)
#define REG_HDMI3_DUAL_1_1F_H       (REG_HDMI3_DUAL_1_BASE + 0x3F)
#define REG_HDMI3_DUAL_1_20_L       (REG_HDMI3_DUAL_1_BASE + 0x40)
#define REG_HDMI3_DUAL_1_20_H       (REG_HDMI3_DUAL_1_BASE + 0x41)
#define REG_HDMI3_DUAL_1_21_L       (REG_HDMI3_DUAL_1_BASE + 0x42)
#define REG_HDMI3_DUAL_1_21_H       (REG_HDMI3_DUAL_1_BASE + 0x43)
#define REG_HDMI3_DUAL_1_22_L       (REG_HDMI3_DUAL_1_BASE + 0x44)
#define REG_HDMI3_DUAL_1_22_H       (REG_HDMI3_DUAL_1_BASE + 0x45)
#define REG_HDMI3_DUAL_1_23_L       (REG_HDMI3_DUAL_1_BASE + 0x46)
#define REG_HDMI3_DUAL_1_23_H       (REG_HDMI3_DUAL_1_BASE + 0x47)
#define REG_HDMI3_DUAL_1_24_L       (REG_HDMI3_DUAL_1_BASE + 0x48)
#define REG_HDMI3_DUAL_1_24_H       (REG_HDMI3_DUAL_1_BASE + 0x49)
#define REG_HDMI3_DUAL_1_25_L       (REG_HDMI3_DUAL_1_BASE + 0x4A)
#define REG_HDMI3_DUAL_1_25_H       (REG_HDMI3_DUAL_1_BASE + 0x4B)
#define REG_HDMI3_DUAL_1_26_L       (REG_HDMI3_DUAL_1_BASE + 0x4C)
#define REG_HDMI3_DUAL_1_26_H       (REG_HDMI3_DUAL_1_BASE + 0x4D)
#define REG_HDMI3_DUAL_1_27_L       (REG_HDMI3_DUAL_1_BASE + 0x4E)
#define REG_HDMI3_DUAL_1_27_H       (REG_HDMI3_DUAL_1_BASE + 0x4F)
#define REG_HDMI3_DUAL_1_28_L       (REG_HDMI3_DUAL_1_BASE + 0x50)
#define REG_HDMI3_DUAL_1_28_H       (REG_HDMI3_DUAL_1_BASE + 0x51)
#define REG_HDMI3_DUAL_1_29_L       (REG_HDMI3_DUAL_1_BASE + 0x52)
#define REG_HDMI3_DUAL_1_29_H       (REG_HDMI3_DUAL_1_BASE + 0x53)
#define REG_HDMI3_DUAL_1_2A_L       (REG_HDMI3_DUAL_1_BASE + 0x54)
#define REG_HDMI3_DUAL_1_2A_H       (REG_HDMI3_DUAL_1_BASE + 0x55)
#define REG_HDMI3_DUAL_1_2B_L       (REG_HDMI3_DUAL_1_BASE + 0x56)
#define REG_HDMI3_DUAL_1_2B_H       (REG_HDMI3_DUAL_1_BASE + 0x57)
#define REG_HDMI3_DUAL_1_2C_L       (REG_HDMI3_DUAL_1_BASE + 0x58)
#define REG_HDMI3_DUAL_1_2C_H       (REG_HDMI3_DUAL_1_BASE + 0x59)
#define REG_HDMI3_DUAL_1_2D_L       (REG_HDMI3_DUAL_1_BASE + 0x5A)
#define REG_HDMI3_DUAL_1_2D_H       (REG_HDMI3_DUAL_1_BASE + 0x5B)
#define REG_HDMI3_DUAL_1_2E_L       (REG_HDMI3_DUAL_1_BASE + 0x5C)
#define REG_HDMI3_DUAL_1_2E_H       (REG_HDMI3_DUAL_1_BASE + 0x5D)
#define REG_HDMI3_DUAL_1_2F_L       (REG_HDMI3_DUAL_1_BASE + 0x5E)
#define REG_HDMI3_DUAL_1_2F_H       (REG_HDMI3_DUAL_1_BASE + 0x5F)
#define REG_HDMI3_DUAL_1_30_L       (REG_HDMI3_DUAL_1_BASE + 0x60)
#define REG_HDMI3_DUAL_1_30_H       (REG_HDMI3_DUAL_1_BASE + 0x61)
#define REG_HDMI3_DUAL_1_31_L       (REG_HDMI3_DUAL_1_BASE + 0x62)
#define REG_HDMI3_DUAL_1_31_H       (REG_HDMI3_DUAL_1_BASE + 0x63)
#define REG_HDMI3_DUAL_1_32_L       (REG_HDMI3_DUAL_1_BASE + 0x64)
#define REG_HDMI3_DUAL_1_32_H       (REG_HDMI3_DUAL_1_BASE + 0x65)
#define REG_HDMI3_DUAL_1_33_L       (REG_HDMI3_DUAL_1_BASE + 0x66)
#define REG_HDMI3_DUAL_1_33_H       (REG_HDMI3_DUAL_1_BASE + 0x67)
#define REG_HDMI3_DUAL_1_34_L       (REG_HDMI3_DUAL_1_BASE + 0x68)
#define REG_HDMI3_DUAL_1_34_H       (REG_HDMI3_DUAL_1_BASE + 0x69)
#define REG_HDMI3_DUAL_1_35_L       (REG_HDMI3_DUAL_1_BASE + 0x6A)
#define REG_HDMI3_DUAL_1_35_H       (REG_HDMI3_DUAL_1_BASE + 0x6B)
#define REG_HDMI3_DUAL_1_36_L       (REG_HDMI3_DUAL_1_BASE + 0x6C)
#define REG_HDMI3_DUAL_1_36_H       (REG_HDMI3_DUAL_1_BASE + 0x6D)
#define REG_HDMI3_DUAL_1_37_L       (REG_HDMI3_DUAL_1_BASE + 0x6E)
#define REG_HDMI3_DUAL_1_37_H       (REG_HDMI3_DUAL_1_BASE + 0x6F)
#define REG_HDMI3_DUAL_1_38_L       (REG_HDMI3_DUAL_1_BASE + 0x70)
#define REG_HDMI3_DUAL_1_38_H       (REG_HDMI3_DUAL_1_BASE + 0x71)
#define REG_HDMI3_DUAL_1_39_L       (REG_HDMI3_DUAL_1_BASE + 0x72)
#define REG_HDMI3_DUAL_1_39_H       (REG_HDMI3_DUAL_1_BASE + 0x73)
#define REG_HDMI3_DUAL_1_3A_L       (REG_HDMI3_DUAL_1_BASE + 0x74)
#define REG_HDMI3_DUAL_1_3A_H       (REG_HDMI3_DUAL_1_BASE + 0x75)
#define REG_HDMI3_DUAL_1_3B_L       (REG_HDMI3_DUAL_1_BASE + 0x76)
#define REG_HDMI3_DUAL_1_3B_H       (REG_HDMI3_DUAL_1_BASE + 0x77)
#define REG_HDMI3_DUAL_1_3C_L       (REG_HDMI3_DUAL_1_BASE + 0x78)
#define REG_HDMI3_DUAL_1_3C_H       (REG_HDMI3_DUAL_1_BASE + 0x79)
#define REG_HDMI3_DUAL_1_3D_L       (REG_HDMI3_DUAL_1_BASE + 0x7A)
#define REG_HDMI3_DUAL_1_3D_H       (REG_HDMI3_DUAL_1_BASE + 0x7B)
#define REG_HDMI3_DUAL_1_3E_L       (REG_HDMI3_DUAL_1_BASE + 0x7C)
#define REG_HDMI3_DUAL_1_3E_H       (REG_HDMI3_DUAL_1_BASE + 0x7D)
#define REG_HDMI3_DUAL_1_3F_L       (REG_HDMI3_DUAL_1_BASE + 0x7E)
#define REG_HDMI3_DUAL_1_3F_H       (REG_HDMI3_DUAL_1_BASE + 0x7F)
#define REG_HDMI3_DUAL_1_40_L       (REG_HDMI3_DUAL_1_BASE + 0x80)
#define REG_HDMI3_DUAL_1_40_H       (REG_HDMI3_DUAL_1_BASE + 0x81)
#define REG_HDMI3_DUAL_1_41_L       (REG_HDMI3_DUAL_1_BASE + 0x82)
#define REG_HDMI3_DUAL_1_41_H       (REG_HDMI3_DUAL_1_BASE + 0x83)
#define REG_HDMI3_DUAL_1_42_L       (REG_HDMI3_DUAL_1_BASE + 0x84)
#define REG_HDMI3_DUAL_1_42_H       (REG_HDMI3_DUAL_1_BASE + 0x85)
#define REG_HDMI3_DUAL_1_43_L       (REG_HDMI3_DUAL_1_BASE + 0x86)
#define REG_HDMI3_DUAL_1_43_H       (REG_HDMI3_DUAL_1_BASE + 0x87)
#define REG_HDMI3_DUAL_1_44_L       (REG_HDMI3_DUAL_1_BASE + 0x88)
#define REG_HDMI3_DUAL_1_44_H       (REG_HDMI3_DUAL_1_BASE + 0x89)
#define REG_HDMI3_DUAL_1_45_L       (REG_HDMI3_DUAL_1_BASE + 0x8A)
#define REG_HDMI3_DUAL_1_45_H       (REG_HDMI3_DUAL_1_BASE + 0x8B)
#define REG_HDMI3_DUAL_1_46_L       (REG_HDMI3_DUAL_1_BASE + 0x8C)
#define REG_HDMI3_DUAL_1_46_H       (REG_HDMI3_DUAL_1_BASE + 0x8D)
#define REG_HDMI3_DUAL_1_47_L       (REG_HDMI3_DUAL_1_BASE + 0x8E)
#define REG_HDMI3_DUAL_1_47_H       (REG_HDMI3_DUAL_1_BASE + 0x8F)
#define REG_HDMI3_DUAL_1_48_L       (REG_HDMI3_DUAL_1_BASE + 0x90)
#define REG_HDMI3_DUAL_1_48_H       (REG_HDMI3_DUAL_1_BASE + 0x91)
#define REG_HDMI3_DUAL_1_49_L       (REG_HDMI3_DUAL_1_BASE + 0x92)
#define REG_HDMI3_DUAL_1_49_H       (REG_HDMI3_DUAL_1_BASE + 0x93)
#define REG_HDMI3_DUAL_1_4A_L       (REG_HDMI3_DUAL_1_BASE + 0x94)
#define REG_HDMI3_DUAL_1_4A_H       (REG_HDMI3_DUAL_1_BASE + 0x95)
#define REG_HDMI3_DUAL_1_4B_L       (REG_HDMI3_DUAL_1_BASE + 0x96)
#define REG_HDMI3_DUAL_1_4B_H       (REG_HDMI3_DUAL_1_BASE + 0x97)
#define REG_HDMI3_DUAL_1_4C_L       (REG_HDMI3_DUAL_1_BASE + 0x98)
#define REG_HDMI3_DUAL_1_4C_H       (REG_HDMI3_DUAL_1_BASE + 0x99)
#define REG_HDMI3_DUAL_1_4D_L       (REG_HDMI3_DUAL_1_BASE + 0x9A)
#define REG_HDMI3_DUAL_1_4D_H       (REG_HDMI3_DUAL_1_BASE + 0x9B)
#define REG_HDMI3_DUAL_1_4E_L       (REG_HDMI3_DUAL_1_BASE + 0x9C)
#define REG_HDMI3_DUAL_1_4E_H       (REG_HDMI3_DUAL_1_BASE + 0x9D)
#define REG_HDMI3_DUAL_1_4F_L       (REG_HDMI3_DUAL_1_BASE + 0x9E)
#define REG_HDMI3_DUAL_1_4F_H       (REG_HDMI3_DUAL_1_BASE + 0x9F)
#define REG_HDMI3_DUAL_1_50_L       (REG_HDMI3_DUAL_1_BASE + 0xA0)
#define REG_HDMI3_DUAL_1_50_H       (REG_HDMI3_DUAL_1_BASE + 0xA1)
#define REG_HDMI3_DUAL_1_51_L       (REG_HDMI3_DUAL_1_BASE + 0xA2)
#define REG_HDMI3_DUAL_1_51_H       (REG_HDMI3_DUAL_1_BASE + 0xA3)
#define REG_HDMI3_DUAL_1_52_L       (REG_HDMI3_DUAL_1_BASE + 0xA4)
#define REG_HDMI3_DUAL_1_52_H       (REG_HDMI3_DUAL_1_BASE + 0xA5)
#define REG_HDMI3_DUAL_1_53_L       (REG_HDMI3_DUAL_1_BASE + 0xA6)
#define REG_HDMI3_DUAL_1_53_H       (REG_HDMI3_DUAL_1_BASE + 0xA7)
#define REG_HDMI3_DUAL_1_54_L       (REG_HDMI3_DUAL_1_BASE + 0xA8)
#define REG_HDMI3_DUAL_1_54_H       (REG_HDMI3_DUAL_1_BASE + 0xA9)
#define REG_HDMI3_DUAL_1_55_L       (REG_HDMI3_DUAL_1_BASE + 0xAA)
#define REG_HDMI3_DUAL_1_55_H       (REG_HDMI3_DUAL_1_BASE + 0xAB)
#define REG_HDMI3_DUAL_1_56_L       (REG_HDMI3_DUAL_1_BASE + 0xAC)
#define REG_HDMI3_DUAL_1_56_H       (REG_HDMI3_DUAL_1_BASE + 0xAD)
#define REG_HDMI3_DUAL_1_57_L       (REG_HDMI3_DUAL_1_BASE + 0xAE)
#define REG_HDMI3_DUAL_1_57_H       (REG_HDMI3_DUAL_1_BASE + 0xAF)
#define REG_HDMI3_DUAL_1_58_L       (REG_HDMI3_DUAL_1_BASE + 0xB0)
#define REG_HDMI3_DUAL_1_58_H       (REG_HDMI3_DUAL_1_BASE + 0xB1)
#define REG_HDMI3_DUAL_1_59_L       (REG_HDMI3_DUAL_1_BASE + 0xB2)
#define REG_HDMI3_DUAL_1_59_H       (REG_HDMI3_DUAL_1_BASE + 0xB3)
#define REG_HDMI3_DUAL_1_5A_L       (REG_HDMI3_DUAL_1_BASE + 0xB4)
#define REG_HDMI3_DUAL_1_5A_H       (REG_HDMI3_DUAL_1_BASE + 0xB5)
#define REG_HDMI3_DUAL_1_5B_L       (REG_HDMI3_DUAL_1_BASE + 0xB6)
#define REG_HDMI3_DUAL_1_5B_H       (REG_HDMI3_DUAL_1_BASE + 0xB7)
#define REG_HDMI3_DUAL_1_5C_L       (REG_HDMI3_DUAL_1_BASE + 0xB8)
#define REG_HDMI3_DUAL_1_5C_H       (REG_HDMI3_DUAL_1_BASE + 0xB9)
#define REG_HDMI3_DUAL_1_5D_L       (REG_HDMI3_DUAL_1_BASE + 0xBA)
#define REG_HDMI3_DUAL_1_5D_H       (REG_HDMI3_DUAL_1_BASE + 0xBB)
#define REG_HDMI3_DUAL_1_5E_L       (REG_HDMI3_DUAL_1_BASE + 0xBC)
#define REG_HDMI3_DUAL_1_5E_H       (REG_HDMI3_DUAL_1_BASE + 0xBD)
#define REG_HDMI3_DUAL_1_5F_L       (REG_HDMI3_DUAL_1_BASE + 0xBE)
#define REG_HDMI3_DUAL_1_5F_H       (REG_HDMI3_DUAL_1_BASE + 0xBF)
#define REG_HDMI3_DUAL_1_60_L       (REG_HDMI3_DUAL_1_BASE + 0xC0)
#define REG_HDMI3_DUAL_1_60_H       (REG_HDMI3_DUAL_1_BASE + 0xC1)
#define REG_HDMI3_DUAL_1_61_L       (REG_HDMI3_DUAL_1_BASE + 0xC2)
#define REG_HDMI3_DUAL_1_61_H       (REG_HDMI3_DUAL_1_BASE + 0xC3)
#define REG_HDMI3_DUAL_1_62_L       (REG_HDMI3_DUAL_1_BASE + 0xC4)
#define REG_HDMI3_DUAL_1_62_H       (REG_HDMI3_DUAL_1_BASE + 0xC5)
#define REG_HDMI3_DUAL_1_63_L       (REG_HDMI3_DUAL_1_BASE + 0xC6)
#define REG_HDMI3_DUAL_1_63_H       (REG_HDMI3_DUAL_1_BASE + 0xC7)
#define REG_HDMI3_DUAL_1_64_L       (REG_HDMI3_DUAL_1_BASE + 0xC8)
#define REG_HDMI3_DUAL_1_64_H       (REG_HDMI3_DUAL_1_BASE + 0xC9)
#define REG_HDMI3_DUAL_1_65_L       (REG_HDMI3_DUAL_1_BASE + 0xCA)
#define REG_HDMI3_DUAL_1_65_H       (REG_HDMI3_DUAL_1_BASE + 0xCB)
#define REG_HDMI3_DUAL_1_66_L       (REG_HDMI3_DUAL_1_BASE + 0xCC)
#define REG_HDMI3_DUAL_1_66_H       (REG_HDMI3_DUAL_1_BASE + 0xCD)
#define REG_HDMI3_DUAL_1_67_L       (REG_HDMI3_DUAL_1_BASE + 0xCE)
#define REG_HDMI3_DUAL_1_67_H       (REG_HDMI3_DUAL_1_BASE + 0xCF)
#define REG_HDMI3_DUAL_1_68_L       (REG_HDMI3_DUAL_1_BASE + 0xD0)
#define REG_HDMI3_DUAL_1_68_H       (REG_HDMI3_DUAL_1_BASE + 0xD1)
#define REG_HDMI3_DUAL_1_69_L       (REG_HDMI3_DUAL_1_BASE + 0xD2)
#define REG_HDMI3_DUAL_1_69_H       (REG_HDMI3_DUAL_1_BASE + 0xD3)
#define REG_HDMI3_DUAL_1_6A_L       (REG_HDMI3_DUAL_1_BASE + 0xD4)
#define REG_HDMI3_DUAL_1_6A_H       (REG_HDMI3_DUAL_1_BASE + 0xD5)
#define REG_HDMI3_DUAL_1_6B_L       (REG_HDMI3_DUAL_1_BASE + 0xD6)
#define REG_HDMI3_DUAL_1_6B_H       (REG_HDMI3_DUAL_1_BASE + 0xD7)
#define REG_HDMI3_DUAL_1_6C_L       (REG_HDMI3_DUAL_1_BASE + 0xD8)
#define REG_HDMI3_DUAL_1_6C_H       (REG_HDMI3_DUAL_1_BASE + 0xD9)
#define REG_HDMI3_DUAL_1_6D_L       (REG_HDMI3_DUAL_1_BASE + 0xDA)
#define REG_HDMI3_DUAL_1_6D_H       (REG_HDMI3_DUAL_1_BASE + 0xDB)
#define REG_HDMI3_DUAL_1_6E_L       (REG_HDMI3_DUAL_1_BASE + 0xDC)
#define REG_HDMI3_DUAL_1_6E_H       (REG_HDMI3_DUAL_1_BASE + 0xDD)
#define REG_HDMI3_DUAL_1_6F_L       (REG_HDMI3_DUAL_1_BASE + 0xDE)
#define REG_HDMI3_DUAL_1_6F_H       (REG_HDMI3_DUAL_1_BASE + 0xDF)
#define REG_HDMI3_DUAL_1_70_L       (REG_HDMI3_DUAL_1_BASE + 0xE0)
#define REG_HDMI3_DUAL_1_70_H       (REG_HDMI3_DUAL_1_BASE + 0xE1)
#define REG_HDMI3_DUAL_1_71_L       (REG_HDMI3_DUAL_1_BASE + 0xE2)
#define REG_HDMI3_DUAL_1_71_H       (REG_HDMI3_DUAL_1_BASE + 0xE3)
#define REG_HDMI3_DUAL_1_72_L       (REG_HDMI3_DUAL_1_BASE + 0xE4)
#define REG_HDMI3_DUAL_1_72_H       (REG_HDMI3_DUAL_1_BASE + 0xE5)
#define REG_HDMI3_DUAL_1_73_L       (REG_HDMI3_DUAL_1_BASE + 0xE6)
#define REG_HDMI3_DUAL_1_73_H       (REG_HDMI3_DUAL_1_BASE + 0xE7)
#define REG_HDMI3_DUAL_1_74_L       (REG_HDMI3_DUAL_1_BASE + 0xE8)
#define REG_HDMI3_DUAL_1_74_H       (REG_HDMI3_DUAL_1_BASE + 0xE9)
#define REG_HDMI3_DUAL_1_75_L       (REG_HDMI3_DUAL_1_BASE + 0xEA)
#define REG_HDMI3_DUAL_1_75_H       (REG_HDMI3_DUAL_1_BASE + 0xEB)
#define REG_HDMI3_DUAL_1_76_L       (REG_HDMI3_DUAL_1_BASE + 0xEC)
#define REG_HDMI3_DUAL_1_76_H       (REG_HDMI3_DUAL_1_BASE + 0xED)
#define REG_HDMI3_DUAL_1_77_L       (REG_HDMI3_DUAL_1_BASE + 0xEE)
#define REG_HDMI3_DUAL_1_77_H       (REG_HDMI3_DUAL_1_BASE + 0xEF)
#define REG_HDMI3_DUAL_1_78_L       (REG_HDMI3_DUAL_1_BASE + 0xF0)
#define REG_HDMI3_DUAL_1_78_H       (REG_HDMI3_DUAL_1_BASE + 0xF1)
#define REG_HDMI3_DUAL_1_79_L       (REG_HDMI3_DUAL_1_BASE + 0xF2)
#define REG_HDMI3_DUAL_1_79_H       (REG_HDMI3_DUAL_1_BASE + 0xF3)
#define REG_HDMI3_DUAL_1_7A_L       (REG_HDMI3_DUAL_1_BASE + 0xF4)
#define REG_HDMI3_DUAL_1_7A_H       (REG_HDMI3_DUAL_1_BASE + 0xF5)
#define REG_HDMI3_DUAL_1_7B_L       (REG_HDMI3_DUAL_1_BASE + 0xF6)
#define REG_HDMI3_DUAL_1_7B_H       (REG_HDMI3_DUAL_1_BASE + 0xF7)
#define REG_HDMI3_DUAL_1_7C_L       (REG_HDMI3_DUAL_1_BASE + 0xF8)
#define REG_HDMI3_DUAL_1_7C_H       (REG_HDMI3_DUAL_1_BASE + 0xF9)
#define REG_HDMI3_DUAL_1_7D_L       (REG_HDMI3_DUAL_1_BASE + 0xFA)
#define REG_HDMI3_DUAL_1_7D_H       (REG_HDMI3_DUAL_1_BASE + 0xFB)
#define REG_HDMI3_DUAL_1_7E_L       (REG_HDMI3_DUAL_1_BASE + 0xFC)
#define REG_HDMI3_DUAL_1_7E_H       (REG_HDMI3_DUAL_1_BASE + 0xFD)
#define REG_HDMI3_DUAL_1_7F_L       (REG_HDMI3_DUAL_1_BASE + 0xFE)
#define REG_HDMI3_DUAL_1_7F_H       (REG_HDMI3_DUAL_1_BASE + 0xFF)

//=============================================================
// COMBO_GP_TOP
#define REG_COMBO_GP_TOP_00_L       (REG_COMBO_GP_TOP_BASE + 0x00)
#define REG_COMBO_GP_TOP_00_H       (REG_COMBO_GP_TOP_BASE + 0x01)
#define REG_COMBO_GP_TOP_01_L       (REG_COMBO_GP_TOP_BASE + 0x02)
#define REG_COMBO_GP_TOP_01_H       (REG_COMBO_GP_TOP_BASE + 0x03)
#define REG_COMBO_GP_TOP_02_L       (REG_COMBO_GP_TOP_BASE + 0x04)
#define REG_COMBO_GP_TOP_02_H       (REG_COMBO_GP_TOP_BASE + 0x05)
#define REG_COMBO_GP_TOP_03_L       (REG_COMBO_GP_TOP_BASE + 0x06)
#define REG_COMBO_GP_TOP_03_H       (REG_COMBO_GP_TOP_BASE + 0x07)
#define REG_COMBO_GP_TOP_04_L       (REG_COMBO_GP_TOP_BASE + 0x08)
#define REG_COMBO_GP_TOP_04_H       (REG_COMBO_GP_TOP_BASE + 0x09)
#define REG_COMBO_GP_TOP_05_L       (REG_COMBO_GP_TOP_BASE + 0x0A)
#define REG_COMBO_GP_TOP_05_H       (REG_COMBO_GP_TOP_BASE + 0x0B)
#define REG_COMBO_GP_TOP_06_L       (REG_COMBO_GP_TOP_BASE + 0x0C)
#define REG_COMBO_GP_TOP_06_H       (REG_COMBO_GP_TOP_BASE + 0x0D)
#define REG_COMBO_GP_TOP_07_L       (REG_COMBO_GP_TOP_BASE + 0x0E)
#define REG_COMBO_GP_TOP_07_H       (REG_COMBO_GP_TOP_BASE + 0x0F)
#define REG_COMBO_GP_TOP_08_L       (REG_COMBO_GP_TOP_BASE + 0x10)
#define REG_COMBO_GP_TOP_08_H       (REG_COMBO_GP_TOP_BASE + 0x11)
#define REG_COMBO_GP_TOP_09_L       (REG_COMBO_GP_TOP_BASE + 0x12)
#define REG_COMBO_GP_TOP_09_H       (REG_COMBO_GP_TOP_BASE + 0x13)
#define REG_COMBO_GP_TOP_0A_L       (REG_COMBO_GP_TOP_BASE + 0x14)
#define REG_COMBO_GP_TOP_0A_H       (REG_COMBO_GP_TOP_BASE + 0x15)
#define REG_COMBO_GP_TOP_0B_L       (REG_COMBO_GP_TOP_BASE + 0x16)
#define REG_COMBO_GP_TOP_0B_H       (REG_COMBO_GP_TOP_BASE + 0x17)
#define REG_COMBO_GP_TOP_0C_L       (REG_COMBO_GP_TOP_BASE + 0x18)
#define REG_COMBO_GP_TOP_0C_H       (REG_COMBO_GP_TOP_BASE + 0x19)
#define REG_COMBO_GP_TOP_0D_L       (REG_COMBO_GP_TOP_BASE + 0x1A)
#define REG_COMBO_GP_TOP_0D_H       (REG_COMBO_GP_TOP_BASE + 0x1B)
#define REG_COMBO_GP_TOP_0E_L       (REG_COMBO_GP_TOP_BASE + 0x1C)
#define REG_COMBO_GP_TOP_0E_H       (REG_COMBO_GP_TOP_BASE + 0x1D)
#define REG_COMBO_GP_TOP_0F_L       (REG_COMBO_GP_TOP_BASE + 0x1E)
#define REG_COMBO_GP_TOP_0F_H       (REG_COMBO_GP_TOP_BASE + 0x1F)
#define REG_COMBO_GP_TOP_10_L       (REG_COMBO_GP_TOP_BASE + 0x20)
#define REG_COMBO_GP_TOP_10_H       (REG_COMBO_GP_TOP_BASE + 0x21)
#define REG_COMBO_GP_TOP_11_L       (REG_COMBO_GP_TOP_BASE + 0x22)
#define REG_COMBO_GP_TOP_11_H       (REG_COMBO_GP_TOP_BASE + 0x23)
#define REG_COMBO_GP_TOP_12_L       (REG_COMBO_GP_TOP_BASE + 0x24)
#define REG_COMBO_GP_TOP_12_H       (REG_COMBO_GP_TOP_BASE + 0x25)
#define REG_COMBO_GP_TOP_13_L       (REG_COMBO_GP_TOP_BASE + 0x26)
#define REG_COMBO_GP_TOP_13_H       (REG_COMBO_GP_TOP_BASE + 0x27)
#define REG_COMBO_GP_TOP_14_L       (REG_COMBO_GP_TOP_BASE + 0x28)
#define REG_COMBO_GP_TOP_14_H       (REG_COMBO_GP_TOP_BASE + 0x29)
#define REG_COMBO_GP_TOP_15_L       (REG_COMBO_GP_TOP_BASE + 0x2A)
#define REG_COMBO_GP_TOP_15_H       (REG_COMBO_GP_TOP_BASE + 0x2B)
#define REG_COMBO_GP_TOP_16_L       (REG_COMBO_GP_TOP_BASE + 0x2C)
#define REG_COMBO_GP_TOP_16_H       (REG_COMBO_GP_TOP_BASE + 0x2D)
#define REG_COMBO_GP_TOP_17_L       (REG_COMBO_GP_TOP_BASE + 0x2E)
#define REG_COMBO_GP_TOP_17_H       (REG_COMBO_GP_TOP_BASE + 0x2F)
#define REG_COMBO_GP_TOP_18_L       (REG_COMBO_GP_TOP_BASE + 0x30)
#define REG_COMBO_GP_TOP_18_H       (REG_COMBO_GP_TOP_BASE + 0x31)
#define REG_COMBO_GP_TOP_19_L       (REG_COMBO_GP_TOP_BASE + 0x32)
#define REG_COMBO_GP_TOP_19_H       (REG_COMBO_GP_TOP_BASE + 0x33)
#define REG_COMBO_GP_TOP_1A_L       (REG_COMBO_GP_TOP_BASE + 0x34)
#define REG_COMBO_GP_TOP_1A_H       (REG_COMBO_GP_TOP_BASE + 0x35)
#define REG_COMBO_GP_TOP_1B_L       (REG_COMBO_GP_TOP_BASE + 0x36)
#define REG_COMBO_GP_TOP_1B_H       (REG_COMBO_GP_TOP_BASE + 0x37)
#define REG_COMBO_GP_TOP_1C_L       (REG_COMBO_GP_TOP_BASE + 0x38)
#define REG_COMBO_GP_TOP_1C_H       (REG_COMBO_GP_TOP_BASE + 0x39)
#define REG_COMBO_GP_TOP_1D_L       (REG_COMBO_GP_TOP_BASE + 0x3A)
#define REG_COMBO_GP_TOP_1D_H       (REG_COMBO_GP_TOP_BASE + 0x3B)
#define REG_COMBO_GP_TOP_1E_L       (REG_COMBO_GP_TOP_BASE + 0x3C)
#define REG_COMBO_GP_TOP_1E_H       (REG_COMBO_GP_TOP_BASE + 0x3D)
#define REG_COMBO_GP_TOP_1F_L       (REG_COMBO_GP_TOP_BASE + 0x3E)
#define REG_COMBO_GP_TOP_1F_H       (REG_COMBO_GP_TOP_BASE + 0x3F)
#define REG_COMBO_GP_TOP_20_L       (REG_COMBO_GP_TOP_BASE + 0x40)
#define REG_COMBO_GP_TOP_20_H       (REG_COMBO_GP_TOP_BASE + 0x41)
#define REG_COMBO_GP_TOP_21_L       (REG_COMBO_GP_TOP_BASE + 0x42)
#define REG_COMBO_GP_TOP_21_H       (REG_COMBO_GP_TOP_BASE + 0x43)
#define REG_COMBO_GP_TOP_22_L       (REG_COMBO_GP_TOP_BASE + 0x44)
#define REG_COMBO_GP_TOP_22_H       (REG_COMBO_GP_TOP_BASE + 0x45)
#define REG_COMBO_GP_TOP_23_L       (REG_COMBO_GP_TOP_BASE + 0x46)
#define REG_COMBO_GP_TOP_23_H       (REG_COMBO_GP_TOP_BASE + 0x47)
#define REG_COMBO_GP_TOP_24_L       (REG_COMBO_GP_TOP_BASE + 0x48)
#define REG_COMBO_GP_TOP_24_H       (REG_COMBO_GP_TOP_BASE + 0x49)
#define REG_COMBO_GP_TOP_25_L       (REG_COMBO_GP_TOP_BASE + 0x4A)
#define REG_COMBO_GP_TOP_25_H       (REG_COMBO_GP_TOP_BASE + 0x4B)
#define REG_COMBO_GP_TOP_26_L       (REG_COMBO_GP_TOP_BASE + 0x4C)
#define REG_COMBO_GP_TOP_26_H       (REG_COMBO_GP_TOP_BASE + 0x4D)
#define REG_COMBO_GP_TOP_27_L       (REG_COMBO_GP_TOP_BASE + 0x4E)
#define REG_COMBO_GP_TOP_27_H       (REG_COMBO_GP_TOP_BASE + 0x4F)
#define REG_COMBO_GP_TOP_28_L       (REG_COMBO_GP_TOP_BASE + 0x50)
#define REG_COMBO_GP_TOP_28_H       (REG_COMBO_GP_TOP_BASE + 0x51)
#define REG_COMBO_GP_TOP_29_L       (REG_COMBO_GP_TOP_BASE + 0x52)
#define REG_COMBO_GP_TOP_29_H       (REG_COMBO_GP_TOP_BASE + 0x53)
#define REG_COMBO_GP_TOP_2A_L       (REG_COMBO_GP_TOP_BASE + 0x54)
#define REG_COMBO_GP_TOP_2A_H       (REG_COMBO_GP_TOP_BASE + 0x55)
#define REG_COMBO_GP_TOP_2B_L       (REG_COMBO_GP_TOP_BASE + 0x56)
#define REG_COMBO_GP_TOP_2B_H       (REG_COMBO_GP_TOP_BASE + 0x57)
#define REG_COMBO_GP_TOP_2C_L       (REG_COMBO_GP_TOP_BASE + 0x58)
#define REG_COMBO_GP_TOP_2C_H       (REG_COMBO_GP_TOP_BASE + 0x59)
#define REG_COMBO_GP_TOP_2D_L       (REG_COMBO_GP_TOP_BASE + 0x5A)
#define REG_COMBO_GP_TOP_2D_H       (REG_COMBO_GP_TOP_BASE + 0x5B)
#define REG_COMBO_GP_TOP_2E_L       (REG_COMBO_GP_TOP_BASE + 0x5C)
#define REG_COMBO_GP_TOP_2E_H       (REG_COMBO_GP_TOP_BASE + 0x5D)
#define REG_COMBO_GP_TOP_2F_L       (REG_COMBO_GP_TOP_BASE + 0x5E)
#define REG_COMBO_GP_TOP_2F_H       (REG_COMBO_GP_TOP_BASE + 0x5F)
#define REG_COMBO_GP_TOP_30_L       (REG_COMBO_GP_TOP_BASE + 0x60)
#define REG_COMBO_GP_TOP_30_H       (REG_COMBO_GP_TOP_BASE + 0x61)
#define REG_COMBO_GP_TOP_31_L       (REG_COMBO_GP_TOP_BASE + 0x62)
#define REG_COMBO_GP_TOP_31_H       (REG_COMBO_GP_TOP_BASE + 0x63)
#define REG_COMBO_GP_TOP_32_L       (REG_COMBO_GP_TOP_BASE + 0x64)
#define REG_COMBO_GP_TOP_32_H       (REG_COMBO_GP_TOP_BASE + 0x65)
#define REG_COMBO_GP_TOP_33_L       (REG_COMBO_GP_TOP_BASE + 0x66)
#define REG_COMBO_GP_TOP_33_H       (REG_COMBO_GP_TOP_BASE + 0x67)
#define REG_COMBO_GP_TOP_34_L       (REG_COMBO_GP_TOP_BASE + 0x68)
#define REG_COMBO_GP_TOP_34_H       (REG_COMBO_GP_TOP_BASE + 0x69)
#define REG_COMBO_GP_TOP_35_L       (REG_COMBO_GP_TOP_BASE + 0x6A)
#define REG_COMBO_GP_TOP_35_H       (REG_COMBO_GP_TOP_BASE + 0x6B)
#define REG_COMBO_GP_TOP_36_L       (REG_COMBO_GP_TOP_BASE + 0x6C)
#define REG_COMBO_GP_TOP_36_H       (REG_COMBO_GP_TOP_BASE + 0x6D)
#define REG_COMBO_GP_TOP_37_L       (REG_COMBO_GP_TOP_BASE + 0x6E)
#define REG_COMBO_GP_TOP_37_H       (REG_COMBO_GP_TOP_BASE + 0x6F)
#define REG_COMBO_GP_TOP_38_L       (REG_COMBO_GP_TOP_BASE + 0x70)
#define REG_COMBO_GP_TOP_38_H       (REG_COMBO_GP_TOP_BASE + 0x71)
#define REG_COMBO_GP_TOP_39_L       (REG_COMBO_GP_TOP_BASE + 0x72)
#define REG_COMBO_GP_TOP_39_H       (REG_COMBO_GP_TOP_BASE + 0x73)
#define REG_COMBO_GP_TOP_3A_L       (REG_COMBO_GP_TOP_BASE + 0x74)
#define REG_COMBO_GP_TOP_3A_H       (REG_COMBO_GP_TOP_BASE + 0x75)
#define REG_COMBO_GP_TOP_3B_L       (REG_COMBO_GP_TOP_BASE + 0x76)
#define REG_COMBO_GP_TOP_3B_H       (REG_COMBO_GP_TOP_BASE + 0x77)
#define REG_COMBO_GP_TOP_3C_L       (REG_COMBO_GP_TOP_BASE + 0x78)
#define REG_COMBO_GP_TOP_3C_H       (REG_COMBO_GP_TOP_BASE + 0x79)
#define REG_COMBO_GP_TOP_3D_L       (REG_COMBO_GP_TOP_BASE + 0x7A)
#define REG_COMBO_GP_TOP_3D_H       (REG_COMBO_GP_TOP_BASE + 0x7B)
#define REG_COMBO_GP_TOP_3E_L       (REG_COMBO_GP_TOP_BASE + 0x7C)
#define REG_COMBO_GP_TOP_3E_H       (REG_COMBO_GP_TOP_BASE + 0x7D)
#define REG_COMBO_GP_TOP_3F_L       (REG_COMBO_GP_TOP_BASE + 0x7E)
#define REG_COMBO_GP_TOP_3F_H       (REG_COMBO_GP_TOP_BASE + 0x7F)
#define REG_COMBO_GP_TOP_40_L       (REG_COMBO_GP_TOP_BASE + 0x80)
#define REG_COMBO_GP_TOP_40_H       (REG_COMBO_GP_TOP_BASE + 0x81)
#define REG_COMBO_GP_TOP_41_L       (REG_COMBO_GP_TOP_BASE + 0x82)
#define REG_COMBO_GP_TOP_41_H       (REG_COMBO_GP_TOP_BASE + 0x83)
#define REG_COMBO_GP_TOP_42_L       (REG_COMBO_GP_TOP_BASE + 0x84)
#define REG_COMBO_GP_TOP_42_H       (REG_COMBO_GP_TOP_BASE + 0x85)
#define REG_COMBO_GP_TOP_43_L       (REG_COMBO_GP_TOP_BASE + 0x86)
#define REG_COMBO_GP_TOP_43_H       (REG_COMBO_GP_TOP_BASE + 0x87)
#define REG_COMBO_GP_TOP_44_L       (REG_COMBO_GP_TOP_BASE + 0x88)
#define REG_COMBO_GP_TOP_44_H       (REG_COMBO_GP_TOP_BASE + 0x89)
#define REG_COMBO_GP_TOP_45_L       (REG_COMBO_GP_TOP_BASE + 0x8A)
#define REG_COMBO_GP_TOP_45_H       (REG_COMBO_GP_TOP_BASE + 0x8B)
#define REG_COMBO_GP_TOP_46_L       (REG_COMBO_GP_TOP_BASE + 0x8C)
#define REG_COMBO_GP_TOP_46_H       (REG_COMBO_GP_TOP_BASE + 0x8D)
#define REG_COMBO_GP_TOP_47_L       (REG_COMBO_GP_TOP_BASE + 0x8E)
#define REG_COMBO_GP_TOP_47_H       (REG_COMBO_GP_TOP_BASE + 0x8F)
#define REG_COMBO_GP_TOP_48_L       (REG_COMBO_GP_TOP_BASE + 0x90)
#define REG_COMBO_GP_TOP_48_H       (REG_COMBO_GP_TOP_BASE + 0x91)
#define REG_COMBO_GP_TOP_49_L       (REG_COMBO_GP_TOP_BASE + 0x92)
#define REG_COMBO_GP_TOP_49_H       (REG_COMBO_GP_TOP_BASE + 0x93)
#define REG_COMBO_GP_TOP_4A_L       (REG_COMBO_GP_TOP_BASE + 0x94)
#define REG_COMBO_GP_TOP_4A_H       (REG_COMBO_GP_TOP_BASE + 0x95)
#define REG_COMBO_GP_TOP_4B_L       (REG_COMBO_GP_TOP_BASE + 0x96)
#define REG_COMBO_GP_TOP_4B_H       (REG_COMBO_GP_TOP_BASE + 0x97)
#define REG_COMBO_GP_TOP_4C_L       (REG_COMBO_GP_TOP_BASE + 0x98)
#define REG_COMBO_GP_TOP_4C_H       (REG_COMBO_GP_TOP_BASE + 0x99)
#define REG_COMBO_GP_TOP_4D_L       (REG_COMBO_GP_TOP_BASE + 0x9A)
#define REG_COMBO_GP_TOP_4D_H       (REG_COMBO_GP_TOP_BASE + 0x9B)
#define REG_COMBO_GP_TOP_4E_L       (REG_COMBO_GP_TOP_BASE + 0x9C)
#define REG_COMBO_GP_TOP_4E_H       (REG_COMBO_GP_TOP_BASE + 0x9D)
#define REG_COMBO_GP_TOP_4F_L       (REG_COMBO_GP_TOP_BASE + 0x9E)
#define REG_COMBO_GP_TOP_4F_H       (REG_COMBO_GP_TOP_BASE + 0x9F)
#define REG_COMBO_GP_TOP_50_L       (REG_COMBO_GP_TOP_BASE + 0xA0)
#define REG_COMBO_GP_TOP_50_H       (REG_COMBO_GP_TOP_BASE + 0xA1)
#define REG_COMBO_GP_TOP_51_L       (REG_COMBO_GP_TOP_BASE + 0xA2)
#define REG_COMBO_GP_TOP_51_H       (REG_COMBO_GP_TOP_BASE + 0xA3)
#define REG_COMBO_GP_TOP_52_L       (REG_COMBO_GP_TOP_BASE + 0xA4)
#define REG_COMBO_GP_TOP_52_H       (REG_COMBO_GP_TOP_BASE + 0xA5)
#define REG_COMBO_GP_TOP_53_L       (REG_COMBO_GP_TOP_BASE + 0xA6)
#define REG_COMBO_GP_TOP_53_H       (REG_COMBO_GP_TOP_BASE + 0xA7)
#define REG_COMBO_GP_TOP_54_L       (REG_COMBO_GP_TOP_BASE + 0xA8)
#define REG_COMBO_GP_TOP_54_H       (REG_COMBO_GP_TOP_BASE + 0xA9)
#define REG_COMBO_GP_TOP_55_L       (REG_COMBO_GP_TOP_BASE + 0xAA)
#define REG_COMBO_GP_TOP_55_H       (REG_COMBO_GP_TOP_BASE + 0xAB)
#define REG_COMBO_GP_TOP_56_L       (REG_COMBO_GP_TOP_BASE + 0xAC)
#define REG_COMBO_GP_TOP_56_H       (REG_COMBO_GP_TOP_BASE + 0xAD)
#define REG_COMBO_GP_TOP_57_L       (REG_COMBO_GP_TOP_BASE + 0xAE)
#define REG_COMBO_GP_TOP_57_H       (REG_COMBO_GP_TOP_BASE + 0xAF)
#define REG_COMBO_GP_TOP_58_L       (REG_COMBO_GP_TOP_BASE + 0xB0)
#define REG_COMBO_GP_TOP_58_H       (REG_COMBO_GP_TOP_BASE + 0xB1)
#define REG_COMBO_GP_TOP_59_L       (REG_COMBO_GP_TOP_BASE + 0xB2)
#define REG_COMBO_GP_TOP_59_H       (REG_COMBO_GP_TOP_BASE + 0xB3)
#define REG_COMBO_GP_TOP_5A_L       (REG_COMBO_GP_TOP_BASE + 0xB4)
#define REG_COMBO_GP_TOP_5A_H       (REG_COMBO_GP_TOP_BASE + 0xB5)
#define REG_COMBO_GP_TOP_5B_L       (REG_COMBO_GP_TOP_BASE + 0xB6)
#define REG_COMBO_GP_TOP_5B_H       (REG_COMBO_GP_TOP_BASE + 0xB7)
#define REG_COMBO_GP_TOP_5C_L       (REG_COMBO_GP_TOP_BASE + 0xB8)
#define REG_COMBO_GP_TOP_5C_H       (REG_COMBO_GP_TOP_BASE + 0xB9)
#define REG_COMBO_GP_TOP_5D_L       (REG_COMBO_GP_TOP_BASE + 0xBA)
#define REG_COMBO_GP_TOP_5D_H       (REG_COMBO_GP_TOP_BASE + 0xBB)
#define REG_COMBO_GP_TOP_5E_L       (REG_COMBO_GP_TOP_BASE + 0xBC)
#define REG_COMBO_GP_TOP_5E_H       (REG_COMBO_GP_TOP_BASE + 0xBD)
#define REG_COMBO_GP_TOP_5F_L       (REG_COMBO_GP_TOP_BASE + 0xBE)
#define REG_COMBO_GP_TOP_5F_H       (REG_COMBO_GP_TOP_BASE + 0xBF)
#define REG_COMBO_GP_TOP_60_L       (REG_COMBO_GP_TOP_BASE + 0xC0)
#define REG_COMBO_GP_TOP_60_H       (REG_COMBO_GP_TOP_BASE + 0xC1)
#define REG_COMBO_GP_TOP_61_L       (REG_COMBO_GP_TOP_BASE + 0xC2)
#define REG_COMBO_GP_TOP_61_H       (REG_COMBO_GP_TOP_BASE + 0xC3)
#define REG_COMBO_GP_TOP_62_L       (REG_COMBO_GP_TOP_BASE + 0xC4)
#define REG_COMBO_GP_TOP_62_H       (REG_COMBO_GP_TOP_BASE + 0xC5)
#define REG_COMBO_GP_TOP_63_L       (REG_COMBO_GP_TOP_BASE + 0xC6)
#define REG_COMBO_GP_TOP_63_H       (REG_COMBO_GP_TOP_BASE + 0xC7)
#define REG_COMBO_GP_TOP_64_L       (REG_COMBO_GP_TOP_BASE + 0xC8)
#define REG_COMBO_GP_TOP_64_H       (REG_COMBO_GP_TOP_BASE + 0xC9)
#define REG_COMBO_GP_TOP_65_L       (REG_COMBO_GP_TOP_BASE + 0xCA)
#define REG_COMBO_GP_TOP_65_H       (REG_COMBO_GP_TOP_BASE + 0xCB)
#define REG_COMBO_GP_TOP_66_L       (REG_COMBO_GP_TOP_BASE + 0xCC)
#define REG_COMBO_GP_TOP_66_H       (REG_COMBO_GP_TOP_BASE + 0xCD)
#define REG_COMBO_GP_TOP_67_L       (REG_COMBO_GP_TOP_BASE + 0xCE)
#define REG_COMBO_GP_TOP_67_H       (REG_COMBO_GP_TOP_BASE + 0xCF)
#define REG_COMBO_GP_TOP_68_L       (REG_COMBO_GP_TOP_BASE + 0xD0)
#define REG_COMBO_GP_TOP_68_H       (REG_COMBO_GP_TOP_BASE + 0xD1)
#define REG_COMBO_GP_TOP_69_L       (REG_COMBO_GP_TOP_BASE + 0xD2)
#define REG_COMBO_GP_TOP_69_H       (REG_COMBO_GP_TOP_BASE + 0xD3)
#define REG_COMBO_GP_TOP_6A_L       (REG_COMBO_GP_TOP_BASE + 0xD4)
#define REG_COMBO_GP_TOP_6A_H       (REG_COMBO_GP_TOP_BASE + 0xD5)
#define REG_COMBO_GP_TOP_6B_L       (REG_COMBO_GP_TOP_BASE + 0xD6)
#define REG_COMBO_GP_TOP_6B_H       (REG_COMBO_GP_TOP_BASE + 0xD7)
#define REG_COMBO_GP_TOP_6C_L       (REG_COMBO_GP_TOP_BASE + 0xD8)
#define REG_COMBO_GP_TOP_6C_H       (REG_COMBO_GP_TOP_BASE + 0xD9)
#define REG_COMBO_GP_TOP_6D_L       (REG_COMBO_GP_TOP_BASE + 0xDA)
#define REG_COMBO_GP_TOP_6D_H       (REG_COMBO_GP_TOP_BASE + 0xDB)
#define REG_COMBO_GP_TOP_6E_L       (REG_COMBO_GP_TOP_BASE + 0xDC)
#define REG_COMBO_GP_TOP_6E_H       (REG_COMBO_GP_TOP_BASE + 0xDD)

//=============================================================
// SECURE_TZPC
#define REG_SECURE_TZPC_00_L        (REG_SECURE_TZPC_BASE + 0x00)
#define REG_SECURE_TZPC_00_H        (REG_SECURE_TZPC_BASE + 0x01)
#define REG_SECURE_TZPC_01_L        (REG_SECURE_TZPC_BASE + 0x02)
#define REG_SECURE_TZPC_01_H        (REG_SECURE_TZPC_BASE + 0x03)
#define REG_SECURE_TZPC_02_L        (REG_SECURE_TZPC_BASE + 0x04)
#define REG_SECURE_TZPC_02_H        (REG_SECURE_TZPC_BASE + 0x05)
#define REG_SECURE_TZPC_03_L        (REG_SECURE_TZPC_BASE + 0x06)
#define REG_SECURE_TZPC_03_H        (REG_SECURE_TZPC_BASE + 0x07)
#define REG_SECURE_TZPC_04_L        (REG_SECURE_TZPC_BASE + 0x08)
#define REG_SECURE_TZPC_04_H        (REG_SECURE_TZPC_BASE + 0x09)
#define REG_SECURE_TZPC_05_L        (REG_SECURE_TZPC_BASE + 0x0A)
#define REG_SECURE_TZPC_05_H        (REG_SECURE_TZPC_BASE + 0x0B)
#define REG_SECURE_TZPC_06_L        (REG_SECURE_TZPC_BASE + 0x0C)
#define REG_SECURE_TZPC_06_H        (REG_SECURE_TZPC_BASE + 0x0D)
#define REG_SECURE_TZPC_07_L        (REG_SECURE_TZPC_BASE + 0x0E)
#define REG_SECURE_TZPC_07_H        (REG_SECURE_TZPC_BASE + 0x0F)
#define REG_SECURE_TZPC_08_L        (REG_SECURE_TZPC_BASE + 0x10)
#define REG_SECURE_TZPC_08_H        (REG_SECURE_TZPC_BASE + 0x11)
#define REG_SECURE_TZPC_09_L        (REG_SECURE_TZPC_BASE + 0x12)
#define REG_SECURE_TZPC_09_H        (REG_SECURE_TZPC_BASE + 0x13)
#define REG_SECURE_TZPC_0A_L        (REG_SECURE_TZPC_BASE + 0x14)
#define REG_SECURE_TZPC_0A_H        (REG_SECURE_TZPC_BASE + 0x15)
#define REG_SECURE_TZPC_0B_L        (REG_SECURE_TZPC_BASE + 0x16)
#define REG_SECURE_TZPC_0B_H        (REG_SECURE_TZPC_BASE + 0x17)
#define REG_SECURE_TZPC_0C_L        (REG_SECURE_TZPC_BASE + 0x18)
#define REG_SECURE_TZPC_0C_H        (REG_SECURE_TZPC_BASE + 0x19)
#define REG_SECURE_TZPC_0D_L        (REG_SECURE_TZPC_BASE + 0x1A)
#define REG_SECURE_TZPC_0D_H        (REG_SECURE_TZPC_BASE + 0x1B)
#define REG_SECURE_TZPC_0E_L        (REG_SECURE_TZPC_BASE + 0x1C)
#define REG_SECURE_TZPC_0E_H        (REG_SECURE_TZPC_BASE + 0x1D)
#define REG_SECURE_TZPC_0F_L        (REG_SECURE_TZPC_BASE + 0x1E)
#define REG_SECURE_TZPC_0F_H        (REG_SECURE_TZPC_BASE + 0x1F)
#define REG_SECURE_TZPC_10_L        (REG_SECURE_TZPC_BASE + 0x20)
#define REG_SECURE_TZPC_10_H        (REG_SECURE_TZPC_BASE + 0x21)
#define REG_SECURE_TZPC_11_L        (REG_SECURE_TZPC_BASE + 0x22)
#define REG_SECURE_TZPC_11_H        (REG_SECURE_TZPC_BASE + 0x23)
#define REG_SECURE_TZPC_12_L        (REG_SECURE_TZPC_BASE + 0x24)
#define REG_SECURE_TZPC_12_H        (REG_SECURE_TZPC_BASE + 0x25)
#define REG_SECURE_TZPC_13_L        (REG_SECURE_TZPC_BASE + 0x26)
#define REG_SECURE_TZPC_13_H        (REG_SECURE_TZPC_BASE + 0x27)
#define REG_SECURE_TZPC_14_L        (REG_SECURE_TZPC_BASE + 0x28)
#define REG_SECURE_TZPC_14_H        (REG_SECURE_TZPC_BASE + 0x29)
#define REG_SECURE_TZPC_15_L        (REG_SECURE_TZPC_BASE + 0x2A)
#define REG_SECURE_TZPC_15_H        (REG_SECURE_TZPC_BASE + 0x2B)
#define REG_SECURE_TZPC_16_L        (REG_SECURE_TZPC_BASE + 0x2C)
#define REG_SECURE_TZPC_16_H        (REG_SECURE_TZPC_BASE + 0x2D)
#define REG_SECURE_TZPC_17_L        (REG_SECURE_TZPC_BASE + 0x2E)
#define REG_SECURE_TZPC_17_H        (REG_SECURE_TZPC_BASE + 0x2F)
#define REG_SECURE_TZPC_18_L        (REG_SECURE_TZPC_BASE + 0x30)
#define REG_SECURE_TZPC_18_H        (REG_SECURE_TZPC_BASE + 0x31)
#define REG_SECURE_TZPC_19_L        (REG_SECURE_TZPC_BASE + 0x32)
#define REG_SECURE_TZPC_19_H        (REG_SECURE_TZPC_BASE + 0x33)
#define REG_SECURE_TZPC_1A_L        (REG_SECURE_TZPC_BASE + 0x34)
#define REG_SECURE_TZPC_1A_H        (REG_SECURE_TZPC_BASE + 0x35)
#define REG_SECURE_TZPC_1B_L        (REG_SECURE_TZPC_BASE + 0x36)
#define REG_SECURE_TZPC_1B_H        (REG_SECURE_TZPC_BASE + 0x37)
#define REG_SECURE_TZPC_1C_L        (REG_SECURE_TZPC_BASE + 0x38)
#define REG_SECURE_TZPC_1C_H        (REG_SECURE_TZPC_BASE + 0x39)
#define REG_SECURE_TZPC_1D_L        (REG_SECURE_TZPC_BASE + 0x3A)
#define REG_SECURE_TZPC_1D_H        (REG_SECURE_TZPC_BASE + 0x3B)
#define REG_SECURE_TZPC_1E_L        (REG_SECURE_TZPC_BASE + 0x3C)
#define REG_SECURE_TZPC_1E_H        (REG_SECURE_TZPC_BASE + 0x3D)
#define REG_SECURE_TZPC_1F_L        (REG_SECURE_TZPC_BASE + 0x3E)
#define REG_SECURE_TZPC_1F_H        (REG_SECURE_TZPC_BASE + 0x3F)
#define REG_SECURE_TZPC_20_L        (REG_SECURE_TZPC_BASE + 0x40)
#define REG_SECURE_TZPC_20_H        (REG_SECURE_TZPC_BASE + 0x41)
#define REG_SECURE_TZPC_21_L        (REG_SECURE_TZPC_BASE + 0x42)
#define REG_SECURE_TZPC_21_H        (REG_SECURE_TZPC_BASE + 0x43)
#define REG_SECURE_TZPC_22_L        (REG_SECURE_TZPC_BASE + 0x44)
#define REG_SECURE_TZPC_22_H        (REG_SECURE_TZPC_BASE + 0x45)
#define REG_SECURE_TZPC_23_L        (REG_SECURE_TZPC_BASE + 0x46)
#define REG_SECURE_TZPC_23_H        (REG_SECURE_TZPC_BASE + 0x47)
#define REG_SECURE_TZPC_24_L        (REG_SECURE_TZPC_BASE + 0x48)
#define REG_SECURE_TZPC_24_H        (REG_SECURE_TZPC_BASE + 0x49)
#define REG_SECURE_TZPC_25_L        (REG_SECURE_TZPC_BASE + 0x4A)
#define REG_SECURE_TZPC_25_H        (REG_SECURE_TZPC_BASE + 0x4B)
#define REG_SECURE_TZPC_26_L        (REG_SECURE_TZPC_BASE + 0x4C)
#define REG_SECURE_TZPC_26_H        (REG_SECURE_TZPC_BASE + 0x4D)
#define REG_SECURE_TZPC_27_L        (REG_SECURE_TZPC_BASE + 0x4E)
#define REG_SECURE_TZPC_27_H        (REG_SECURE_TZPC_BASE + 0x4F)
#define REG_SECURE_TZPC_28_L        (REG_SECURE_TZPC_BASE + 0x50)
#define REG_SECURE_TZPC_28_H        (REG_SECURE_TZPC_BASE + 0x51)
#define REG_SECURE_TZPC_29_L        (REG_SECURE_TZPC_BASE + 0x52)
#define REG_SECURE_TZPC_29_H        (REG_SECURE_TZPC_BASE + 0x53)
#define REG_SECURE_TZPC_2A_L        (REG_SECURE_TZPC_BASE + 0x54)
#define REG_SECURE_TZPC_2A_H        (REG_SECURE_TZPC_BASE + 0x55)
#define REG_SECURE_TZPC_2B_L        (REG_SECURE_TZPC_BASE + 0x56)
#define REG_SECURE_TZPC_2B_H        (REG_SECURE_TZPC_BASE + 0x57)
#define REG_SECURE_TZPC_2C_L        (REG_SECURE_TZPC_BASE + 0x58)
#define REG_SECURE_TZPC_2C_H        (REG_SECURE_TZPC_BASE + 0x59)
#define REG_SECURE_TZPC_2D_L        (REG_SECURE_TZPC_BASE + 0x5A)
#define REG_SECURE_TZPC_2D_H        (REG_SECURE_TZPC_BASE + 0x5B)
#define REG_SECURE_TZPC_2E_L        (REG_SECURE_TZPC_BASE + 0x5C)
#define REG_SECURE_TZPC_2E_H        (REG_SECURE_TZPC_BASE + 0x5D)
#define REG_SECURE_TZPC_2F_L        (REG_SECURE_TZPC_BASE + 0x5E)
#define REG_SECURE_TZPC_2F_H        (REG_SECURE_TZPC_BASE + 0x5F)
#define REG_SECURE_TZPC_30_L        (REG_SECURE_TZPC_BASE + 0x60)
#define REG_SECURE_TZPC_30_H        (REG_SECURE_TZPC_BASE + 0x61)
#define REG_SECURE_TZPC_31_L        (REG_SECURE_TZPC_BASE + 0x62)
#define REG_SECURE_TZPC_31_H        (REG_SECURE_TZPC_BASE + 0x63)
#define REG_SECURE_TZPC_32_L        (REG_SECURE_TZPC_BASE + 0x64)
#define REG_SECURE_TZPC_32_H        (REG_SECURE_TZPC_BASE + 0x65)
#define REG_SECURE_TZPC_33_L        (REG_SECURE_TZPC_BASE + 0x66)
#define REG_SECURE_TZPC_33_H        (REG_SECURE_TZPC_BASE + 0x67)
#define REG_SECURE_TZPC_34_L        (REG_SECURE_TZPC_BASE + 0x68)
#define REG_SECURE_TZPC_34_H        (REG_SECURE_TZPC_BASE + 0x69)
#define REG_SECURE_TZPC_35_L        (REG_SECURE_TZPC_BASE + 0x6A)
#define REG_SECURE_TZPC_35_H        (REG_SECURE_TZPC_BASE + 0x6B)
#define REG_SECURE_TZPC_36_L        (REG_SECURE_TZPC_BASE + 0x6C)
#define REG_SECURE_TZPC_36_H        (REG_SECURE_TZPC_BASE + 0x6D)
#define REG_SECURE_TZPC_37_L        (REG_SECURE_TZPC_BASE + 0x6E)
#define REG_SECURE_TZPC_37_H        (REG_SECURE_TZPC_BASE + 0x6F)
#define REG_SECURE_TZPC_38_L        (REG_SECURE_TZPC_BASE + 0x70)
#define REG_SECURE_TZPC_38_H        (REG_SECURE_TZPC_BASE + 0x71)
#define REG_SECURE_TZPC_39_L        (REG_SECURE_TZPC_BASE + 0x72)
#define REG_SECURE_TZPC_39_H        (REG_SECURE_TZPC_BASE + 0x73)
#define REG_SECURE_TZPC_3A_L        (REG_SECURE_TZPC_BASE + 0x74)
#define REG_SECURE_TZPC_3A_H        (REG_SECURE_TZPC_BASE + 0x75)
#define REG_SECURE_TZPC_3B_L        (REG_SECURE_TZPC_BASE + 0x76)
#define REG_SECURE_TZPC_3B_H        (REG_SECURE_TZPC_BASE + 0x77)
#define REG_SECURE_TZPC_3C_L        (REG_SECURE_TZPC_BASE + 0x78)
#define REG_SECURE_TZPC_3C_H        (REG_SECURE_TZPC_BASE + 0x79)
#define REG_SECURE_TZPC_3D_L        (REG_SECURE_TZPC_BASE + 0x7A)
#define REG_SECURE_TZPC_3D_H        (REG_SECURE_TZPC_BASE + 0x7B)
#define REG_SECURE_TZPC_3E_L        (REG_SECURE_TZPC_BASE + 0x7C)
#define REG_SECURE_TZPC_3E_H        (REG_SECURE_TZPC_BASE + 0x7D)
#define REG_SECURE_TZPC_3F_L        (REG_SECURE_TZPC_BASE + 0x7E)
#define REG_SECURE_TZPC_3F_H        (REG_SECURE_TZPC_BASE + 0x7F)
#define REG_SECURE_TZPC_40_L        (REG_SECURE_TZPC_BASE + 0x80)
#define REG_SECURE_TZPC_40_H        (REG_SECURE_TZPC_BASE + 0x81)
#define REG_SECURE_TZPC_41_L        (REG_SECURE_TZPC_BASE + 0x82)
#define REG_SECURE_TZPC_41_H        (REG_SECURE_TZPC_BASE + 0x83)
#define REG_SECURE_TZPC_42_L        (REG_SECURE_TZPC_BASE + 0x84)
#define REG_SECURE_TZPC_42_H        (REG_SECURE_TZPC_BASE + 0x85)
#define REG_SECURE_TZPC_43_L        (REG_SECURE_TZPC_BASE + 0x86)
#define REG_SECURE_TZPC_43_H        (REG_SECURE_TZPC_BASE + 0x87)
#define REG_SECURE_TZPC_44_L        (REG_SECURE_TZPC_BASE + 0x88)
#define REG_SECURE_TZPC_44_H        (REG_SECURE_TZPC_BASE + 0x89)
#define REG_SECURE_TZPC_45_L        (REG_SECURE_TZPC_BASE + 0x8A)
#define REG_SECURE_TZPC_45_H        (REG_SECURE_TZPC_BASE + 0x8B)
#define REG_SECURE_TZPC_46_L        (REG_SECURE_TZPC_BASE + 0x8C)
#define REG_SECURE_TZPC_46_H        (REG_SECURE_TZPC_BASE + 0x8D)
#define REG_SECURE_TZPC_47_L        (REG_SECURE_TZPC_BASE + 0x8E)
#define REG_SECURE_TZPC_47_H        (REG_SECURE_TZPC_BASE + 0x8F)
#define REG_SECURE_TZPC_48_L        (REG_SECURE_TZPC_BASE + 0x90)
#define REG_SECURE_TZPC_48_H        (REG_SECURE_TZPC_BASE + 0x91)
#define REG_SECURE_TZPC_49_L        (REG_SECURE_TZPC_BASE + 0x92)
#define REG_SECURE_TZPC_49_H        (REG_SECURE_TZPC_BASE + 0x93)
#define REG_SECURE_TZPC_4A_L        (REG_SECURE_TZPC_BASE + 0x94)
#define REG_SECURE_TZPC_4A_H        (REG_SECURE_TZPC_BASE + 0x95)
#define REG_SECURE_TZPC_4B_L        (REG_SECURE_TZPC_BASE + 0x96)
#define REG_SECURE_TZPC_4B_H        (REG_SECURE_TZPC_BASE + 0x97)
#define REG_SECURE_TZPC_4C_L        (REG_SECURE_TZPC_BASE + 0x98)
#define REG_SECURE_TZPC_4C_H        (REG_SECURE_TZPC_BASE + 0x99)
#define REG_SECURE_TZPC_4D_L        (REG_SECURE_TZPC_BASE + 0x9A)
#define REG_SECURE_TZPC_4D_H        (REG_SECURE_TZPC_BASE + 0x9B)
#define REG_SECURE_TZPC_4E_L        (REG_SECURE_TZPC_BASE + 0x9C)
#define REG_SECURE_TZPC_4E_H        (REG_SECURE_TZPC_BASE + 0x9D)
#define REG_SECURE_TZPC_4F_L        (REG_SECURE_TZPC_BASE + 0x9E)
#define REG_SECURE_TZPC_4F_H        (REG_SECURE_TZPC_BASE + 0x9F)
#define REG_SECURE_TZPC_50_L        (REG_SECURE_TZPC_BASE + 0xA0)
#define REG_SECURE_TZPC_50_H        (REG_SECURE_TZPC_BASE + 0xA1)
#define REG_SECURE_TZPC_51_L        (REG_SECURE_TZPC_BASE + 0xA2)
#define REG_SECURE_TZPC_51_H        (REG_SECURE_TZPC_BASE + 0xA3)
#define REG_SECURE_TZPC_52_L        (REG_SECURE_TZPC_BASE + 0xA4)
#define REG_SECURE_TZPC_52_H        (REG_SECURE_TZPC_BASE + 0xA5)
#define REG_SECURE_TZPC_53_L        (REG_SECURE_TZPC_BASE + 0xA6)
#define REG_SECURE_TZPC_53_H        (REG_SECURE_TZPC_BASE + 0xA7)
#define REG_SECURE_TZPC_54_L        (REG_SECURE_TZPC_BASE + 0xA8)
#define REG_SECURE_TZPC_54_H        (REG_SECURE_TZPC_BASE + 0xA9)
#define REG_SECURE_TZPC_55_L        (REG_SECURE_TZPC_BASE + 0xAA)
#define REG_SECURE_TZPC_55_H        (REG_SECURE_TZPC_BASE + 0xAB)
#define REG_SECURE_TZPC_56_L        (REG_SECURE_TZPC_BASE + 0xAC)
#define REG_SECURE_TZPC_56_H        (REG_SECURE_TZPC_BASE + 0xAD)
#define REG_SECURE_TZPC_57_L        (REG_SECURE_TZPC_BASE + 0xAE)
#define REG_SECURE_TZPC_57_H        (REG_SECURE_TZPC_BASE + 0xAF)
#define REG_SECURE_TZPC_58_L        (REG_SECURE_TZPC_BASE + 0xB0)
#define REG_SECURE_TZPC_58_H        (REG_SECURE_TZPC_BASE + 0xB1)
#define REG_SECURE_TZPC_59_L        (REG_SECURE_TZPC_BASE + 0xB2)
#define REG_SECURE_TZPC_59_H        (REG_SECURE_TZPC_BASE + 0xB3)
#define REG_SECURE_TZPC_5A_L        (REG_SECURE_TZPC_BASE + 0xB4)
#define REG_SECURE_TZPC_5A_H        (REG_SECURE_TZPC_BASE + 0xB5)
#define REG_SECURE_TZPC_5B_L        (REG_SECURE_TZPC_BASE + 0xB6)
#define REG_SECURE_TZPC_5B_H        (REG_SECURE_TZPC_BASE + 0xB7)
#define REG_SECURE_TZPC_5C_L        (REG_SECURE_TZPC_BASE + 0xB8)
#define REG_SECURE_TZPC_5C_H        (REG_SECURE_TZPC_BASE + 0xB9)
#define REG_SECURE_TZPC_5D_L        (REG_SECURE_TZPC_BASE + 0xBA)
#define REG_SECURE_TZPC_5D_H        (REG_SECURE_TZPC_BASE + 0xBB)
#define REG_SECURE_TZPC_5E_L        (REG_SECURE_TZPC_BASE + 0xBC)
#define REG_SECURE_TZPC_5E_H        (REG_SECURE_TZPC_BASE + 0xBD)
#define REG_SECURE_TZPC_5F_L        (REG_SECURE_TZPC_BASE + 0xBE)
#define REG_SECURE_TZPC_5F_H        (REG_SECURE_TZPC_BASE + 0xBF)
#define REG_SECURE_TZPC_60_L        (REG_SECURE_TZPC_BASE + 0xC0)
#define REG_SECURE_TZPC_60_H        (REG_SECURE_TZPC_BASE + 0xC1)
#define REG_SECURE_TZPC_61_L        (REG_SECURE_TZPC_BASE + 0xC2)
#define REG_SECURE_TZPC_61_H        (REG_SECURE_TZPC_BASE + 0xC3)
#define REG_SECURE_TZPC_62_L        (REG_SECURE_TZPC_BASE + 0xC4)
#define REG_SECURE_TZPC_62_H        (REG_SECURE_TZPC_BASE + 0xC5)
#define REG_SECURE_TZPC_63_L        (REG_SECURE_TZPC_BASE + 0xC6)
#define REG_SECURE_TZPC_63_H        (REG_SECURE_TZPC_BASE + 0xC7)
#define REG_SECURE_TZPC_64_L        (REG_SECURE_TZPC_BASE + 0xC8)
#define REG_SECURE_TZPC_64_H        (REG_SECURE_TZPC_BASE + 0xC9)
#define REG_SECURE_TZPC_65_L        (REG_SECURE_TZPC_BASE + 0xCA)
#define REG_SECURE_TZPC_65_H        (REG_SECURE_TZPC_BASE + 0xCB)
#define REG_SECURE_TZPC_66_L        (REG_SECURE_TZPC_BASE + 0xCC)
#define REG_SECURE_TZPC_66_H        (REG_SECURE_TZPC_BASE + 0xCD)
#define REG_SECURE_TZPC_67_L        (REG_SECURE_TZPC_BASE + 0xCE)
#define REG_SECURE_TZPC_67_H        (REG_SECURE_TZPC_BASE + 0xCF)
#define REG_SECURE_TZPC_68_L        (REG_SECURE_TZPC_BASE + 0xD0)
#define REG_SECURE_TZPC_68_H        (REG_SECURE_TZPC_BASE + 0xD1)
#define REG_SECURE_TZPC_69_L        (REG_SECURE_TZPC_BASE + 0xD2)
#define REG_SECURE_TZPC_69_H        (REG_SECURE_TZPC_BASE + 0xD3)
#define REG_SECURE_TZPC_6A_L        (REG_SECURE_TZPC_BASE + 0xD4)
#define REG_SECURE_TZPC_6A_H        (REG_SECURE_TZPC_BASE + 0xD5)
#define REG_SECURE_TZPC_6B_L        (REG_SECURE_TZPC_BASE + 0xD6)
#define REG_SECURE_TZPC_6B_H        (REG_SECURE_TZPC_BASE + 0xD7)
#define REG_SECURE_TZPC_6C_L        (REG_SECURE_TZPC_BASE + 0xD8)
#define REG_SECURE_TZPC_6C_H        (REG_SECURE_TZPC_BASE + 0xD9)
#define REG_SECURE_TZPC_6D_L        (REG_SECURE_TZPC_BASE + 0xDA)
#define REG_SECURE_TZPC_6D_H        (REG_SECURE_TZPC_BASE + 0xDB)
#define REG_SECURE_TZPC_6E_L        (REG_SECURE_TZPC_BASE + 0xDC)
#define REG_SECURE_TZPC_6E_H        (REG_SECURE_TZPC_BASE + 0xDD)

// CHIP_GPIO
#define REG_CHIP_GPIO_08_L          (REG_CHIP_GPIO_BASE + 0x10)
#define REG_CHIP_GPIO_08_H          (REG_CHIP_GPIO_BASE + 0x11)
#define REG_CHIP_GPIO_09_L          (REG_CHIP_GPIO_BASE + 0x12)
#define REG_CHIP_GPIO_09_H          (REG_CHIP_GPIO_BASE + 0x13)
#define REG_CHIP_GPIO_0A_L          (REG_CHIP_GPIO_BASE + 0x14)
#define REG_CHIP_GPIO_0A_H          (REG_CHIP_GPIO_BASE + 0x15)
#define REG_CHIP_GPIO_0B_L          (REG_CHIP_GPIO_BASE + 0x16)
#define REG_CHIP_GPIO_0B_H          (REG_CHIP_GPIO_BASE + 0x17)
#define REG_CHIP_GPIO_0C_L          (REG_CHIP_GPIO_BASE + 0x18)
#define REG_CHIP_GPIO_0C_H          (REG_CHIP_GPIO_BASE + 0x19)
#define REG_CHIP_GPIO_0D_L          (REG_CHIP_GPIO_BASE + 0x1A)
#define REG_CHIP_GPIO_0D_H          (REG_CHIP_GPIO_BASE + 0x1B)
#define REG_CHIP_GPIO_0E_L          (REG_CHIP_GPIO_BASE + 0x1C)
#define REG_CHIP_GPIO_0E_H          (REG_CHIP_GPIO_BASE + 0x1D)
#define REG_CHIP_GPIO_0F_L          (REG_CHIP_GPIO_BASE + 0x1E)
#define REG_CHIP_GPIO_0F_H          (REG_CHIP_GPIO_BASE + 0x1F)

#define REG_CHIP_GPIO_50_L          (REG_CHIP_GPIO_BASE + 0xA0)
#define REG_CHIP_GPIO_50_H          (REG_CHIP_GPIO_BASE + 0xA1)
#define REG_CHIP_GPIO_51_L          (REG_CHIP_GPIO_BASE + 0xA2)
#define REG_CHIP_GPIO_51_H          (REG_CHIP_GPIO_BASE + 0xA3)
#define REG_CHIP_GPIO_52_L          (REG_CHIP_GPIO_BASE + 0xA4)
#define REG_CHIP_GPIO_52_H          (REG_CHIP_GPIO_BASE + 0xA5)
#define REG_CHIP_GPIO_53_L          (REG_CHIP_GPIO_BASE + 0xA6)
#define REG_CHIP_GPIO_53_H          (REG_CHIP_GPIO_BASE + 0xA7)
#define REG_CHIP_GPIO_54_L          (REG_CHIP_GPIO_BASE + 0xA8)
#define REG_CHIP_GPIO_54_H          (REG_CHIP_GPIO_BASE + 0xA9)
#define REG_CHIP_GPIO_55_L          (REG_CHIP_GPIO_BASE + 0xAA)
#define REG_CHIP_GPIO_55_H          (REG_CHIP_GPIO_BASE + 0xAB)
#define REG_CHIP_GPIO_56_L          (REG_CHIP_GPIO_BASE + 0xAC)
#define REG_CHIP_GPIO_56_H          (REG_CHIP_GPIO_BASE + 0xAD)
#define REG_CHIP_GPIO_57_L          (REG_CHIP_GPIO_BASE + 0xAE)
#define REG_CHIP_GPIO_57_H          (REG_CHIP_GPIO_BASE + 0xAF)

#endif