// //****************************************************************************** // MStar Software // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. // All software, firmware and related documentation herein ("MStar Software") are // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by // law, including, but not limited to, copyright law and international treaties. // Any use, modification, reproduction, retransmission, or republication of all // or part of MStar Software is expressly prohibited, unless prior written // permission has been granted by MStar. // // By accessing, browsing and/or using MStar Software, you acknowledge that you // have read, understood, and agree, to be bound by below terms ("Terms") and to // comply with all applicable laws and regulations: // // 1. MStar shall retain any and all right, ownership and interest to MStar // Software and any modification/derivatives thereof. // No right, ownership, or interest to MStar Software and any // modification/derivatives thereof is transferred to you under Terms. // // 2. You understand that MStar Software might include, incorporate or be // supplied together with third party`s software and the use of MStar // Software may require additional licenses from third parties. // Therefore, you hereby agree it is your sole responsibility to separately // obtain any and all third party right and license necessary for your use of // such third party`s software. // // 3. MStar Software and any modification/derivatives thereof shall be deemed as // MStar`s confidential information and you agree to keep MStar`s // confidential information in strictest confidence and not disclose to any // third party. // // 4. MStar Software is provided on an "AS IS" basis without warranties of any // kind. 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If requested, MStar may from time to time provide technical supports or // services in relation with MStar Software to you for your use of // MStar Software in conjunction with your or your customer`s product // ("Services"). // You understand and agree that, except otherwise agreed by both parties in // writing, Services are provided on an "AS IS" basis and the warranty // disclaimer set forth in Section 4 above shall apply. // // 6. Nothing contained herein shall be construed as by implication, estoppels // or otherwise: // (a) conferring any license or right to use MStar name, trademark, service // mark, symbol or any other identification; // (b) obligating MStar or any of its affiliates to furnish any person, // including without limitation, you and your customers, any assistance // of any kind whatsoever, or any information; or // (c) conferring any license or right under any intellectual property right. // // 7. These terms shall be governed by and construed in accordance with the laws // of Taiwan, R.O.C., excluding its conflict of law rules. // Any and all dispute arising out hereof or related hereto shall be finally // settled by arbitration referred to the Chinese Arbitration Association, // Taipei in accordance with the ROC Arbitration Law and the Arbitration // Rules of the Association by three (3) arbitrators appointed in accordance // with the said Rules. // The place of arbitration shall be in Taipei, Taiwan and the language shall // be English. // The arbitration award shall be final and binding to both parties. // //****************************************************************************** // //////////////////////////////////////////////////////////////////////////////// // // Copyright (c) 2008-2009 MStar Semiconductor, Inc. // All rights reserved. // // Unless otherwise stipulated in writing, any and all information contained // herein regardless in any format shall remain the sole proprietary of // MStar Semiconductor Inc. and be kept in strict confidence // ("MStar Confidential Information") by the recipient. // Any unauthorized act including without limitation unauthorized disclosure, // copying, use, reproduction, sale, distribution, modification, disassembling, // reverse engineering and compiling of the contents of MStar Confidential // Information is unlawful and strictly prohibited. MStar hereby reserves the // rights to any and all damages, losses, costs and expenses resulting therefrom. // //////////////////////////////////////////////////////////////////////////////// #ifndef _REGVIF_H_ #define _REGVIF_H_ // ========== Register Definition ===================== #define ADC_REG_BASE 0x12800UL #define RF_REG_BASE 0x12100UL #define DBB1_REG_BASE 0x12200UL #define DBB2_REG_BASE 0x12300UL #define DBB3_REG_BASE 0x12400UL /////////////////////////////////////////////////////// // [ADC bank register] /////////////////////////////////////////////////////// #define VCLP (ADC_REG_BASE+0x40) #define PWDN_REF (ADC_REG_BASE+0x40) #define SIF_EN (ADC_REG_BASE+0x40) #define VIF_EN (ADC_REG_BASE+0x40) #define VCLPGA2 (ADC_REG_BASE+0x41) #define VCLPGA1 (ADC_REG_BASE+0x41) #define VIF_ICT1 (ADC_REG_BASE+0x42) #define VIF_ICT2 (ADC_REG_BASE+0x42) #define VIF_ICT3 (ADC_REG_BASE+0x42) #define VIF_ICT4 (ADC_REG_BASE+0x42) #define VIF_ICT5 (ADC_REG_BASE+0x44) #define SIF_ICT1 (ADC_REG_BASE+0x44) #define SIF_ICT2 (ADC_REG_BASE+0x44) #define SIF_ICT3 (ADC_REG_BASE+0x44) #define SIF_ICT4 (ADC_REG_BASE+0x44) #define SIF_ICT5 (ADC_REG_BASE+0x45) #define VIF_TEST (ADC_REG_BASE+0x46) #define SIF_TEST (ADC_REG_BASE+0x47) #define VIF_GSEL2 (ADC_REG_BASE+0x48) #define VIF_GSEL3 (ADC_REG_BASE+0x49) #define VIF_GSEL4 (ADC_REG_BASE+0x49) #define SIF_GSEL2 (ADC_REG_BASE+0x4A) #define SIF_GSEL3 (ADC_REG_BASE+0x4B) #define SIF_GSEL4 (ADC_REG_BASE+0x4B) #define VIF_REFS1 (ADC_REG_BASE+0x4C) #define SIF_REFS1 (ADC_REG_BASE+0x4C) #define VIF_REFS2 (ADC_REG_BASE+0x4C) #define SIF_REFS2 (ADC_REG_BASE+0x4C) #define RFAGC_ENABLE (ADC_REG_BASE+0x6C) #define RFAGC_ODMODE (ADC_REG_BASE+0x6C) #define TAGC_ODMODE (ADC_REG_BASE+0x6C) #define RFAGC_DATA_SEL (ADC_REG_BASE+0x6C) #define IFAGC_ENABLE (ADC_REG_BASE+0x6C) #define IFAGC_ODMODE (ADC_REG_BASE+0x6C) #define IFAGC_DATA_SEL (ADC_REG_BASE+0x6C) /////////////////////////////////////////////////////// // [RF bank register] /////////////////////////////////////////////////////// #define RF_LOAD (RF_REG_BASE+0x02) #define VIF_VCO_BANK_W (RF_REG_BASE+0x08) #define VIF_PLL_CPINIT_W (RF_REG_BASE+0x08) #define VIF_CAL_START (RF_REG_BASE+0x08) #define VIF_PGA1GAINS_W (RF_REG_BASE+0x09) #define VIF_PGA1GAINV_W (RF_REG_BASE+0x09) #define VIF_GAIN_PGA2S_W (RF_REG_BASE+0x0A) #define VIF_GAIN_PGA2V_W (RF_REG_BASE+0x0A) #define PGAV_ORDER (RF_REG_BASE+0x0C) #define PGAS_ORDER (RF_REG_BASE+0x0C) #define VIF_PGCR (RF_REG_BASE+0x0D) #define IFAGC_W_L (RF_REG_BASE+0x10) #define IFAGC_W_H (RF_REG_BASE+0x11) #define RFAGC_W_L (RF_REG_BASE+0x12) #define RFAGC_W_H (RF_REG_BASE+0x13) #define IFAGC_TEST_EN (RF_REG_BASE+0x14) #define IFAGC_POLARITY (RF_REG_BASE+0x14) #define IFAGC_SEL_DECIMATE_NUM (RF_REG_BASE+0x15) #define IFAGC_DITHER_SHIFT (RF_REG_BASE+0x15) #define IFAGC_SEL_SECONDER (RF_REG_BASE+0x15) #define IFAGC_DITHER_EN (RF_REG_BASE+0x15) #define RFAGC_TEST_EN (RF_REG_BASE+0x16) #define RFAGC_POLARITY (RF_REG_BASE+0x16) #define RFAGC_SEL_DECIMATE_NUM (RF_REG_BASE+0x17) #define RFAGC_DITHER_SHIFT (RF_REG_BASE+0x17) #define RFAGC_SEL_SECONDER (RF_REG_BASE+0x17) #define RFAGC_DITHER_EN (RF_REG_BASE+0x17) #define OREN_PGA2_S (RF_REG_BASE+0x19) #define OREN_PGA1_S (RF_REG_BASE+0x19) #define OREN_PGA2_V (RF_REG_BASE+0x19) #define OREN_PGA1_V (RF_REG_BASE+0x19) #define OREN_VCO_BANK (RF_REG_BASE+0x19) #define OREN_RFAGC (RF_REG_BASE+0x19) #define OREN_IFAGC (RF_REG_BASE+0x19) #define VIF_VCO_BANK (RF_REG_BASE+0x1A) #define VIF_PLL_CPINIT (RF_REG_BASE+0x1A) #define VIF_LOCK (RF_REG_BASE+0x1A) #define VIF_VCTRL_UNDER (RF_REG_BASE+0x1A) #define VIF_VCTRL_OVER (RF_REG_BASE+0x1A) #define VIF_VCOCAL_FAIL (RF_REG_BASE+0x1A) #define VIF_PGA1GAINS (RF_REG_BASE+0x1B) #define VIF_PGA1GAINV (RF_REG_BASE+0x1B) #define VIF_GAIN_PGA2S (RF_REG_BASE+0x1C) #define VIF_GAIN_PGA2V (RF_REG_BASE+0x1C) #define VIF_FCODE_OUT (RF_REG_BASE+0x1D) #define VIF_STOPCAL_TUNE (RF_REG_BASE+0x1D) #define VIF_CAL_FINISH (RF_REG_BASE+0x1D) #define VIF_CAL_GAP (RF_REG_BASE+0x1E) #define VSYNC_VD_MASK (RF_REG_BASE+0x20) #define VSYNC_VD_POLARITY (RF_REG_BASE+0x20) #define VSYNC_OVERRIDE (RF_REG_BASE+0x21) #define VIF_BIST_FAIL (RF_REG_BASE+0x22) #define VIF_DACDLY_NUM (RF_REG_BASE+0x24) #define VIF_DACDLY_BYPASS (RF_REG_BASE+0x25) #define RFAGC_DAC_TESTBUS (RF_REG_BASE+0x28) #define IFAGC_DAC_TESTBUS (RF_REG_BASE+0x28) #define CLAMPGAIN_RSTZ (RF_REG_BASE+0x40) #define CLAMPGAIN_BYPASS (RF_REG_BASE+0x40) #define CLAMPGAIN_EN (RF_REG_BASE+0x40) #define CLAMPGAIN_SEL (RF_REG_BASE+0x40) #define CLAMPGAIN_STATUS_FREEZE (RF_REG_BASE+0x40) #define CLAMPGAIN_SYNCBOTT_REF (RF_REG_BASE+0x42) #define CLAMPGAIN_SYNCHEIGHT_REF (RF_REG_BASE+0x43) #define CLAMPGAIN_KC (RF_REG_BASE+0x44) #define CLAMPGAIN_KG (RF_REG_BASE+0x44) #define CLAMPGAIN_CLAMP_OREN (RF_REG_BASE+0x45) #define CLAMPGAIN_GAIN_OREN (RF_REG_BASE+0x45) #define CLAMPGAIN_CLAMP_OVERWRITE (RF_REG_BASE+0x46) #define CLAMPGAIN_GAIN_OVERWRITE (RF_REG_BASE+0x48) #define CLAMPGAIN_CLAMP_MIN (RF_REG_BASE+0x4A) #define CLAMPGAIN_CLAMP_MAX (RF_REG_BASE+0x4B) #define CLAMPGAIN_GAIN_MIN (RF_REG_BASE+0x4C) #define CLAMPGAIN_GAIN_MAX (RF_REG_BASE+0x4D) #define CLAMPGAIN_SYNCBOTTOM_OFFSET (RF_REG_BASE+0x4E) #define CLAMPGAIN_RATIO (RF_REG_BASE+0x4F) #define CLAMPGAIN_SYNCBOTTOM_CNT (RF_REG_BASE+0x50) #define CLAMPGAIN_PORCH_CNT (RF_REG_BASE+0x52) #define CLAMPGAIN_PEAK_MEAN (RF_REG_BASE+0x54) #define CLAMPGAIN_SYNCBOTTOM_MEAN (RF_REG_BASE+0x56) #define CLAMPGAIN_PORCH_MEAN (RF_REG_BASE+0x58) #define CLAMPGAIN_CLAMP (RF_REG_BASE+0x5A) #define CLAMPGAIN_GAIN (RF_REG_BASE+0x5C) #define VSYNC_RSTZ (RF_REG_BASE+0x80) #define VSYNC_ENABLE (RF_REG_BASE+0x80) #define VSYNC_LPF_SEL (RF_REG_BASE+0x80) #define VSYNC_DET_DATAIN_SEL (RF_REG_BASE+0x80) #define VSYNC_OFFSET (RF_REG_BASE+0x82) #define VSYNC_CNT (RF_REG_BASE+0x83) #define VSYNC_VSYNC_CNT (RF_REG_BASE+0x84) #define VSYNC_BYPASS_CNT (RF_REG_BASE+0x85) #define VSYNC_MIN_CNT (RF_REG_BASE+0x86) #define VIF_VADC_DEC (RF_REG_BASE+0xAA) #define VIF_AADC_DEC (RF_REG_BASE+0xAA) #define VIFDAC_OUT_SEL (RF_REG_BASE+0xC0) #define VIFDAC_ENABLE (RF_REG_BASE+0xC0) #define VIFDAC_MSB_INV (RF_REG_BASE+0xC0) #define VIFDAC_CLK_INV (RF_REG_BASE+0xC0) #define VIFDAC_TB_SWAP (RF_REG_BASE+0xC0) #define VIFDAC_RAMP_OUT_MAX_L (RF_REG_BASE+0xC2) #define VIFDAC_RAMP_OUT_MAX_H (RF_REG_BASE+0xC3) #define VIFDAC_RAMP_OUT_MIN_L (RF_REG_BASE+0xC4) #define VIFDAC_RAMP_OUT_MIN_H (RF_REG_BASE+0xC5) #define VIFDAC_FORCE_DATA_L (RF_REG_BASE+0xC6) #define VIFDAC_FORCE_DATA_H (RF_REG_BASE+0xC7) #define VSYNC_EXT (RF_REG_BASE+0xD0) #define VIFDAC_CVBSIN_SEL (RF_REG_BASE+0xD0) #define CLAMPGAIN_SEL2 (RF_REG_BASE+0xD0) #define VSYNC_INV (RF_REG_BASE+0xD0) #define VIF_RF_RESERVED_1 (RF_REG_BASE+0xD2) #define VIF_RF_RESERVED_2 (RF_REG_BASE+0xD4) #define VIF_RF_RESERVED_3 (RF_REG_BASE+0xD6) #define VIF_RF_READ0 (RF_REG_BASE+0xD8) #define VIF_RF_READ1 (RF_REG_BASE+0xDA) #define VIF_TIMER_MAX (RF_REG_BASE+0xE0) #define TIMER (RF_REG_BASE+0xE2) #define CNT_43 (RF_REG_BASE+0xE3) #define VIF_ADC_OUT (RF_REG_BASE+0xE4) #define SIF_ADC_OUT (RF_REG_BASE+0xE6) #define DCXO_RSTZ (RF_REG_BASE+0xEA) #define DCXO_MODE (RF_REG_BASE+0xEA) #define DCXO_SYNC (RF_REG_BASE+0xEB) #define DCXO_TRI_ANG_MIN (RF_REG_BASE+0xEC) #define DCXO_TRI_ANG_MAX (RF_REG_BASE+0xED) #define DCXO_FORCE (RF_REG_BASE+0xEE) #define DCXO_STEP_CNT (RF_REG_BASE+0xF0) #define DCXO_CODE (RF_REG_BASE+0xF4) ////////////////////////////////////////////////////////// // [DBB1 bank register] ///////////////////////////////////////////////////////// #define VIF_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define AFC_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define FILTER_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define AGC_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define DAGC1_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define DAGC2_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define AAGC_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define ADAGC_SOFT_RSTZ (DBB1_REG_BASE+0x00) #define MODULATION_TYPE (DBB1_REG_BASE+0x02) #define CR_STATUS_LATCH_EN (DBB1_REG_BASE+0x02) #define DEBUG_CLK_FINAL_SEL (DBB1_REG_BASE+0x02) #define BYPASS_N_A4 (DBB1_REG_BASE+0x02) #define BYPASS_CR_NOTCH2 (DBB1_REG_BASE+0x02) #define AUDIO_BYPASS (DBB1_REG_BASE+0x04) #define VIF_ADC_48M (DBB1_REG_BASE+0x04) #define VIF_ADC_LSB_MASK (DBB1_REG_BASE+0x05) #define VIF_DECI_COEF_SEL (DBB1_REG_BASE+0x05) #define LOCK_LEAKY_SEL (DBB1_REG_BASE+0x06) #define LOCK_LEAKY_FF_SEL (DBB1_REG_BASE+0x06) #define VNCO_INV_OREN (DBB1_REG_BASE+0x06) #define VNCO_INV_OV (DBB1_REG_BASE+0x06) #define CR_LEAKY_FACTOR_SEL (DBB1_REG_BASE+0x06) #define CR_LEAKY_FACTOR_SEL2 (DBB1_REG_BASE+0x06) #define CR_LEAKY_FACTOR_SEL3 (DBB1_REG_BASE+0x07) #define CR_CODIC_TH (DBB1_REG_BASE+0x08) #define BYPASS_SOS11 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS12 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS21 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS22 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS31 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS32 (DBB1_REG_BASE+0x0A) #define BYPASS_SOS33 (DBB1_REG_BASE+0x0A) #define BYPASS_NYQUIST_SLOPE (DBB1_REG_BASE+0x0B) #define BYPASS_IMAGE_REJ_IIR (DBB1_REG_BASE+0x0B) #define IMAGE_REJ_OUT_SEL (DBB1_REG_BASE+0x0B) #define DBB1_LOAD (DBB1_REG_BASE+0x10) #define CR_DL_A (DBB1_REG_BASE+0x14) #define CR_DL_A_BYPASS (DBB1_REG_BASE+0x14) #define CR_F_OFFSET (DBB1_REG_BASE+0x15) #define CR_PD_ERR_MAX_L (DBB1_REG_BASE+0x16) #define CR_PD_ERR_MAX_H (DBB1_REG_BASE+0x17) #define CR_KL_L (DBB1_REG_BASE+0x18) #define CR_KL_H (DBB1_REG_BASE+0x19) #define CR_NOTCH_A1_L (DBB1_REG_BASE+0x1A) #define CR_NOTCH_A1_H (DBB1_REG_BASE+0x1B) #define CR_NOTCH_A2_L (DBB1_REG_BASE+0x1C) #define CR_NOTCH_A2_H (DBB1_REG_BASE+0x1D) #define CR_NOTCH_B1_L (DBB1_REG_BASE+0x1E) #define CR_NOTCH_B1_H (DBB1_REG_BASE+0x1F) #define CR_ANCO_SEL (DBB1_REG_BASE+0x20) #define CR_PD_MODE (DBB1_REG_BASE+0x20) #define CR_PD_X2 (DBB1_REG_BASE+0x20) #define CR_INV (DBB1_REG_BASE+0x20) #define CR_LPF_SEL (DBB1_REG_BASE+0x20) #define CR_LF_FF_RSTZ (DBB1_REG_BASE+0x20) #define CR_K_SEL (DBB1_REG_BASE+0x20) #define CR_PD_LIMITER (DBB1_REG_BASE+0x20) #define CR_FD_IN_SEL (DBB1_REG_BASE+0x21) #define CR_IIR_SEL (DBB1_REG_BASE+0x21) #define CR_NCO_FF_RSTZ (DBB1_REG_BASE+0x21) #define CR_KP_SW (DBB1_REG_BASE+0x22) #define CR_KI_SW (DBB1_REG_BASE+0x22) #define CR_KF_SW (DBB1_REG_BASE+0x23) #define CR_RATE (DBB1_REG_BASE+0x24) #define CR_KP1_HW (DBB1_REG_BASE+0x28) #define CR_KI1_HW (DBB1_REG_BASE+0x28) #define CR_KF1_HW (DBB1_REG_BASE+0x29) #define CR_KP2_HW (DBB1_REG_BASE+0x2A) #define CR_KI2_HW (DBB1_REG_BASE+0x2A) #define CR_KF2_HW (DBB1_REG_BASE+0x2B) #define CR_FD_DELAY_SEL (DBB1_REG_BASE+0x2B) #define CR_LOCK_TH_L (DBB1_REG_BASE+0x2C) #define CR_LOCK_TH_H (DBB1_REG_BASE+0x2D) #define CR_FOE_SCAL_FACTOR_L (DBB1_REG_BASE+0x2E) #define CR_FOE_SCAL_FACTOR_H (DBB1_REG_BASE+0x2F) #define CR_FD_MU (DBB1_REG_BASE+0x2F) #define CR_LOCK_NUM (DBB1_REG_BASE+0x30) #define CR_UNLOCK_NUM (DBB1_REG_BASE+0x34) #define CR_FOE (DBB1_REG_BASE+0x38) #define CR_LOCK_STATUS (DBB1_REG_BASE+0x39) #define CR_LOCK_STATUS2 (DBB1_REG_BASE+0x39) #define CR_LOCK_LEAKY_FF_I (DBB1_REG_BASE+0x3A) #define CR_LOCK_LEAKY_FF_Q (DBB1_REG_BASE+0x3C) #define CR_NOTCH2_A1_L (DBB1_REG_BASE+0x3E) #define CR_NOTCH2_A1_H (DBB1_REG_BASE+0x3F) #define CR_NOTCH2_A2_L (DBB1_REG_BASE+0x40) #define CR_NOTCH2_A2_H (DBB1_REG_BASE+0x41) #define CR_NOTCH2_B1_L (DBB1_REG_BASE+0x42) #define CR_NOTCH2_B1_H (DBB1_REG_BASE+0x43) #define CR_LF_FF_RPT (DBB1_REG_BASE+0x44) #define ZERO_ENABLE (DBB1_REG_BASE+0x48) #define ZERO_IN_SEL (DBB1_REG_BASE+0x48) #define ZERO_TH (DBB1_REG_BASE+0x49) #define ZERO_CNT_NUM (DBB1_REG_BASE+0x4A) #define ZERO_ZERO_NUM (DBB1_REG_BASE+0x4C) #define CR_IIR_COEF_G (DBB1_REG_BASE+0x50) #define CR_IIR_COEF_A1 (DBB1_REG_BASE+0x52) #define CR_IIR_COEF_A2 (DBB1_REG_BASE+0x54) #define CR_IIR_COEF_B1 (DBB1_REG_BASE+0x56) #define CR_IIR_COEF_B2 (DBB1_REG_BASE+0x58) #define CR_KP_SCALE (DBB1_REG_BASE+0x5A) #define CR_KI_SCALE (DBB1_REG_BASE+0x5A) #define CR_KP_SCALE2 (DBB1_REG_BASE+0x5B) #define CR_KI_SCALE2 (DBB1_REG_BASE+0x5B) #define CR_RATE2 (DBB1_REG_BASE+0x5C) #define CR_K_SEL2 (DBB1_REG_BASE+0x5F) #define CR_KP_SW2 (DBB1_REG_BASE+0x60) #define CR_KI_SW2 (DBB1_REG_BASE+0x60) #define CR_KP1_HW2 (DBB1_REG_BASE+0x61) #define CR_KI1_HW2 (DBB1_REG_BASE+0x61) #define CR_KP2_HW2 (DBB1_REG_BASE+0x62) #define CR_KI2_HW2 (DBB1_REG_BASE+0x62) #define CR_LOCK_TH2 (DBB1_REG_BASE+0x64) #define CR_LOCK_NUM2 (DBB1_REG_BASE+0x66) #define CR_UNLOCK_NUM2 (DBB1_REG_BASE+0x6A) #define CR_PD_ERR_MAX2 (DBB1_REG_BASE+0x6E) #define CR_PD_KL2 (DBB1_REG_BASE+0x70) #define CR_JTR_MAX_CNT (DBB1_REG_BASE+0x72) #define CR_JTR_SEL (DBB1_REG_BASE+0x74) #define JTR_DELTA_AVE_NUM (DBB1_REG_BASE+0x74) #define CR_OBS_SEL (DBB1_REG_BASE+0x74) #define CR_LF_FF2_RSTZ (DBB1_REG_BASE+0x75) #define CR_LOCK_LEAKY_SEL2 (DBB1_REG_BASE+0x75) #define CR_JTR_OUT (DBB1_REG_BASE+0x76) #define ZERO_DETECT (DBB1_REG_BASE+0x78) #define CR_FSWEEP (DBB1_REG_BASE+0x7A) #define CR_FSWEEP_SEL (DBB1_REG_BASE+0x7B) #define BYPASS_DC (DBB1_REG_BASE+0x80) #define BYPASS_N_A1 (DBB1_REG_BASE+0x80) #define BYPASS_N_A2 (DBB1_REG_BASE+0x80) #define BYPASS_IMAGE_REJ1 (DBB1_REG_BASE+0x80) #define BYPASS_ACI_REJ_NTSC (DBB1_REG_BASE+0x80) #define A_BP_OUT_X2 (DBB1_REG_BASE+0x80) #define BYPASS_A_DC (DBB1_REG_BASE+0x81) #define BYPASS_A_BPF (DBB1_REG_BASE+0x81) #define AD_SIGNED_UNSIGNED (DBB1_REG_BASE+0x81) #define VD_SIGNED_UNSIGNED (DBB1_REG_BASE+0x81) #define BYPASS_N_A3 (DBB1_REG_BASE+0x81) #define BYPASS_IMAGE_REJ2 (DBB1_REG_BASE+0x81) #define DC_C (DBB1_REG_BASE+0x82) #define A_DC_C (DBB1_REG_BASE+0x83) #define N_A1_C0_L (DBB1_REG_BASE+0x84) #define N_A1_C0_H (DBB1_REG_BASE+0x85) #define N_A1_C1_L (DBB1_REG_BASE+0x86) #define N_A1_C1_H (DBB1_REG_BASE+0x87) #define N_A1_C2_L (DBB1_REG_BASE+0x88) #define N_A1_C2_H (DBB1_REG_BASE+0x89) #define N_A2_C0_L (DBB1_REG_BASE+0x8A) #define N_A2_C0_H (DBB1_REG_BASE+0x8B) #define N_A2_C1_L (DBB1_REG_BASE+0x8C) #define N_A2_C1_H (DBB1_REG_BASE+0x8D) #define N_A2_C2_L (DBB1_REG_BASE+0x8E) #define N_A2_C2_H (DBB1_REG_BASE+0x8F) #define AN_C0_L (DBB1_REG_BASE+0x90) #define AN_C0_H (DBB1_REG_BASE+0x91) #define AN_C1_L (DBB1_REG_BASE+0x92) #define AN_C1_H (DBB1_REG_BASE+0x93) #define AN_C2_L (DBB1_REG_BASE+0x94) #define AN_C2_H (DBB1_REG_BASE+0x95) #define SOS11_C0_L (DBB1_REG_BASE+0x96) #define SOS11_C0_H (DBB1_REG_BASE+0x97) #define SOS11_C1_L (DBB1_REG_BASE+0x98) #define SOS11_C1_H (DBB1_REG_BASE+0x99) #define SOS11_C2_L (DBB1_REG_BASE+0x9A) #define SOS11_C2_H (DBB1_REG_BASE+0x9B) #define SOS11_C3_L (DBB1_REG_BASE+0x9C) #define SOS11_C3_H (DBB1_REG_BASE+0x9D) #define SOS11_C4_L (DBB1_REG_BASE+0x9E) #define SOS11_C4_H (DBB1_REG_BASE+0x9F) #define SOS12_C0_L (DBB1_REG_BASE+0xA0) #define SOS12_C0_H (DBB1_REG_BASE+0xA1) #define SOS12_C1_L (DBB1_REG_BASE+0xA2) #define SOS12_C1_H (DBB1_REG_BASE+0xA3) #define SOS12_C2_L (DBB1_REG_BASE+0xA4) #define SOS12_C2_H (DBB1_REG_BASE+0xA5) #define N_A3_C0_L (DBB1_REG_BASE+0xA6) #define N_A3_C0_H (DBB1_REG_BASE+0xA7) #define N_A3_C1_L (DBB1_REG_BASE+0xA8) #define N_A3_C1_H (DBB1_REG_BASE+0xA9) #define N_A3_C2_L (DBB1_REG_BASE+0xAA) #define N_A3_C2_H (DBB1_REG_BASE+0xAB) #define N_A4_C0_L (DBB1_REG_BASE+0xAC) #define N_A4_C0_H (DBB1_REG_BASE+0xAD) #define N_A4_C1_L (DBB1_REG_BASE+0xAE) #define N_A4_C1_H (DBB1_REG_BASE+0xAF) #define N_A4_C2_L (DBB1_REG_BASE+0xB0) #define N_A4_C2_H (DBB1_REG_BASE+0xB1) #define SOS12_C3_L (DBB1_REG_BASE+0xB2) #define SOS12_C3_H (DBB1_REG_BASE+0xB3) #define SOS12_C4_L (DBB1_REG_BASE+0xB4) #define SOS12_C4_H (DBB1_REG_BASE+0xB5) #define SOS21_C0_L (DBB1_REG_BASE+0xB6) #define SOS21_C0_H (DBB1_REG_BASE+0xB7) #define SOS21_C1_L (DBB1_REG_BASE+0xB8) #define SOS21_C1_H (DBB1_REG_BASE+0xB9) #define SOS21_C2_L (DBB1_REG_BASE+0xBA) #define SOS21_C2_H (DBB1_REG_BASE+0xBB) #define SOS21_C3_L (DBB1_REG_BASE+0xBC) #define SOS21_C3_H (DBB1_REG_BASE+0xBD) #define SOS21_C4_L (DBB1_REG_BASE+0xBE) #define SOS21_C4_H (DBB1_REG_BASE+0xBF) #define SOS22_C0_L (DBB1_REG_BASE+0xC0) #define SOS22_C0_H (DBB1_REG_BASE+0xC1) #define SOS22_C1_L (DBB1_REG_BASE+0xC2) #define SOS22_C1_H (DBB1_REG_BASE+0xC3) #define SOS22_C2_L (DBB1_REG_BASE+0xC4) #define SOS22_C2_H (DBB1_REG_BASE+0xC5) #define SOS22_C3_L (DBB1_REG_BASE+0xC6) #define SOS22_C3_H (DBB1_REG_BASE+0xC7) #define SOS22_C4_L (DBB1_REG_BASE+0xC8) #define SOS22_C4_H (DBB1_REG_BASE+0xC9) #define SOS31_C0_L (DBB1_REG_BASE+0xCA) #define SOS31_C0_H (DBB1_REG_BASE+0xCB) #define SOS31_C1_L (DBB1_REG_BASE+0xCC) #define SOS31_C1_H (DBB1_REG_BASE+0xCD) #define SOS31_C2_L (DBB1_REG_BASE+0xCE) #define SOS31_C2_H (DBB1_REG_BASE+0xCF) #define SOS31_C3_L (DBB1_REG_BASE+0xD0) #define SOS31_C3_H (DBB1_REG_BASE+0xD1) #define SOS31_C4_L (DBB1_REG_BASE+0xD2) #define SOS31_C4_H (DBB1_REG_BASE+0xD3) #define SOS32_C0_L (DBB1_REG_BASE+0xD4) #define SOS32_C0_H (DBB1_REG_BASE+0xD5) #define SOS32_C1_L (DBB1_REG_BASE+0xD6) #define SOS32_C1_H (DBB1_REG_BASE+0xD7) #define SOS32_C2_L (DBB1_REG_BASE+0xD8) #define SOS32_C2_H (DBB1_REG_BASE+0xD9) #define SOS32_C3_L (DBB1_REG_BASE+0xDA) #define SOS32_C3_H (DBB1_REG_BASE+0xDB) #define SOS32_C4_L (DBB1_REG_BASE+0xDC) #define SOS32_C4_H (DBB1_REG_BASE+0xDD) #define SOS33_C0_L (DBB1_REG_BASE+0xDE) #define SOS33_C0_H (DBB1_REG_BASE+0xDF) #define SOS33_C1_L (DBB1_REG_BASE+0xE0) #define SOS33_C1_H (DBB1_REG_BASE+0xE1) #define SOS33_C2_L (DBB1_REG_BASE+0xE2) #define SOS33_C2_H (DBB1_REG_BASE+0xE3) #define SOS33_C3_L (DBB1_REG_BASE+0xE4) #define SOS33_C3_H (DBB1_REG_BASE+0xE5) #define SOS33_C4_L (DBB1_REG_BASE+0xE6) #define SOS33_C4_H (DBB1_REG_BASE+0xE7) #define ZERO_OVMD_DET (DBB1_REG_BASE+0xF4) #define CR_PD_IMAG_INV (DBB1_REG_BASE+0xF4) #define LEVEL_SENSE_PEAK_IN_SEL (DBB1_REG_BASE+0xF4) #define VAGC_PEAK_IN_SEL (DBB1_REG_BASE+0xF4) #define LEVEL_SENSE_OUT_SEL (DBB1_REG_BASE+0xF4) #define BYPASS_V_ACI_BPF4LS (DBB1_REG_BASE+0xF4) #define VIF_DBB1_RESERVED_0 (DBB1_REG_BASE+0xF4) #define VIF_DBB1_RESERVED_1 (DBB1_REG_BASE+0xF6) #define VIF_DBB1_RESERVED_2 (DBB1_REG_BASE+0xF8) #define FIRMWARE_VERSION_L (DBB1_REG_BASE+0xFA) #define FIRMWARE_VERSION_H (DBB1_REG_BASE+0xFB) #define VIF_DBB1_READ0 (DBB1_REG_BASE+0xFC) #define VIF_DBB1_READ1 (DBB1_REG_BASE+0xFE) ///////////////////////////////////////////////////////// // [DBB2 bank register] ///////////////////////////////////////////////////////// #define AGC_ENABLE (DBB2_REG_BASE+0x00) #define AGC_MODE (DBB2_REG_BASE+0x00) #define AGC_MEAN_SEL (DBB2_REG_BASE+0x00) #define AGC_GAIN_SLOPE (DBB2_REG_BASE+0x00) #define AGC_VSYNC_ENA (DBB2_REG_BASE+0x00) #define AGC_VSYNC_ENB (DBB2_REG_BASE+0x00) #define AGC_VSYNC_SEL (DBB2_REG_BASE+0x00) #define AGC_VSYNC_POL (DBB2_REG_BASE+0x01) #define AGC_IN_SEL (DBB2_REG_BASE+0x01) #define AGC_ABS_DATA_IN_SEL (DBB2_REG_BASE+0x01) #define AGC_DBB_VVGA_SEL (DBB2_REG_BASE+0x01) #define AGC_DBB_AVGA_SEL (DBB2_REG_BASE+0x01) #define AGC_VSYNC_PULSE (DBB2_REG_BASE+0x01) #define AGC_LINE_CNT_L (DBB2_REG_BASE+0x02) #define AGC_LINE_CNT_H (DBB2_REG_BASE+0x03) #define AGC_PORCH_CNT_L (DBB2_REG_BASE+0x04) #define AGC_PORCH_CNT_H (DBB2_REG_BASE+0x05) #define AGC_PEAK_CNT_L (DBB2_REG_BASE+0x06) #define AGC_PEAK_CNT_H (DBB2_REG_BASE+0x07) #define AGC_REF (DBB2_REG_BASE+0x08) #define AGC_K (DBB2_REG_BASE+0x0A) #define AGC_OFFSET (DBB2_REG_BASE+0x0B) #define AGC_PGA1_OREN (DBB2_REG_BASE+0x0C) #define AGC_PGA2_OREN (DBB2_REG_BASE+0x0C) #define AGC_VGA_OREN (DBB2_REG_BASE+0x0C) #define AGC_DBB_VVGA_OREN (DBB2_REG_BASE+0x0C) #define AAGC_DBB_VVGA_OREN (DBB2_REG_BASE+0x0C) #define AGC_PGA1_OV (DBB2_REG_BASE+0x0E) #define AGC_PGA2_OV (DBB2_REG_BASE+0x0F) #define AGC_VGA_OV_L (DBB2_REG_BASE+0x10) #define AGC_VGA_OV_H (DBB2_REG_BASE+0x11) #define AGC_PGA1_MIN (DBB2_REG_BASE+0x12) #define AGC_PGA1_MAX (DBB2_REG_BASE+0x13) #define AGC_PGA2_MIN (DBB2_REG_BASE+0x14) #define AGC_PGA2_MAX (DBB2_REG_BASE+0x15) #define AGC_VGA_MIN_L (DBB2_REG_BASE+0x16) #define AGC_VGA_MIN_H (DBB2_REG_BASE+0x17) #define AGC_VGA_MAX_L (DBB2_REG_BASE+0x18) #define AGC_VGA_MAX_H (DBB2_REG_BASE+0x19) #define AGC_DBB_VVGA_OV_L (DBB2_REG_BASE+0x1A) #define AGC_DBB_VVGA_OV_H (DBB2_REG_BASE+0x1B) #define AAGC_DBB_VVGA_OV_L (DBB2_REG_BASE+0x1C) #define AAGC_DBB_VVGA_OV_H (DBB2_REG_BASE+0x1D) #define DBB2_LOAD (DBB2_REG_BASE+0x1E) #define AGC_MEAN0 (DBB2_REG_BASE+0x20) #define AGC_MEAN16 (DBB2_REG_BASE+0x22) #define AGC_MEAN256 (DBB2_REG_BASE+0x24) #define AGC_DIFF (DBB2_REG_BASE+0x26) #define AGC_VGA (DBB2_REG_BASE+0x28) #define AGC_PGA1A (DBB2_REG_BASE+0x2A) #define AGC_PGA2A (DBB2_REG_BASE+0x2B) #define AGC_PGA1B (DBB2_REG_BASE+0x2C) #define AGC_PGA2B (DBB2_REG_BASE+0x2D) #define AGC_PGA1C (DBB2_REG_BASE+0x2E) #define AGC_PGA2C (DBB2_REG_BASE+0x2F) #define AGC_VSYNC_IN (DBB2_REG_BASE+0x30) #define AGC_HS_FOUND (DBB2_REG_BASE+0x30) #define AGC_MAX_MEAN (DBB2_REG_BASE+0x31) #define LEVEL_SENSE_TUNER_VGA (DBB2_REG_BASE+0x32) #define LEVEL_SENSE_MEAN0 (DBB2_REG_BASE+0x34) #define LEVEL_SENSE_MEAN16 (DBB2_REG_BASE+0x36) #define LEVEL_SENSE_MEAN256 (DBB2_REG_BASE+0x38) #define LEVEL_SENSE_DIFF (DBB2_REG_BASE+0x3A) #define LEVEL_SENSE_MAX_MEAN (DBB2_REG_BASE+0x3C) #define LEVEL_SENSE_LOCK (DBB2_REG_BASE+0x3E) #define LEVEL_SENSE_DIFF_AVG (DBB2_REG_BASE+0x40) #define AGC_VGA_THR (DBB2_REG_BASE+0x46) #define AGC_VGA_BASE (DBB2_REG_BASE+0x48) #define AGC_VGA_OFFS (DBB2_REG_BASE+0x49) #define BYPASS_V_ACI_BPF4AGC (DBB2_REG_BASE+0x4A) #define BYPASS_A_ACI_BPF (DBB2_REG_BASE+0x4A) #define BYPASS_VSPUR_REJ (DBB2_REG_BASE+0x4A) #define BYPASS_ASPUR_REJ (DBB2_REG_BASE+0x4A) #define RATE_INV (DBB2_REG_BASE+0x4A) #define CR_RATE_INV (DBB2_REG_BASE+0x4B) #define AGCSOS_BYPASS (DBB2_REG_BASE+0x4C) #define AGCSOS_COEF0 (DBB2_REG_BASE+0x4E) #define AGCSOS_COEF1 (DBB2_REG_BASE+0x50) #define AGCSOS_COEF2 (DBB2_REG_BASE+0x52) #define AGCSOS_COEF3 (DBB2_REG_BASE+0x54) #define AGCSOS_COEF4 (DBB2_REG_BASE+0x56) #define IF_RATE (DBB2_REG_BASE+0x58) #define V_DC_FREEZE (DBB2_REG_BASE+0x5C) #define A_DC_FREEZE (DBB2_REG_BASE+0x5C) #define V_ACI_BPF_SEL (DBB2_REG_BASE+0x5C) #define A_ACI_BPF_SEL (DBB2_REG_BASE+0x5C) #define ACI_REJ_NTSC_SEL (DBB2_REG_BASE+0x5C) #define A_LPF_BG_SEL (DBB2_REG_BASE+0x5C) #define A_DAGC_SEL (DBB2_REG_BASE+0x5C) #define FILTER_DEBUG_SEL (DBB2_REG_BASE+0x5D) #define BYPASS_V_NOTCH_T1 (DBB2_REG_BASE+0x5E) #define BYPASS_V_SOS_T1 (DBB2_REG_BASE+0x5E) #define BYPASS_A_NOTCH_T1 (DBB2_REG_BASE+0x5E) #define BYPASS_A_SOS_T1 (DBB2_REG_BASE+0x5E) #define BYPASS_CO_A_REJ (DBB2_REG_BASE+0x5E) #define BYPASS_CO_A_REJ_NTSC (DBB2_REG_BASE+0x5E) #define BYPASS_A_NOTCH (DBB2_REG_BASE+0x5E) #define BYPASS_A_SOS (DBB2_REG_BASE+0x5E) #define BYPASS_2ND_A_BP (DBB2_REG_BASE+0x5F) #define BYPASS_A_LPF_BG (DBB2_REG_BASE+0x5F) #define V_NOTCH_T1_COEF0 (DBB2_REG_BASE+0x60) #define V_NOTCH_T1_COEF1 (DBB2_REG_BASE+0x62) #define V_NOTCH_T1_COEF2 (DBB2_REG_BASE+0x64) #define V_SOS_T1_COEF0 (DBB2_REG_BASE+0x66) #define V_SOS_T1_COEF1 (DBB2_REG_BASE+0x68) #define V_SOS_T1_COEF2 (DBB2_REG_BASE+0x6A) #define V_SOS_T1_COEF3 (DBB2_REG_BASE+0x6C) #define V_SOS_T1_COEF4 (DBB2_REG_BASE+0x6E) #define A_NOTCH_T1_COEF0 (DBB2_REG_BASE+0x70) #define A_NOTCH_T1_COEF1 (DBB2_REG_BASE+0x72) #define A_NOTCH_T1_COEF2 (DBB2_REG_BASE+0x74) #define A_SOS_T1_COEF0 (DBB2_REG_BASE+0x76) #define A_SOS_T1_COEF1 (DBB2_REG_BASE+0x78) #define A_SOS_T1_COEF2 (DBB2_REG_BASE+0x7A) #define A_SOS_T1_COEF3 (DBB2_REG_BASE+0x7C) #define A_SOS_T1_COEF4 (DBB2_REG_BASE+0x7E) #define A_SOS1_COEF0 (DBB2_REG_BASE+0x86) #define A_SOS1_COEF1 (DBB2_REG_BASE+0x88) #define A_SOS1_COEF2 (DBB2_REG_BASE+0x8A) #define A_SOS1_COEF3 (DBB2_REG_BASE+0x8C) #define A_SOS1_COEF4 (DBB2_REG_BASE+0x8E) #define EQFIR_COEF_ADDR (DBB2_REG_BASE+0x90) #define EQFIR_COEF_CTRL (DBB2_REG_BASE+0x91) #define EQFIR_COEF_WD (DBB2_REG_BASE+0x92) #define EQFIR_COEF_WR (DBB2_REG_BASE+0x93) #define EQFIR_COEF_RD (DBB2_REG_BASE+0x94) #define BYPASS_EQFIR (DBB2_REG_BASE+0x96) #define VIF_COEF_WR_SEL (DBB2_REG_BASE+0x96) #define IMAGE_REJ1_SEL (DBB2_REG_BASE+0x98) #define IMAGE_REJ_IIR_SEL (DBB2_REG_BASE+0x98) #define N_A1_IN_SEL (DBB2_REG_BASE+0x98) #define LEVEL_SENSE_LOCK_CNT (DBB2_REG_BASE+0x9A) #define LEVEL_SENSE_DIFF_AVG_TH (DBB2_REG_BASE+0x9C) #define AGC_VGA1_HILIM (DBB2_REG_BASE+0x9E) #define AAGC_ENABLE (DBB2_REG_BASE+0xA0) #define AAGC_PGA1_IGN_PGA2 (DBB2_REG_BASE+0xA0) #define AAGC_PGA2_IGN_PGA1 (DBB2_REG_BASE+0xA0) #define AAGC_PEAK_MEAN_SEL (DBB2_REG_BASE+0xA0) #define AAGC_LINE_CNT (DBB2_REG_BASE+0xA2) #define AAGC_PGA1_OREN (DBB2_REG_BASE+0xA4) #define AAGC_PGA2_OREN (DBB2_REG_BASE+0xA4) #define AAGC_VPGA1_OREN (DBB2_REG_BASE+0xA4) #define AAGC_VPGA2_OREN (DBB2_REG_BASE+0xA4) #define AAGC_DEC (DBB2_REG_BASE+0xA5) #define AAGC_PGA1_OV (DBB2_REG_BASE+0xA6) #define AAGC_PGA2_OV (DBB2_REG_BASE+0xA7) #define AAGC_PGA1_MIN (DBB2_REG_BASE+0xA8) #define AAGC_PGA1_MAX (DBB2_REG_BASE+0xA9) #define AAGC_PGA2_MIN (DBB2_REG_BASE+0xAA) #define AAGC_PGA2_MAX (DBB2_REG_BASE+0xAB) #define AAGC_MEAN_MIN (DBB2_REG_BASE+0xAC) #define AAGC_MEAN_MAX (DBB2_REG_BASE+0xAD) #define AAGC_MEAN (DBB2_REG_BASE+0xAE) #define AAGC_PEAKMEAN (DBB2_REG_BASE+0xB0) #define AAGC_PGA1 (DBB2_REG_BASE+0xB2) #define AAGC_PGA2 (DBB2_REG_BASE+0xB3) #define AAGC_CNT (DBB2_REG_BASE+0xB4) #define LEVEL_SENSE_EN (DBB2_REG_BASE+0xB8) #define LEVLE_SENSE_MOD_TYPE (DBB2_REG_BASE+0xB8) #define LEVEL_SENSE_MODE (DBB2_REG_BASE+0xB9) #define LEVEL_SENSE_VGA_OREN (DBB2_REG_BASE+0xB9) #define LEVEL_SENSE_MEAN_SEL (DBB2_REG_BASE+0xBA) #define LEVEL_SENSE_BYPASS (DBB2_REG_BASE+0xBB) #define LEVEL_SENSE_DVGA_OREN_SEL (DBB2_REG_BASE+0xBB) #define LEVEL_SENSE_SYNC_HEIGHT (DBB2_REG_BASE+0xBC) #define LEVEL_SENSE_REF (DBB2_REG_BASE+0xBE) #define ACI_DET_EN (DBB2_REG_BASE+0xC0) #define ACI_DET_MOD_TYPE (DBB2_REG_BASE+0xC0) #define ACI_DET_VAGC_MODE (DBB2_REG_BASE+0xC1) #define ACI_DET_SOS_BYPASS (DBB2_REG_BASE+0xC1) #define ACI_DET_SYNC_HEIGHT (DBB2_REG_BASE+0xC2) #define ACI_DET_VAGC_PORCH_CNT (DBB2_REG_BASE+0xC4) #define ACI_DET_VAGC_LINE_CNT (DBB2_REG_BASE+0xC6) #define ACI_DET_VAGA_PEAK_CNT (DBB2_REG_BASE+0xC8) #define ACI_DET_VAGC_OFFSET (DBB2_REG_BASE+0xCA) #define ACI_DET_SOS_COEF0 (DBB2_REG_BASE+0xCC) #define ACI_DET_SOS_COEF1 (DBB2_REG_BASE+0xCE) #define ACI_DET_SOS_COEF2 (DBB2_REG_BASE+0xD0) #define ACI_DET_SOS_COEF3 (DBB2_REG_BASE+0xD2) #define ACI_DET_SOS_COEF4 (DBB2_REG_BASE+0xD4) #define ACI_DET_MEAN0 (DBB2_REG_BASE+0xD6) #define ACI_DET_MEAN16 (DBB2_REG_BASE+0xD8) #define ACI_DET_MEAN256 (DBB2_REG_BASE+0xDA) #define ACI_DET_IN_SEL (DBB2_REG_BASE+0xDC) #define ACI_DET_PEAKIN_SEL (DBB2_REG_BASE+0xDC) #define ACI_DET_MEAN_SEL (DBB2_REG_BASE+0xDD) #define ACI_DET_DETECT_THR (DBB2_REG_BASE+0xDE) #define ACI_DET_UNDETECT_THR (DBB2_REG_BASE+0xDF) #define DEBUG_PORT (DBB2_REG_BASE+0xE0) #define DEBUG_CLK_SEL (DBB2_REG_BASE+0xE0) #define DEBUG_CLK_INV (DBB2_REG_BASE+0xE0) #define DEBUG_SIGNED_UNSIGNED (DBB2_REG_BASE+0xE0) #define DEBUG_MODULE (DBB2_REG_BASE+0xE1) #define DEBUG_SWITCH (DBB2_REG_BASE+0xE1) #define DEBUG_V_A (DBB2_REG_BASE+0xE1) #define TESTBUS_INV (DBB2_REG_BASE+0xE1) #define DEBUG2_EN (DBB2_REG_BASE+0xE1) #define DEBUG_FREQ_L (DBB2_REG_BASE+0xE2) #define DEBUG_FREQ_H (DBB2_REG_BASE+0xE3) #define LEVEL_SENSE_LINE_CNT (DBB2_REG_BASE+0xE4) #define LEVEL_SENSE_PORCH_CNT (DBB2_REG_BASE+0xE6) #define LEVEL_SENSE_PEAK_CNT (DBB2_REG_BASE+0xE8) #define LEVEL_SENSE_K (DBB2_REG_BASE+0xEA) #define LEVEL_SENSE_VGA_OV (DBB2_REG_BASE+0xEC) #define LEVEL_SENSE_ADJ_SEL (DBB2_REG_BASE+0xEE) #define LEVEL_SENSE_ADJ_SW_MODE (DBB2_REG_BASE+0xEE) #define LEVEL_SENSE_DIFF_AVG_LOAD (DBB2_REG_BASE+0xEF) #define LEVEL_SENSE_DIFF_AVG_INI (DBB2_REG_BASE+0xF0) #define LEVEL_SENSE_OFFSET (DBB2_REG_BASE+0xF2) #define VIF_DBB2_RESERVED_1 (DBB2_REG_BASE+0xF6) #define VIF_DBB2_RESERVED_2 (DBB2_REG_BASE+0xF8) #define VIF_DBB2_RESERVED_3 (DBB2_REG_BASE+0xFA) #define VIF_DBB2_READ0 (DBB2_REG_BASE+0xFC) #define VIF_DBB2_READ1 (DBB2_REG_BASE+0xFE) ////////////////////////////////////////////////////////// // [DBB3 bank register] ////////////////////////////////////////////////////////// #define DAGC1_ENABLE (DBB3_REG_BASE+0x00) #define DAGC1_BYPASS (DBB3_REG_BASE+0x00) #define DAGC1_GAIN0_FB_EN (DBB3_REG_BASE+0x00) #define DAGC1_DL_BYPASS (DBB3_REG_BASE+0x00) #define DAGC2_ENABLE (DBB3_REG_BASE+0x01) #define DAGC2_BYPASS (DBB3_REG_BASE+0x01) #define DAGC2_GAIN0_FB_EN (DBB3_REG_BASE+0x01) #define DAGC2_DL_BYPASS (DBB3_REG_BASE+0x01) #define DAGC1_GAIN_OVERWRITE_L (DBB3_REG_BASE+0x02) #define DAGC1_GAIN_OVERWRITE_H (DBB3_REG_BASE+0x03) #define DAGC1_OREN (DBB3_REG_BASE+0x03) #define DAGC2_GAIN_OVERWRITE_L (DBB3_REG_BASE+0x04) #define DAGC2_GAIN_OVERWRITE_H (DBB3_REG_BASE+0x05) #define DAGC2_OREN (DBB3_REG_BASE+0x05) #define DAGC1_REF (DBB3_REG_BASE+0x06) #define DAGC2_REF (DBB3_REG_BASE+0x07) #define DAGC1_LEVEL_SHIFT (DBB3_REG_BASE+0x08) #define DAGC2_LEVEL_SHIFT (DBB3_REG_BASE+0x09) #define DAGC1_RATIO (DBB3_REG_BASE+0x0A) #define DAGC2_RATIO (DBB3_REG_BASE+0x0B) #define DAGC1_PEAK_CNT_L (DBB3_REG_BASE+0x0C) #define DAGC1_PEAK_CNT_H (DBB3_REG_BASE+0x0D) #define DAGC2_PEAK_CNT_L (DBB3_REG_BASE+0x0E) #define DAGC2_PEAK_CNT_H (DBB3_REG_BASE+0x0F) #define DAGC1_PORCH_CNT_L (DBB3_REG_BASE+0x10) #define DAGC1_PORCH_CNT_H (DBB3_REG_BASE+0x11) #define DAGC2_PORCH_CNT_L (DBB3_REG_BASE+0x12) #define DAGC2_PORCH_CNT_H (DBB3_REG_BASE+0x13) #define DAGC1_MEAN (DBB3_REG_BASE+0x14) #define DAGC1_VAR (DBB3_REG_BASE+0x16) #define DAGC2_MEAN (DBB3_REG_BASE+0x18) #define DAGC2_VAR (DBB3_REG_BASE+0x1A) #define DAGC1_GAIN (DBB3_REG_BASE+0x1C) #define DAGC2_GAIN (DBB3_REG_BASE+0x1E) #define DAGC1_SYNCHEIGHT (DBB3_REG_BASE+0x20) #define DAGC1_VSYNC (DBB3_REG_BASE+0x21) #define DAGC2_SYNCHEIGHT (DBB3_REG_BASE+0x22) #define DAGC2_VSYNC (DBB3_REG_BASE+0x23) #define DAGC1_LPF_DELAY_0 (DBB3_REG_BASE+0x24) #define DAGC2_LPF_DELAY_0 (DBB3_REG_BASE+0x26) #define DAGC1_OFFSET (DBB3_REG_BASE+0x28) #define DAGC2_OFFSET (DBB3_REG_BASE+0x29) #define CR_KPKI_SPEEDUP_EN (DBB3_REG_BASE+0x2A) #define CR_INV2_EN (DBB3_REG_BASE+0x2A) #define CR_DET_CARRIER_DRIFT (DBB3_REG_BASE+0x2B) #define CR_CSD_TH_LOW (DBB3_REG_BASE+0x2C) #define CR_CSD_TH_HIGH (DBB3_REG_BASE+0x2E) #define CR_CSD_Q_PART_LEN (DBB3_REG_BASE+0x30) #define CR_LOCK_LEAKY_FF_I_3_LEN (DBB3_REG_BASE+0x32) #define CR_K_SPEEDUP (DBB3_REG_BASE+0x34) #define CR_LOCK_LEAKY_FF_I_3 (DBB3_REG_BASE+0x36) #define CR_LOCK_LEAKY_FF_Q_3 (DBB3_REG_BASE+0x38) #define CR_CSD_DET_OUT (DBB3_REG_BASE+0x3A) #define CR_KP_SPEED (DBB3_REG_BASE+0x3E) #define CR_KI_SPEED (DBB3_REG_BASE+0x3E) #define VAGC_VGA_OUT_SEL (DBB3_REG_BASE+0x40) #define VAGC_VGA_PGA_SEL (DBB3_REG_BASE+0x40) #define VAGC_VGA2_OREN (DBB3_REG_BASE+0x40) #define VAGC_VGA2_OV_L (DBB3_REG_BASE+0x42) #define VAGC_VGA2_OV_H (DBB3_REG_BASE+0x43) #define VAGC_VGA2_MIN_L (DBB3_REG_BASE+0x44) #define VAGC_VGA2_MIN_H (DBB3_REG_BASE+0x45) #define VAGC_VGA2_MAX_L (DBB3_REG_BASE+0x46) #define VAGC_VGA2_MAX_H (DBB3_REG_BASE+0x47) #define VAGC_LINE_CNT2_L (DBB3_REG_BASE+0x48) #define VAGC_LINE_CNT2_H (DBB3_REG_BASE+0x49) #define VAGC_IF_VGA_L (DBB3_REG_BASE+0x60) #define VAGC_IF_VGA_H (DBB3_REG_BASE+0x61) #define CR_CSD_MA_SEL (DBB3_REG_BASE+0x64) #define CR_JTRDET_IN_SEL (DBB3_REG_BASE+0x64) #define ACI_DET_DETECT_NUM (DBB3_REG_BASE+0x66) #define ACI_DET_UNDETECT_NUM (DBB3_REG_BASE+0x6A) #define ACI_DET_ACI_IDCT (DBB3_REG_BASE+0x6E) #define KPKI_ADJ_TH1_L (DBB3_REG_BASE+0x70) #define KPKI_ADJ_TH1_H (DBB3_REG_BASE+0x72) #define KPKI_ADJ_TH2_L (DBB3_REG_BASE+0x74) #define KPKI_ADJ_TH2_H (DBB3_REG_BASE+0x76) #define KPKI_ADJ_TH3_L (DBB3_REG_BASE+0x78) #define KPKI_ADJ_TH3_H (DBB3_REG_BASE+0x7A) #define CR_KP_ADJ1 (DBB3_REG_BASE+0x7C) #define CR_KI_ADJ1 (DBB3_REG_BASE+0x7C) #define CR_KP_ADJ2 (DBB3_REG_BASE+0x7D) #define CR_KI_ADJ2 (DBB3_REG_BASE+0x7D) #define CR_KP_ADJ3 (DBB3_REG_BASE+0x7E) #define CR_KI_ADJ3 (DBB3_REG_BASE+0x7E) #define KPKI_ADJ_EN (DBB3_REG_BASE+0x7F) #define CR_KPKI_GEAR (DBB3_REG_BASE+0x7F) #define ADAGC_ENABLE (DBB3_REG_BASE+0x80) #define ADAGC_BYPASS (DBB3_REG_BASE+0x80) #define ADAGC_PEAK_MEAN_SEL (DBB3_REG_BASE+0x80) #define ADAGC_K (DBB3_REG_BASE+0x81) #define ADAGC_CNT (DBB3_REG_BASE+0x82) #define ADAGC_DEC (DBB3_REG_BASE+0x86) #define ADAGC_LINE_CNT (DBB3_REG_BASE+0x87) #define ADAGC_REF (DBB3_REG_BASE+0x88) #define ADAGC_GAIN_OREN (DBB3_REG_BASE+0x8A) #define ADAGC_GAIN_OV (DBB3_REG_BASE+0x8C) #define ADAGC_MEAN (DBB3_REG_BASE+0xA0) #define ADAGC_PEAK (DBB3_REG_BASE+0xA1) #define ADAGC_GAIN (DBB3_REG_BASE+0xA2) #define AGC_HUM_SW_RST (DBB3_REG_BASE+0xA4) #define AGC_HUM_CNT_MAX (DBB3_REG_BASE+0xA4) #define AGC_HUM_ERR_THR (DBB3_REG_BASE+0xA5) #define AGC_HUM_DET_LIM (DBB3_REG_BASE+0xA6) #define AGC_HUM_DETECT (DBB3_REG_BASE+0xA7) #define AGC_NUM_HUM_ERR (DBB3_REG_BASE+0xA8) #define BYPASS_N_A5 (DBB3_REG_BASE+0xAA) #define N_A5_C0_L (DBB3_REG_BASE+0xAC) #define N_A5_C0_H (DBB3_REG_BASE+0xAD) #define N_A5_C1_L (DBB3_REG_BASE+0xAE) #define N_A5_C1_H (DBB3_REG_BASE+0xAF) #define N_A5_C2_L (DBB3_REG_BASE+0xB0) #define N_A5_C2_H (DBB3_REG_BASE+0xB1) #define AGC_VGA2_LOLIM (DBB3_REG_BASE+0xB2) #define DEBUG_PORT2 (DBB3_REG_BASE+0xDE) #define FILTER_DBG_SEL2 (DBB3_REG_BASE+0xDF) #define FILTER_RAM_FREEZE (DBB3_REG_BASE+0xE0) #define FILTER_RAM_ADDR (DBB3_REG_BASE+0xE2) #define F144_RAM_OUT (DBB3_REG_BASE+0xE4) #define F43_RAM_OUT (DBB3_REG_BASE+0xE6) #define VIF_DBB3_RESERVED_0 (DBB3_REG_BASE+0xF4) #define VIF_DBB3_RESERVED_1 (DBB3_REG_BASE+0xF6) #define VIF_DBB3_RESERVED_2 (DBB3_REG_BASE+0xF8) #define VIF_DBB3_RESERVED_3 (DBB3_REG_BASE+0xFA) #define VIF_DBB3_READ0 (DBB3_REG_BASE+0xFC) #define VIF_DBB3_READ1 (DBB3_REG_BASE+0xFE) #endif //_REGVIF_H_