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MStar hereby reserves the // rights to any and all damages, losses, costs and expenses resulting therefrom. // //////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////////// /// /// @file drvHVD.h /// @brief HVD Driver Interface /// @author MStar Semiconductor Inc. /////////////////////////////////////////////////////////////////////////////////////////////////// #ifndef _DRV_HVD_DEF_H_ #define _DRV_HVD_DEF_H_ #include "drvHVD_Common.h" //------------------------------------------------------------------------------------------------- // Driver Capability //------------------------------------------------------------------------------------------------- // HW capability #define HVD_HW_SVD 1 #define HVD_HW_HVD 2 #if defined(CHIP_T2) #define HVD_HW_VERSION HVD_HW_SVD #else #define HVD_HW_VERSION HVD_HW_HVD #endif //------------------------------------------------------------------------------------------------- // Macro and Define //------------------------------------------------------------------------------------------------- // Feature switch #if defined(REDLION_LINUX_KERNEL_ENVI) #define HVD_ENABLE_MUTEX_PROTECT 0 #define HVD_ENABLE_MIU_RST_PROTECT 1 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 #define HVD_ENABLE_MSOS_MIU1_BASE 0 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 #define HVD_ENABLE_TIME_MEASURE 0 #define HVD_ENABLE_REINIT_FAILED 1 #define HVD_ENABLE_RV_FEATURE 0 #else #define HVD_ENABLE_MUTEX_PROTECT 1 #define HVD_ENABLE_MIU_RST_PROTECT 1 #if 1//defined( MSOS_TYPE_LINUX) #define HVD_ENABLE_AUTO_SET_REG_BASE 1 #else #define HVD_ENABLE_AUTO_SET_REG_BASE 0 #endif #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) #define HVD_ENABLE_PATCH_ISFRAMERDY 0 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 #else #define HVD_ENABLE_PATCH_ISFRAMERDY 1 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 #endif #if defined(MSOS_TYPE_NOS) && (defined(CHIP_T3) || defined(CHIP_T8) || defined(CHIP_J2)) #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 #else #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 #endif #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 #if defined(CHIP_JANUS) #define HVD_ENABLE_MSOS_MIU1_BASE 0 #else #define HVD_ENABLE_MSOS_MIU1_BASE 1 #endif #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 #define HVD_ENABLE_TIME_MEASURE 0 #define HVD_ENABLE_REINIT_FAILED 0 #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) #define HVD_ENABLE_RV_FEATURE 0 #else #define HVD_ENABLE_RV_FEATURE 1 #endif #if defined(CHIP_T12) || \ defined(CHIP_J2) || \ defined(CHIP_A1) || \ defined(CHIP_A2) || \ defined(CHIP_A5) || \ defined(CHIP_A5P) || \ defined(CHIP_A7) || \ defined(CHIP_A3) || \ defined(CHIP_AMETHYST)|| \ defined(CHIP_AGATE) || \ defined(CHIP_EDISON) || \ defined(CHIP_EMERALD)|| \ defined(CHIP_EAGLE) || \ defined(CHIP_EIFFEL) || \ defined(CHIP_NIKE) || \ defined(CHIP_MADISON) || \ defined(CHIP_CLIPPERS) || \ defined(CHIP_MIAMI) || \ defined(CHIP_NUGGET) || \ defined(CHIP_KAISER) || \ defined(CHIP_NIKON) || \ defined(CHIP_EINSTEIN)|| \ defined(CHIP_NAPOLI) || \ defined(CHIP_KERES) || \ defined(CHIP_MONACO) || \ defined(CHIP_MUNICH) #define HVD_ENABLE_MVC 1 #else #define HVD_ENABLE_MVC 0 #endif #endif #if defined(REDLION_LINUX_KERNEL_ENVI) #include "drvHVD_redlion.h" #endif #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) #include "osalHVD_EX.h" #endif #if HVD_ENABLE_MSOS_MIU1_BASE #include "halCHIP.h" #endif #if HVD_ENABLE_BDMA_2_BITSTREAMBUF #include "drvBDMA.h" #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) #endif // debug switch // DEBUG #if defined (REDLION_LINUX_KERNEL_ENVI) #define HVD_PRINT printk #define HVD_ERR printk #elif defined (ANDROID) #include #include #include #ifndef LOGI // android 4.1 rename LOGx to ALOGx #define HVD_PRINT ALOGI #else #define HVD_PRINT LOGI #endif #ifndef LOGE // android 4.1 rename LOGx to ALOGx #define HVD_ERR ALOGE #else #define HVD_ERR LOGE #endif #else #define HVD_PRINT printf #define HVD_ERR printf #endif #define HVD_EX_MSG_MUST(format, args...) \ do \ { \ if (u32UartCtrl & E_HVD_UART_CTRL_MUST) \ { \ HVD_ERR("[HVD][MUST]%s:", __FUNCTION__); \ HVD_ERR(format, ##args); \ } \ } while (0) #define HVD_EX_MSG_ERR(format, args...) \ do \ { \ if (u32UartCtrl & E_HVD_UART_CTRL_ERR) \ { \ HVD_ERR("[HVD][ERR]%s:", __FUNCTION__); \ HVD_ERR(format, ##args); \ } \ } while (0) #if ((defined(CHIP_A1) || defined(CHIP_A7) || defined(CHIP_AMETHYST) || defined(CHIP_EMERALD) || defined(CHIP_NUGGET) || defined(CHIP_NIKON)) && defined (__aeon__)) #define HVD_EX_MSG_INF(format, args...) #define HVD_EX_MSG_DBG(format, args...) #define HVD_EX_MSG_TRACE() #else #define HVD_EX_MSG_INF(format, args...) \ do \ { \ if (u32UartCtrl & E_HVD_UART_CTRL_INFO) \ { \ HVD_PRINT("[HVD][INF]%s:", __FUNCTION__); \ HVD_PRINT(format, ##args); \ } \ } while (0) #define HVD_EX_MSG_DBG(format, args...) \ do \ { \ if (u32UartCtrl & E_HVD_UART_CTRL_DBG) \ { \ HVD_PRINT("[HVD][DBG]%s:", __FUNCTION__); \ HVD_PRINT(format, ##args); \ } \ } while (0) #define HVD_EX_MSG_TRACE() \ do \ { \ if (u32UartCtrl & E_HVD_UART_CTRL_TRACE) \ { \ HVD_PRINT("[HVD][TRA]%s:", __FUNCTION__); \ } \ } while (0) #endif // Configs #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 // Util or Functions #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) #define HVD_LWORD(x) (MS_U16)((x)&0xffff) #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) #define HVD_U32_MAX 0xffffffffUL #define HVD_RV_BROKENBYUS_MASK 0x00800000 #ifdef MSOS_TYPE_LINUX #if HVD_ENABLE_MSOS_SYSTEM_CALL #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme #else #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme #endif #else #define HVD_VA2PA(x) (x) #endif #if defined(REDLION_LINUX_KERNEL_ENVI) #define HVD_PA2VA(x ) (MS_U32)MDrv_SYS_PA2NonCacheSeg((void*)(x)) #else #define HVD_PA2VA(x ) (MS_U32)MS_PA2KSEG1((MS_U32)(x)) #endif #if 0//def memcpy #define HVD_memcpy(x , y , z) memcpy(x, y, z) #else #if 0 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ do { \ MS_U32 i = 0; \ volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ for (i = 0; i < (u32Size); i++) \ { \ Dest[i] = Src[i]; \ } \ }while(0) #else #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ do { \ register unsigned long u32I=0; \ register unsigned long u32Dst = (unsigned long)pDstAddr; \ void * pSrc = (void *)pSrcAddr; \ MS_U32 _u32memsize = u32Size; \ if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ { \ for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ { \ ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ } \ } \ else \ { \ for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ { \ ((volatile unsigned long *)u32Dst)[u32I] = ((volatile unsigned long *)pSrc)[u32I]; \ } \ if((_u32memsize)%4) \ { \ u32Dst += u32I*4; \ pSrc = (void *)((unsigned long)pSrc + u32I*4); \ for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ { \ ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ } \ } \ } \ }while(0) #endif #endif #if HVD_ENABLE_MSOS_SYSTEM_CALL #define HVD_Delay_ms(x) MsOS_DelayTask(x) #define HVD_SYSTEM_DELAY_MS_TYPE 2 #elif defined(REDLION_LINUX_KERNEL_ENVI) #define HVD_Delay_ms(x) msleep(x) //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) #define HVD_SYSTEM_DELAY_MS_TYPE 3 #else #define HVD_Delay_ms(x) \ do { \ volatile MS_U32 ticks=0; \ while( ticks < ( ((MS_U32)(x)) <<13) ) \ { \ ticks++; \ } \ } while(0) #define HVD_SYSTEM_DELAY_MS_TYPE 0 #endif // HVD_ENABLE_MSOS_SYSTEM_CALL #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ do{ \ MS_U32 i = 0; \ MS_U32 j = 0; \ MS_U8* temp = (MS_U8*)addr; \ MS_U8 string[17] ; \ HVD_EX_MSG_DBG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ memset(string , 0 , sizeof(string)); \ for (j = 0; j < (size >> 4); j++) \ { \ if (ascii) \ { \ for (i = 0; i < 16; i++) \ { \ if (*(temp + i) >= 30 && *(temp + i) <= 126) \ string[i] = *(temp + i); \ else \ string[i] = '.'; \ } \ HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ } \ else \ { \ HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ } \ temp += 16; \ } \ HVD_EX_MSG_DBG("0x%08x " , j << 4); \ memset(string , 0 , sizeof(string)); \ for (i = 0; i < (size & 0x0f); i++) \ { \ if (*(temp + i) >= 30 && *(temp + i) <= 126) \ string[i] = *(temp + i); \ else \ string[i] = '.'; \ HVD_EX_MSG_DBG("%02x ", *(MS_U8*)(temp + i)); \ } \ if (ascii) \ { \ for (; i < 16 ; i++) \ HVD_EX_MSG_DBG(" "); \ HVD_EX_MSG_DBG(" %s\n" , string); \ } \ else \ HVD_EX_MSG_DBG("\n"); \ }while(0) #if HVD_ENABLE_MSOS_SYSTEM_CALL #define HVD_GetSysTime_ms() MsOS_GetSystemTime() #define HVD_SYSTEM_CLOCK_TYPE 1 #elif defined(REDLION_LINUX_KERNEL_ENVI) #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() #define HVD_SYSTEM_CLOCK_TYPE 2 #else #define HVD_GetSysTime_ms() 1 #define HVD_SYSTEM_CLOCK_TYPE 0 #endif // MsOS_GetSystemTime #if HVD_ENABLE_MSOS_SYSTEM_CALL #include "asmCPU.h" #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() #define HVD_MEMORY_BARRIER_TYPE 3 #else #if defined (__mips__) #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") #define HVD_MEMORY_BARRIER_TYPE 1 #elif defined (__aeon__) #ifdef __AEONR2__ #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") #define HVD_MEMORY_BARRIER_TYPE 22 #else #if defined( CHIP_T2 ) #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") #define HVD_MEMORY_BARRIER_TYPE 21 #else #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") #define HVD_MEMORY_BARRIER_TYPE 23 #endif #endif #else #define HAL_MEMORY_BARRIER() #define HVD_MEMORY_BARRIER_TYPE 0 #endif #endif #define HVD_DRV_MODE_EXTERNAL_DS_BUFFER (1 << 0) //------------------------------------------------------------------------------------------------- // Type and Structure //------------------------------------------------------------------------------------------------- typedef void (*HVD_ISRCallBack)(MS_U32 u32Sid); typedef enum { E_HVD_RETURN_FAIL=0, E_HVD_RETURN_SUCCESS, E_HVD_RETURN_INVALID_PARAMETER, E_HVD_RETURN_ILLEGAL_ACCESS, E_HVD_RETURN_HARDWARE_BREAKDOWN, E_HVD_RETURN_OUTOF_MEMORY, E_HVD_RETURN_UNSUPPORTED, E_HVD_RETURN_TIMEOUT, E_HVD_RETURN_NOTREADY, E_HVD_RETURN_MEMORY_OVERWIRTE, E_HVD_RETURN_ES_FULL, E_HVD_RETURN_RE_INIT, E_HVD_RETURN_NOT_RUNNING, } HVD_Return; typedef enum { // share memory E_HVD_GDATA_SHARE_MEM=0x1000, // switch //E_HVD_GDATA_SEMAPHORE, E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), // report E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), E_HVD_GDATA_U64PTS, E_HVD_GDATA_DECODE_CNT, E_HVD_GDATA_DATA_ERROR_CNT, E_HVD_GDATA_DEC_ERROR_CNT, E_HVD_GDATA_ERROR_CODE, E_HVD_GDATA_VPU_IDLE_CNT, E_HVD_GDATA_DISP_FRM_INFO, E_HVD_GDATA_DEC_FRM_INFO, E_HVD_GDATA_ES_LEVEL, E_HVD_GDATA_PTS_STC_DIFF, #if HVD_ENABLE_MVC E_HVD_GDATA_DISP_FRM_INFO_SUB, E_HVD_GDATA_DEC_FRM_INFO_SUB, #endif E_HVD_GDATA_HVD_HW_MAX_PIXEL, // user data E_HVD_GDATA_USERDATA_WPTR, E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, E_HVD_GDATA_USERDATA_PACKET_SIZE, E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, // report - modes E_HVD_GDATA_IS_SHOW_ERR_FRM, E_HVD_GDATA_IS_REPEAT_LAST_FIELD, E_HVD_GDATA_IS_ERR_CONCEAL, E_HVD_GDATA_IS_SYNC_ON, E_HVD_GDATA_IS_PLAYBACK_FINISH, E_HVD_GDATA_SYNC_MODE, E_HVD_GDATA_SKIP_MODE, E_HVD_GDATA_DROP_MODE, E_HVD_GDATA_DISPLAY_DURATION, E_HVD_GDATA_FRC_MODE, E_HVD_GDATA_NEXT_PTS, E_HVD_GDATA_DISP_Q_SIZE, E_HVD_GDATA_DISP_Q_PTR, E_HVD_GDATA_NEXT_DISP_FRM_INFO, E_HVD_GDATA_REAL_FRAMERATE, E_HVD_GDATA_IS_ORI_INTERLACE_MODE, E_HVD_GDATA_FRM_PACKING_SEI_DATA, E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE, E_HVD_GDATA_FIELD_PIC_FLAG, E_HVD_GDATA_FW_STATUS_FLAG, // internal control E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), E_HVD_GDATA_IS_I_FRM_FOUND, E_HVD_GDATA_IS_SYNC_START, E_HVD_GDATA_IS_SYNC_REACH, E_HVD_GDATA_FW_VERSION_ID, E_HVD_GDATA_FW_IF_VERSION_ID, E_HVD_GDATA_BBU_Q_NUMB, E_HVD_GDATA_DEC_Q_NUMB, E_HVD_GDATA_DISP_Q_NUMB, E_HVD_GDATA_PTS_Q_NUMB, E_HVD_GDATA_FW_INIT_DONE, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT, E_HVD_GDATA_FW_IQMEM_CTRL, E_HVD_GDATA_FW_FLUSH_STATUS, E_HVD_GDATA_FW_CODEC_TYPE, E_HVD_GDATA_FW_ES_BUF_STATUS, E_HVD_GDATA_TS_SEAMLESS_STATUS, // debug E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), E_HVD_GDATA_GOP_CNT, E_HVD_GDATA_DISP_CNT, E_HVD_GDATA_DROP_CNT, E_HVD_GDATA_DISP_STC, E_HVD_GDATA_VSYNC_CNT, E_HVD_GDATA_MAIN_LOOP_CNT, // AVC E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), E_HVD_GDATA_AVC_LOW_DELAY, E_HVD_GDATA_AVC_VUI_DISP_INFO, //E_HVD_GDATA_AVC_SPS_ADDR, // SRAM E_HVD_GDATA_SRAM=0x2000, //E_HVD_GDATA_AVC_NAL_CNT, // Mailbox or Reg E_HVD_GDATA_MBOX=0x3000, E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) E_HVD_GDATA_ES_READ_PTR, // E_HVD_GDATA_ES_WRITE_PTR, // E_HVD_GDATA_BBU_READ_PTR, // E_HVD_GDATA_BBU_WRITE_PTR, // E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // E_HVD_GDATA_VPU_PC_CNT, // E_HVD_GDATA_ES_QUANTITY, // FW def E_HVD_GDATA_FW_DEF=0x4000, E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, E_HVD_GDATA_FW_DS_BUF_ADDR, E_HVD_GDATA_FW_DS_BUF_SIZE, E_HVD_GDATA_FW_DS_VECTOR_DEPTH, E_HVD_GDATA_FW_DS_INFO_ADDR, E_HVD_GDATA_FW_DS_IS_ENABLED, E_HVD_GDATA_FW_VSYNC_BRIDGE_ADDR, // BBU size // default pitch number // } HVD_GetData; typedef enum { // share memory E_HVD_SDATA_SHARE_MEM = 0x1000, // switch E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100 + E_HVD_SDATA_SHARE_MEM), E_HVD_SDATA_FRAMEBUF_SIZE, E_HVD_SDATA_ERROR_CODE, E_HVD_SDATA_DISP_INFO_TH, E_HVD_SDATA_FW_FLUSH_STATUS, E_HVD_SDATA_DMX_FRAMERATE, E_HVD_SDATA_DMX_FRAMERATEBASE, E_HVD_SDATA_MIU_SEL, // display info //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), // report //E_HVD_SDATA_PTS=0x0200, // internal control //E_HVD_SDATA_IDLE_CNT=0x0300, // debug //E_HVD_SDATA_SKIP_CNT=0x0400, // RM E_HVD_SDATA_RM_PICTURE_SIZES = (0x0500 | E_HVD_SDATA_SHARE_MEM), // SRAM // Mailbox or Reg E_HVD_SDATA_MAILBOX = 0x3000, E_HVD_SDATA_FW_CODE_TYPE = (0x0000 | E_HVD_SDATA_MAILBOX), E_HVD_SDATA_TRIGGER_DISP, E_HVD_SDATA_GET_DISP_INFO_DONE, E_HVD_SDATA_GET_DISP_INFO_START, // FW def E_HVD_SDATA_FW_DEF = 0x4000, E_HVD_SDATA_VIRTUAL_BOX_WIDTH, E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, //modify the state of the frame in DispQueue E_HVD_SDATA_DISPQ_STATUS_VIEW, E_HVD_SDATA_DISPQ_STATUS_DISP, E_HVD_SDATA_DISPQ_STATUS_FREE, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, } HVD_SetData; typedef enum { E_HVD_UART_CTRL_DISABLE = BIT(4), E_HVD_UART_CTRL_ERR = BIT(0), E_HVD_UART_CTRL_INFO = BIT(1), E_HVD_UART_CTRL_DBG = BIT(2), E_HVD_UART_CTRL_FW = BIT(3), E_HVD_UART_CTRL_MUST = BIT(4), E_HVD_UART_CTRL_TRACE = BIT(5), } HVD_Uart_Ctrl; typedef enum { E_HVD_INIT_HW_MASK = BMASK(3:0), ///< HW Type, should same as HVD_Codec_Type in fwHVD_if.h E_HVD_INIT_HW_AVC = BITS(3:0, 0), ///< HW deflaut: AVC 0X00 E_HVD_INIT_HW_AVS = BITS(3:0, 1), ///< HW: AVS 0X01 E_HVD_INIT_HW_RM = BITS(3:0, 2), ///< HW: RM 0X10 E_HVD_INIT_HW_MVC = BITS(3:0, 3), ///< HW: MVC 0x11 E_HVD_INIT_HW_VP8 = BITS(3:0, 4), ///< HW: VP8 0X100 E_HVD_INIT_HW_MJPEG = BITS(3:0, 5), ///< HW: MJPEG 0x101 E_HVD_INIT_HW_VP6 = BITS(3:0, 6), ///< HW: VP6 0x110 E_HVD_INIT_HW_HEVC = BITS(3:0, 7), ///< HW: HEVC 0x111 E_HVD_INIT_HW_VP9 = BITS(3:0, 8), ///< HW: VP9 0x1000 E_HVD_INIT_MAIN_MASK = BMASK(5:4), ///< main type E_HVD_INIT_MAIN_FILE_RAW = BITS(5:4, 0), ///< main type: default: 0X00 E_HVD_INIT_MAIN_FILE_TS = BITS(5:4, 1), ///< main type: 0X01 E_HVD_INIT_MAIN_LIVE_STREAM = BITS(5:4, 2), ///< main type: 0X10 E_HVD_INIT_INPUT_MASK = BMASK(6:6), ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode E_HVD_INIT_INPUT_TSP = BITS(6:6, 0), ///< tsp input( default) E_HVD_INIT_INPUT_DRV = BITS(6:6, 1), ///< driver input E_HVD_INIT_START_CODE_MASK = BMASK(7:7), ///< AVC FILE MODE ONLY: mkv, mp4 container use. E_HVD_INIT_START_CODE_REMAINED = BITS(7:7, 0), ///< start code remained.(Defualt) E_HVD_INIT_START_CODE_REMOVED = BITS(7:7, 1), ///< start code removed. E_HVD_INIT_UTOPIA_ENVI = BIT(8), ///< check MIU sel and set it E_HVD_INIT_DBG_FW = BIT(9), ///< check FW is debug version or not E_HVD_INIT_DUAL_ES_MASK = BMASK(10:10), ///< Dual ES buffer iput. E_HVD_INIT_DUAL_ES_DISABLE = BITS(10:10, 0), ///< Disable Dual ES buffer input. E_HVD_INIT_DUAL_ES_ENABLE = BITS(10:10, 1), ///< Enable Dual ES buffer input. //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. } HVD_Init_Mode_Flag; typedef enum { E_HVD_PLAY_NORMAL, E_HVD_PLAY_PAUSE, E_HVD_PLAY_STEP_DISPLAY, } HVD_Play_Type; typedef enum { E_HVD_ESB_LEVEL_NORMAL = 0, E_HVD_ESB_LEVEL_UNDER = BIT(0), E_HVD_ESB_LEVEL_OVER = BIT(1), } HVD_ESBuf_Level; //----------------------------------------------------------------------------- /// @brief \b Enum \b Name: HVD_FWInputSourceType /// @brief \b Enum \b Description: The type of fw binary input source //----------------------------------------------------------------------------- typedef enum { E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. } HVD_FWInputSourceType; //----------------------------------------------------------------------------- /// @brief \b Enum \b Name: HVD_FB_Reduction_Type /// @brief \b Enum \b Description: The type of frame buffer reduction type //----------------------------------------------------------------------------- typedef enum { E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 } HVD_FBReductionType; typedef enum { E_VDEC_EX_MAIN_VIEW = 0, ///< MVC main view E_VDEC_EX_SUB_VIEW, ///< MVC sub view } VDEC_EX_View; typedef enum { E_HVD_SECURE_MODE_NONE = 0, /// None secure E_HVD_SECURE_MODE_TRUSTZONE /// Secure for TrustZone } HVD_SECURE_MODE; //----------------------------------------------------------------------------- /// @brief \b Struct \b Name: HVD_EX_MemMap /// @brief \b Struct \b Description: Store the HVD driver config //----------------------------------------------------------------------------- typedef struct { MS_U32 u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. MS_U32 u32MIU2BaseAddr; //!< the physical memory start address of MIU 2 base address. 0: default value. MS_U32 u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM MS_U32 u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. MS_U32 u32FWBinarySize; //!< the FW code size MS_U32 u32VLCBinaryVAddr; ///< VLC table binary data buffer start address MS_U32 u32VLCBinaryAddr; ///< VLC table binary data buffer start address MS_U32 u32VLCBinarySize; ///