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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regAESDMA.h
//  Description: AESDMA Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _RSA_REG_MCU_H_
#define _RSA_REG_MCU_H_


//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream


//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//--------------------------------------------------------------------------------------------------
//  Compliation Option
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------
#define REG_RSACTRL_BASE            (0xA1200 * 2)

#define RSA_E_BASE_ADDR             (0x00)
#define RSA_N_BASE_ADDR             (0x40)
#define RSA_A_BASE_ADDR             (0x80)
#define RSA_Z_BASE_ADDR             (0xC0)  /// 256-64

#define RSA_MAX_SECURE_RANGE_SIZE   (0x6)

typedef struct _REG32
{
    volatile MS_U32                u32Reg;
} REG32;

typedef struct _REG_SecureRange
{
	REG32 Rsa_Sec_Range_Start;
	REG32 Rsa_Sec_Range_End;

}REG_SecureRange;


typedef struct _REG_RSACtrl
{
    REG32               Rsa_Ind32_Start;                        //(REG_X32_RSA_BASE + 4 * 0)
        #define RSA_EXP_START                       0x00000001  ///exp_start
        #define RSA_INDIRECT_START                  0x00000002  /// ram start
        #define RSA_IND32_CTRL_DIRECTION_WRITE      0x00000004  /// ram_wdata
        #define RSA_INT_CLR                         0x00000008  /// int_clr
        #define RSA_BLOCK_RSA_KEY                   0x00000010  /// block_rsa_key
        #define RSA_ROOTKEY_SEL_PUB_NO              0x00000020  /// if public key, 0: select 1st key; 1 select 2nd key
        #define RSA_ROOTKEY_SEL_TYPE                0x00000040  /// 1: OTP RSA key is public; 0: OTP RSA is private
        //#define RSA_ROOTKEY_SEL_MASK                0x00000060 /// rootkey_sel:2
    REG32               Rsa_Dummy;
    REG32               Rsa_Ctrl;                               //(REG_X32_RSA_BASE + 4 * 2)
        #define RSA_CTRL_RSA_RST                    0x00000001  //RSA_SW_RESET_t sw_reset:1;
        #define RSA_CTRL_SEL_HW_KEY                 0x00000002  //RSA_HW_KEY_t hw_key:1;
        #define RSA_CTRL_SEL_PUBLIC_KEY             0x00000004  //RSA_PUB_KEY_t pub_key:1;
        #define RSA_CTRL_NMI                        0x00000010  ///nmi:1;
        #define RSA_CTRL_NLEN_ADJ                   0x00000020  ///nlen_adj:1
        #define RSA_CTRL_SRAM_EN                    0x00000080  ///sram_en:1
        #define RSA_CTRL_KEY_LENGTH_MASK            0x00003F00  ///nlen:6
        #define RSA_RAM_DIR                         0x00020000  ///RAM_DIR_t
        #define RSA_IND32_CTRL_ADDR_AUTO_INC        0x00040000
        #define RSA_IND32_CTRL_ACCESS_AUTO_START    0x00080000
        #define RSA_RAM_MSB_FIRST                   0x00100000
    REG32               Rsa_Ind32_Addr;                         //(REG_X32_RSA_BASE + 4 * 3)  REG_RSA_RAM_ADDR, REG_RSA_STATUS
        #define RSA_STATUS_RSA_BUSY                 0x01000000
        #define RSA_STATUS_MASK                     0x01000000
    REG32               Rsa_Ind32_Data;                         //(REG_X32_RSA_BASE + 4 * 4)          REG_RSA_RAM_DATA

	REG_SecureRange Rsa_Sec_Range[RSA_MAX_SECURE_RANGE_SIZE];
   	    #define REG_RSA_SEC_RANGE_MASK              0xFFFF0000
        #define REG_RSA_SEC_RANGE_SHIFT              16

    REG32               Rsa_CA_Spare_Oneway0;                   //(REG_X32_RSA_BASE + 4 * 11)
    REG32               Rsa_CA_Spare_Oneway1;                   //(REG_X32_RSA_BASE + 4 * 12)
    REG32               Rsa_Miu_Address_Mask;                   //(REG_X32_RSA_BASE + 4 * 13)
    REG32               Rsa_Xiu_Id;                             //(REG_X32_RSA_BASE + 4 * 14)
    REG32               Rsa_Release_Access;                     //(REG_X32_RSA_BASE + 4 * 15)
    REG32               Rsa_Hwkey_Switch;                       //(REG_X32_RSA_BASE + 4 * 16)
        #define RSA_READ_HWKEY_SWITCH               0x00000001
        #define RSA_HWKEY_SWITCH                    0x00000100

}REG_RSACtrl;


#endif // #ifndef _RSA_REG_MCU_H_