//<MStar Software>
//******************************************************************************
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//<MStar Software>
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////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: mmfilein.h
//  Description: Multimedia File In (MMFILEIN) Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _MMFILEIN_REG_H_
#define _MMFILEIN_REG_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------
#define MMFI_ENGINE_NUM                     (1)

#define MMFI_PIDFLT0_NUM                    (4)
#define MMFI_PIDFLT1_NUM                    (0)

#define MMFI_PIDFLT_NUM_ALL                 (MMFI_PIDFLT0_NUM+MMFI_PIDFLT1_NUM)

#define MMFI_PID_NULL                       0x1FFF

//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

#define REG_CTRL_BASE_MMFI0             (0x27E00UL)                            // 0xBF800000+(13F00/2)*4
#define REG_CTRL_BASE_MMFI1             (0x27F00UL)                            // 0xBF800000+(13F80/2)*4

typedef struct _REG32_MM
{
    volatile MS_U16                L;
    volatile MS_U16                empty_L;
    volatile MS_U16                H;
    volatile MS_U16                empty_H;
} REG32_MM;


typedef struct _REG16_MM
{
    volatile MS_U16                data;
    volatile MS_U16                _resv;
} REG16_MM;

typedef struct _REG_Ctrl_MMFI
{
    //----------------------------------------------
    // 0xBF802A00 MIPS direct access
    //----------------------------------------------
                                                                              // Index(word)  CPU(byte)     MIPS(0x13F00/2+index)*4
    REG32_MM                               PidFlt[4];                         // 0xbf827E00   0x00
    #define MMFI_PIDFLT_PID_MASK                    0x00001FFF
    #define MMFI_PIDFLT_EN_MASK                     0x0007E000
    #define MMFI_PIDFLT_AFIFOB_EN                   0x00002000
    #define MMFI_PIDFLT_AFIFO_EN                    0x00004000
    #define MMFI_PIDFLT_VFIFO_EN                    0x00008000
    #define MMFI_PIDFLT_V3DFIFO_EN                  0x00010000
    #define MMFI_PIDFLT_AFIFOC_EN                   0x00020000
    #define MMFI_PIDFLT_AFIFOD_EN                   0x00040000

    REG32_MM                               FileIn_RAddr;                       // 0xbf803820  0x08         //byte address
    REG32_MM                               FileIn_RNum;                        // 0xbf803828  0x0a

    REG16_MM                               FileIn_Ctrl;                        // 0xbf803830   0x0c
    #define MMFI_FILEIN_CTRL_START                  0x0001
    #define MMFI_FILEIN_CTRL_MOBF_EN                0x0002
    #define MMFI_FILEIN_CTRL_ABORT                  0x0010
    #define MMFI_FILEIN_CTRL_MASK                   0x0013
    #define MMFI_FILEIN_TIMER_MASK                  0xFF00
    #define MMFI_FILEIN_TIMER_SHIFT                 8

    REG16_MM                               CmdQSts;                            // 0xbf803834   0x0d
    #define MMFI_CMDQ_SIZE                          8
    #define MMFI_CMDQSTS_WRCNT_MASK                 0x001F
    #define MMFI_CMDQSTS_FIFO_FULL                  0x0040
    #define MMFI_CMDQSTS_FIFO_EMPTY                 0x0080
    #define MMFI_CMDQSTS_FIFO_WRLEVEL_MASK          0x0300
    #define MMFI_CMDQSTS_FIFO_WRLEVEL_SHIFT         8

    REG32_MM                               Cfg;                                // 0xbf803838   0x0e
    #define MMFI_CFG_LPCR2_LD                       0x00000001
    #define MMFI_CFG_LPCR2_WLD                      0x00000002
    #define MMFI_CFG_TEI_SKIP                       0x00000004
    #define MMFI_CFG_CLR_PIDFLT_BYTE_CNT            0x00000008
    #define MMFI_CFG_APID_BYPASS                    0x00000010
    #define MMFI_CFG_APIDB_BYPASS                   0x00000020
    #define MMFI_CFG_VPID_BYPASS                    0x00000040
    #define MMFI_CFG_VPID3D_BYPASS                  0x00000080
    #define MMFI_CFG_AUD_ERR_EN                     0x00000100
    #define MMFI_CFG_AUDB_ERR_EN                    0x00000200
    #define MMFI_CFG_VD_ERR_EN                      0x00000400
    #define MMFI_CFG_V3D_ERR_EN                     0x00000800
    #define MMFI_CFG_APES_ERR_RM_EN                 0x00001000
    #define MMFI_CFG_APESB_ERR_RM_EN                0x00002000
    #define MMFI_CFG_VPES_ERR_RM_EN                 0x00004000
    #define MMFI_CFG_VPES3D_ERR_RM_EN               0x00008000
    #define MMFI_CFG_CLR_PKT_CNT                    0x00010000
    #define MMFI_CFG_DIS_MIU_RQ                     0x00020000
    #define MMFI_CFG_RADDR_READ                     0x00040000
    #define MMFI_CFG_BYTETIMER_EN                   0x00080000
    #define MMFI_CFG_PLY_FILE_INV_EN                0x00100000
    #define MMFI_CFG_DUP_PKT_SKIP                   0x00200000
    #define MMFI_CFG_ALT_TS_SIZE                    0x00400000
    #define MMFI_CFG_2MI_RPRIORITY                  0x00800000
    #define MMFI_CFG_PS_AUD_EN                      0x01000000
    #define MMFI_CFG_PS_AUDB_EN                     0x02000000
    #define MMFI_CFG_PS_VD_EN                       0x04000000
    #define MMFI_CFG_PS_V3D_EN                      0x08000000
    #define MMFI_CFG_MEM_TS_ORDER                   0x10000000
    #define MMFI_CFG_MEM_TS_DATA_ENDIAN             0x20000000
    #define MMFI_CFG_PKT192_EN                      0x40000000
    #define MMFI_CFG_PKT192_BLK_DISABLE             0x80000000
    #define MMFI_CFG_FILEIN_MODE_MASK               (MMFI_CFG_APID_BYPASS|MMFI_CFG_APIDB_BYPASS|MMFI_CFG_VPID_BYPASS|MMFI_CFG_VPID3D_BYPASS|MMFI_CFG_PS_AUD_EN|MMFI_CFG_PS_AUDB_EN|MMFI_CFG_PS_VD_EN|MMFI_CFG_PS_V3D_EN)

    REG32_MM                               TsHeader;                            // 0xbf803840  0x10
    #define MMFI_HD_CCNT_MASK                       0x0000000F
    #define MMFI_HD_AF_MASK                         0x00000030
    #define MMFI_HD_AF_SHIFT                        4
    #define MMFI_HD_SCRAMBLE_MASK                   0x000000C0
    #define MMFI_HD_SCRAMBLE_SHIFT                  6
    #define MMFI_HD_PID                             0x001FFF00
    #define MMFI_HD_PID_SHIFT                       8
    #define MMFI_HD_TS_PRIORITY_MASK                0x00200000
    #define MMFI_HD_TS_PRIORITY_SHIFT               21
    #define MMFI_HD_PAYLOAD_START_FLG_MASK          0x00400000
    #define MMFI_HD_PAYLOAD_START_FLG_SHIFT         22
    #define MMFI_HD_ERR_FLG_MASK                    0x00800000
    #define MMFI_HD_ERR_FLG_SHIFT                   23

    REG16_MM                               APid_Status;                         // 0xbf803848   0x12
    #define MMFI_APID_MATCHED_MASK                  0x00001FFF
    #define MMFI_APID_CHANGE                        0x00002000
	REG16_MM                               APidB_Status;                        // 0xbf803848   0x13
    #define MMFI_APIDB_MATCHED_MASK                 0x00001FFF
    #define MMFI_APIDB_CHANGE                       0x00002000
    REG16_MM                               VPID_Status;                         // 0xbf803850   0x14
    #define MMFI_VPID_MATCHED_MASK                  0x00001FFF
    #define MMFI_VPID_CHANGE                        0x00002000
    REG16_MM                               VPID3D_Status;                       // 0xbf803854   0x15
    #define MMFI_VPID3D_MATCHED_MASK                0x00001FFF
    #define MMFI_VPID3D_CHANGE                      0x00002000

    REG32_MM                               LPcr2_Buf;                           // 0xbf803858   0x16
    REG32_MM                               TimeStamp_FIn;                       // 0xbf803860   0x18

    REG16_MM                               SWRst;                              // 0xbf803868   0x1a
    #define MMFI_SWRST_MASK                         0x07FF
    #define MMFI_SW_RSTZ_MMFILEIN_DISABLE           0x0001                  // low active
    #define MMFI_RST_WB_DMA0                        0x0002
    #define MMFI_RST_CMDQ0                          0x0004
    #define MMFI_RST_TSIF0                          0x0008
    #define MMFI_RST_WB0                            0x0010
    #define MMFI_RST_WB_DMA1                        0x0020
    #define MMFI_RST_CMDQ1                          0x0040
    #define MMFI_RST_TSIF1                          0x0080
    #define MMFI_RST_WB1                            0x0100
    #define MMFI_RST_PATH0                          0x0200
    #define MMFI_RST_PATH1                          0x0400
    #define MMFI_RST_ALL                            0x07FE
    #define MMFI_RST_LPCR_27M_EN_MMFI0              0x4000
    #define MMFI_RST_LPCR_27M_EN_MMFI1              0x8000

    REG16_MM                               HWInt;                             // 0xbf80386c   0x1b
    #define MMFI_HWINT_SRC_MASK                     0x00FF
    #define MMFI_HWINT_SRC_FILEIN_DONE1             0x0004
    #define MMFI_HWINT_SRC_FILEIN_DONE0             0x0008
    #define MMFI_HWINT_SRC_VD3D_ERR1                0x0010
    #define MMFI_HWINT_SRC_AUAUB_ERR1               0x0020
    #define MMFI_HWINT_SRC_VD3D_ERR0                0x0040
    #define MMFI_HWINT_SRC_AUAUB_ERR0               0x0080
    #define MMFI_HWINT_STS_MASK                     0xFF00
    #define MMFI_HWINT_STS_SHIFT                    8
    #define MMFI_HWINT_STS_FILEIN_DONE1             0x0400
    #define MMFI_HWINT_STS_FILEIN_DONE0             0x0800
    #define MMFI_HWINT_STS_VD3D_ERR1                0x1000
    #define MMFI_HWINT_STS_AUAUB_ERR1               0x2000
    #define MMFI_HWINT_STS_VD3D_ERR0                0x4000
    #define MMFI_HWINT_STS_AUAUB_ERR0               0x8000

    REG16_MM                               PktChkSize;                         // 0xbf803870   0x1c
    #define MMFI_PKTCHK_SIZE_MASK                   0x00FF
    #define MMFI_SYNC_BYTE_MASK                     0xFF00
    #define MMFI_SYNC_BYTE_SHIFT                    8

    REG16_MM                               MOBFKey;                            // 0xbf803874   0x1d
    #define MMFI_MOBFKEY_MASK                       0x001F

    REG32_MM                               RAddr;                              // 0xbf803878   0x1e
    #define MMFI_TSP2MI_RADDR_MASK                  0x0FFFFFFF
} REG_Ctrl_MMFI;

typedef struct _REG_Ctrl_MMFI1
{
    //----------------------------------------------
    // 0xBF827F00 MIPS direct access
    //----------------------------------------------
                                                                               // Index(word)  CPU(byte)     MIPS(0x13F80/2+index)*4
    REG16_MM                               CFG2[2];                            // 0xbf827F00   0x40~0x41
    #define MMFI_CFG2_MMFI_APIDC_BYPASS             0x00000001
    #define MMFI_CFG2_APESC_ERR_RM_EN               0x00000002
    #define MMFI_CFG2_MMFI_PS_AUDC_EN               0x00000004
    #define MMFI_CFG2_FILEIN_PAUSE                  0x00000008
    #define MMFI_CFG2_MMFI_APIDD_BYPASS             0x00000010
    #define MMFI_CFG2_APESD_ERR_RM_EN               0x00000020
    #define MMFI_CFG2_MMFI_PS_AUDD_EN               0x00000040
    #define MMFI_CFG2_MMFI_WB_FSM_RESET             0x00000080
    #define MMFI_CFG2_INIT_TIMESTAMP_TSIF           0x00000100
    #define MMFI_CFG2_FILEIN_MODE_MASK              (MMFI_CFG2_MMFI_APIDC_BYPASS | MMFI_CFG2_MMFI_APIDD_BYPASS | MMFI_CFG2_MMFI_PS_AUDC_EN | MMFI_CFG2_MMFI_PS_AUDD_EN)

    REG16_MM                               CFG3[2];                            // 0xbf827F08   0x42~0x43
    #define MMFI_CFG3_RVU_PSI_EN                    0x00000001
    #define MMFI_CFG3_RVU_TEI_EN                    0x00000002
    #define MMFI_CFG3_RVU_ERR_CLR                   0x00000004
    #define MMFI_CFG3_RVU_EN                        0x00000008
    #define MMFI_CFG3_RVU_TIMESTAMP_EN              0x00000010

} REG_Ctrl_MMFI1;


#endif // _MMFILEIN_REG_H_