/* * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __DRM_ANALOGIX_DP_H__ #define __DRM_ANALOGIX_DP_H__ #include /* * Unless otherwise noted, all values are from the DP 1.1a spec. Note that * DP and DPCD versions are independent. Differences from 1.0 are not noted, * 1.0 devices basically don't exist in the wild. * * Abbreviations, in chronological order: * * eDP: Embedded DisplayPort version 1 * DPI: DisplayPort Interoperability Guideline v1.1a * 1.2: DisplayPort 1.2 * MST: Multistream Transport - part of DP 1.2a * * 1.2 formally includes both eDP and DPI definitions. */ #define DP_AUX_MAX_PAYLOAD_BYTES 16 #define DP_AUX_I2C_WRITE 0x0 #define DP_AUX_I2C_READ 0x1 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 #define DP_AUX_I2C_MOT 0x4 #define DP_AUX_NATIVE_WRITE 0x8 #define DP_AUX_NATIVE_READ 0x9 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) /* AUX CH addresses */ /* DPCD */ #define DP_DPCD_REV 0x000 #define DP_MAX_LINK_RATE 0x001 #define DP_MAX_LANE_COUNT 0x002 # define DP_MAX_LANE_COUNT_MASK 0x1f # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ # define DP_ENHANCED_FRAME_CAP (1 << 7) #define DP_MAX_DOWNSPREAD 0x003 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) #define DP_NORP 0x004 #define DP_DOWNSTREAMPORT_PRESENT 0x005 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) # define DP_FORMAT_CONVERSION (1 << 3) # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ #define DP_MAIN_LINK_CHANNEL_CODING 0x006 #define DP_DOWN_STREAM_PORT_COUNT 0x007 # define DP_PORT_COUNT_MASK 0x0f # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ # define DP_OUI_SUPPORT (1 << 7) #define DP_RECEIVE_PORT_0_CAP_0 0x008 # define DP_LOCAL_EDID_PRESENT (1 << 1) # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 #define DP_RECEIVE_PORT_1_CAP_0 0x00a #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b #define DP_I2C_SPEED_CAP 0x00c /* DPI */ # define DP_I2C_SPEED_1K 0x01 # define DP_I2C_SPEED_5K 0x02 # define DP_I2C_SPEED_10K 0x04 # define DP_I2C_SPEED_100K 0x08 # define DP_I2C_SPEED_400K 0x10 # define DP_I2C_SPEED_1M 0x20 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) # define DP_FRAMING_CHANGE_CAP (1 << 1) # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ #define DP_ADAPTER_CAP 0x00f /* 1.2 */ # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0) #define DP_MSTM_CAP 0x021 /* 1.2 */ # define DP_MST_CAP (1 << 0) #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ /* AV_SYNC_DATA_BLOCK 1.2 */ #define DP_AV_GRANULARITY 0x023 # define DP_AG_FACTOR_MASK (0xf << 0) # define DP_AG_FACTOR_3MS (0 << 0) # define DP_AG_FACTOR_2MS (1 << 0) # define DP_AG_FACTOR_1MS (2 << 0) # define DP_AG_FACTOR_500US (3 << 0) # define DP_AG_FACTOR_200US (4 << 0) # define DP_AG_FACTOR_100US (5 << 0) # define DP_AG_FACTOR_10US (6 << 0) # define DP_AG_FACTOR_1US (7 << 0) # define DP_VG_FACTOR_MASK (0xf << 4) # define DP_VG_FACTOR_3MS (0 << 4) # define DP_VG_FACTOR_2MS (1 << 4) # define DP_VG_FACTOR_1MS (2 << 4) # define DP_VG_FACTOR_500US (3 << 4) # define DP_VG_FACTOR_200US (4 << 4) # define DP_VG_FACTOR_100US (5 << 4) #define DP_AUD_DEC_LAT0 0x024 #define DP_AUD_DEC_LAT1 0x025 #define DP_AUD_PP_LAT0 0x026 #define DP_AUD_PP_LAT1 0x027 #define DP_VID_INTER_LAT 0x028 #define DP_VID_PROG_LAT 0x029 #define DP_REP_LAT 0x02a #define DP_AUD_DEL_INS0 0x02b #define DP_AUD_DEL_INS1 0x02c #define DP_AUD_DEL_INS2 0x02d /* End of AV_SYNC_DATA_BLOCK */ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) #define DP_GUID 0x030 /* 1.2 */ #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ # define DP_PSR_NO_TRAIN_ON_EXIT 1 # define DP_PSR_SETUP_TIME_330 (0 << 1) # define DP_PSR_SETUP_TIME_275 (1 << 1) # define DP_PSR_SETUP_TIME_220 (2 << 1) # define DP_PSR_SETUP_TIME_165 (3 << 1) # define DP_PSR_SETUP_TIME_110 (4 << 1) # define DP_PSR_SETUP_TIME_55 (5 << 1) # define DP_PSR_SETUP_TIME_0 (6 << 1) # define DP_PSR_SETUP_TIME_MASK (7 << 1) # define DP_PSR_SETUP_TIME_SHIFT 1 /* * 0x80-0x8f describe downstream port capabilities, but there are two layouts * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, * each port's descriptor is one byte wide. If it was set, each port's is * four bytes wide, starting with the one byte from the base info. As of * DP interop v1.1a only VGA defines additional detail. */ /* offset 0 */ #define DP_DOWNSTREAM_PORT_0 0x80 # define DP_DS_PORT_TYPE_MASK (7 << 0) # define DP_DS_PORT_TYPE_DP 0 # define DP_DS_PORT_TYPE_VGA 1 # define DP_DS_PORT_TYPE_DVI 2 # define DP_DS_PORT_TYPE_HDMI 3 # define DP_DS_PORT_TYPE_NON_EDID 4 # define DP_DS_PORT_HPD (1 << 3) /* offset 1 for VGA is maximum megapixels per second / 8 */ /* offset 2 */ # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) # define DP_DS_VGA_8BPC 0 # define DP_DS_VGA_10BPC 1 # define DP_DS_VGA_12BPC 2 # define DP_DS_VGA_16BPC 3 /* link configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14 /* 1.2 */ #define DP_LANE_COUNT_SET 0x101 # define DP_LANE_COUNT_MASK 0x0f # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) #define DP_TRAINING_PATTERN_SET 0x102 # define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_2 2 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ # define DP_TRAINING_PATTERN_MASK 0x3 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) #define DP_TRAINING_LANE0_SET 0x103 #define DP_TRAINING_LANE1_SET 0x104 #define DP_TRAINING_LANE2_SET 0x105 #define DP_TRAINING_LANE3_SET 0x106 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) #define DP_DOWNSPREAD_CTRL 0x107 # define DP_SPREAD_AMP_0_5 (1 << 4) # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 # define DP_SET_ANSI_8B10B (1 << 0) #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ /* bitmask as for DP_I2C_SPEED_CAP */ #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) # define DP_FRAMING_CHANGE_ENABLE (1 << 1) # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ #define DP_LINK_QUAL_LANE1_SET 0x10c #define DP_LINK_QUAL_LANE2_SET 0x10d #define DP_LINK_QUAL_LANE3_SET 0x10e # define DP_LINK_QUAL_PATTERN_DISABLE 0 # define DP_LINK_QUAL_PATTERN_D10_2 1 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 # define DP_LINK_QUAL_PATTERN_PRBS7 3 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 # define DP_LINK_QUAL_PATTERN_MASK 7 #define DP_TRAINING_LANE0_1_SET2 0x10f #define DP_TRAINING_LANE2_3_SET2 0x110 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) #define DP_MSTM_CTRL 0x111 /* 1.2 */ # define DP_MST_EN (1 << 0) # define DP_UP_REQ_EN (1 << 1) # define DP_UPSTREAM_IS_SRC (1 << 2) #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ #define DP_AUDIO_DELAY1 0x113 #define DP_AUDIO_DELAY2 0x114 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ # define DP_LINK_RATE_SET_SHIFT 0 # define DP_LINK_RATE_SET_MASK (7 << 0) #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE (1 << 0) # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) # define DP_IRQ_HPD_ENABLE (1 << 1) #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ # define DP_PWR_NOT_NEEDED (1 << 0) #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) # define DP_PSR_CRC_VERIFICATION (1 << 2) # define DP_PSR_FRAME_CAPTURE (1 << 3) # define DP_PSR_SELECTIVE_UPDATE (1 << 4) # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) #define DP_ADAPTER_CTRL 0x1a0 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 #define DP_SINK_COUNT 0x200 /* prior to 1.2 bit 7 was reserved mbz */ # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) # define DP_SINK_CP_READY (1 << 6) #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) # define DP_AUTOMATED_TEST_REQUEST (1 << 1) # define DP_CP_IRQ (1 << 2) # define DP_MCCS_IRQ (1 << 3) # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ # define DP_SINK_SPECIFIC_IRQ (1 << 6) #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 # define DP_LANE_CR_DONE (1 << 0) # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) # define DP_LANE_SYMBOL_LOCKED (1 << 2) #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ DP_LANE_CHANNEL_EQ_DONE | \ DP_LANE_SYMBOL_LOCKED) #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 #define DP_INTERLANE_ALIGN_DONE (1 << 0) #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) #define DP_LINK_STATUS_UPDATED (1 << 7) #define DP_SINK_STATUS 0x205 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) #define DP_RECEIVE_PORT_1_STATUS (1 << 1) #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 #define DP_TEST_REQUEST 0x218 # define DP_TEST_LINK_TRAINING (1 << 0) # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) # define DP_TEST_LINK_EDID_READ (1 << 2) # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ #define DP_TEST_LINK_RATE 0x219 # define DP_LINK_RATE_162 (0x6) # define DP_LINK_RATE_27 (0xa) #define DP_TEST_LANE_COUNT 0x220 #define DP_TEST_PATTERN 0x221 #define DP_TEST_CRC_R_CR 0x240 #define DP_TEST_CRC_G_Y 0x242 #define DP_TEST_CRC_B_CB 0x244 #define DP_TEST_SINK_MISC 0x246 # define DP_TEST_CRC_SUPPORTED (1 << 5) # define DP_TEST_COUNT_MASK 0xf #define DP_TEST_RESPONSE 0x260 # define DP_TEST_ACK (1 << 0) # define DP_TEST_NAK (1 << 1) # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) #define DP_TEST_EDID_CHECKSUM 0x261 #define DP_TEST_SINK 0x270 # define DP_TEST_SINK_START (1 << 0) #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) # define DP_PAYLOAD_ACT_HANDLED (1 << 1) #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ /* up to ID_SLOT_63 at 0x2ff */ #define DP_SOURCE_OUI 0x300 #define DP_SINK_OUI 0x400 #define DP_BRANCH_OUI 0x500 #define DP_SET_POWER 0x600 # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 # define DP_SET_POWER_MASK 0x3 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ # define DP_EDP_11 0x00 # define DP_EDP_12 0x01 # define DP_EDP_13 0x02 # define DP_EDP_14 0x03 #define DP_EDP_GENERAL_CAP_1 0x701 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 #define DP_EDP_GENERAL_CAP_2 0x703 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ /* 0-5 sink count */ # define DP_SINK_COUNT_CP_READY (1 << 6) #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ # define DP_PSR_LINK_CRC_ERROR (1 << 0) # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ # define DP_PSR_CAPS_CHANGE (1 << 0) #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ # define DP_PSR_SINK_INACTIVE 0 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 # define DP_PSR_SINK_ACTIVE_RFB 2 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 # define DP_PSR_SINK_ACTIVE_RESYNC 4 # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE 0x0 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 #define DP_PEER_DEVICE_SST_SINK 0x3 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ #define DP_LINK_ADDRESS 0x01 #define DP_CONNECTION_STATUS_NOTIFY 0x02 #define DP_ENUM_PATH_RESOURCES 0x10 #define DP_ALLOCATE_PAYLOAD 0x11 #define DP_QUERY_PAYLOAD 0x12 #define DP_RESOURCE_STATUS_NOTIFY 0x13 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 #define DP_REMOTE_DPCD_READ 0x20 #define DP_REMOTE_DPCD_WRITE 0x21 #define DP_REMOTE_I2C_READ 0x22 #define DP_REMOTE_I2C_WRITE 0x23 #define DP_POWER_UP_PHY 0x24 #define DP_POWER_DOWN_PHY 0x25 #define DP_SINK_EVENT_NOTIFY 0x30 #define DP_QUERY_STREAM_ENC_STATUS 0x38 /* DP 1.2 MST sideband nak reasons - table 2.84 */ #define DP_NAK_WRITE_FAILURE 0x01 #define DP_NAK_INVALID_READ 0x02 #define DP_NAK_CRC_FAILURE 0x03 #define DP_NAK_BAD_PARAM 0x04 #define DP_NAK_DEFER 0x05 #define DP_NAK_LINK_FAILURE 0x06 #define DP_NAK_NO_RESOURCES 0x07 #define DP_NAK_DPCD_FAIL 0x08 #define DP_NAK_I2C_NAK 0x09 #define DP_NAK_ALLOCATE_FAIL 0x0a #define ANALOGIX_DP_TX_SW_RESET 0x14 #define ANALOGIX_DP_FUNC_EN_1 0x18 #define ANALOGIX_DP_FUNC_EN_2 0x1C #define ANALOGIX_DP_VIDEO_CTL_1 0x20 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C #define ANALOGIX_DP_VIDEO_CTL_10 0x44 #define ANALOGIX_DP_PLL_REG_1 0xfc #define ANALOGIX_DP_PLL_REG_2 0x9e4 #define ANALOGIX_DP_PLL_REG_3 0x9e8 #define ANALOGIX_DP_PLL_REG_4 0x9ec #define ANALOGIX_DP_PLL_REG_5 0xa00 #define ANALOGIX_DP_PD 0x12c #define ANALOGIX_DP_LANE_MAP 0x35C #define ANALOGIX_DP_ANALOG_CTL_1 0x370 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 #define ANALOGIX_DP_INT_STA 0x3DC #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC #define ANALOGIX_DP_INT_STA_MASK 0x3F8 #define ANALOGIX_DP_INT_CTL 0x3FC #define ANALOGIX_DP_SYS_CTL_1 0x600 #define ANALOGIX_DP_SYS_CTL_2 0x604 #define ANALOGIX_DP_SYS_CTL_3 0x608 #define ANALOGIX_DP_SYS_CTL_4 0x60C #define ANALOGIX_DP_PKT_SEND_CTL 0x640 #define ANALOGIX_DP_HDCP_CTL 0x648 #define ANALOGIX_DP_LINK_BW_SET 0x680 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 #define ANALOGIX_DP_M_VID_0 0x700 #define ANALOGIX_DP_M_VID_1 0x704 #define ANALOGIX_DP_M_VID_2 0x708 #define ANALOGIX_DP_N_VID_0 0x70C #define ANALOGIX_DP_N_VID_1 0x710 #define ANALOGIX_DP_N_VID_2 0x714 #define ANALOGIX_DP_PLL_CTL 0x71C #define ANALOGIX_DP_PHY_PD 0x720 #define ANALOGIX_DP_PHY_TEST 0x724 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 #define ANALOGIX_DP_AUX_CH_STA 0x780 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 #define ANALOGIX_DP_AUX_RX_COMM 0x78C #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 /* ANALOGIX_DP_TX_SW_RESET */ #define RESET_DP_TX (0x1 << 0) /* ANALOGIX_DP_FUNC_EN_1 */ #define MASTER_VID_FUNC_EN_N (0x1 << 7) #define SLAVE_VID_FUNC_EN_N (0x1 << 5) #define AUD_FIFO_FUNC_EN_N (0x1 << 4) #define AUD_FUNC_EN_N (0x1 << 3) #define HDCP_FUNC_EN_N (0x1 << 2) #define CRC_FUNC_EN_N (0x1 << 1) #define SW_FUNC_EN_N (0x1 << 0) /* ANALOGIX_DP_FUNC_EN_2 */ #define SSC_FUNC_EN_N (0x1 << 7) #define AUX_FUNC_EN_N (0x1 << 2) #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) /* ANALOGIX_DP_VIDEO_CTL_1 */ #define VIDEO_EN (0x1 << 7) #define HDCP_VIDEO_MUTE (0x1 << 6) /* ANALOGIX_DP_VIDEO_CTL_1 */ #define IN_D_RANGE_MASK (0x1 << 7) #define IN_D_RANGE_SHIFT (7) #define IN_D_RANGE_CEA (0x1 << 7) #define IN_D_RANGE_VESA (0x0 << 7) #define IN_BPC_MASK (0x7 << 4) #define IN_BPC_SHIFT (4) #define IN_BPC_12_BITS (0x3 << 4) #define IN_BPC_10_BITS (0x2 << 4) #define IN_BPC_8_BITS (0x1 << 4) #define IN_BPC_6_BITS (0x0 << 4) #define IN_COLOR_F_MASK (0x3 << 0) #define IN_COLOR_F_SHIFT (0) #define IN_COLOR_F_YCBCR444 (0x2 << 0) #define IN_COLOR_F_YCBCR422 (0x1 << 0) #define IN_COLOR_F_RGB (0x0 << 0) /* ANALOGIX_DP_VIDEO_CTL_3 */ #define IN_YC_COEFFI_MASK (0x1 << 7) #define IN_YC_COEFFI_SHIFT (7) #define IN_YC_COEFFI_ITU709 (0x1 << 7) #define IN_YC_COEFFI_ITU601 (0x0 << 7) #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) #define VID_CHK_UPDATE_TYPE_SHIFT (4) #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) /* ANALOGIX_DP_VIDEO_CTL_8 */ #define VID_HRES_TH(x) (((x) & 0xf) << 4) #define VID_VRES_TH(x) (((x) & 0xf) << 0) /* ANALOGIX_DP_VIDEO_CTL_10 */ #define FORMAT_SEL (0x1 << 4) #define INTERACE_SCAN_CFG (0x1 << 2) #define VSYNC_POLARITY_CFG (0x1 << 1) #define HSYNC_POLARITY_CFG (0x1 << 0) /* ANALOGIX_DP_PLL_REG_1 */ #define REF_CLK_24M (0x1 << 0) #define REF_CLK_27M (0x0 << 0) #define REF_CLK_MASK (0x1 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) /* ANALOGIX_DP_ANALOG_CTL_1 */ #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) /* ANALOGIX_DP_ANALOG_CTL_2 */ #define SEL_24M (0x1 << 3) #define TX_DVDD_BIT_1_0625V (0x4 << 0) /* ANALOGIX_DP_ANALOG_CTL_3 */ #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) #define VCO_BIT_600_MICRO (0x5 << 0) /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ #define PD_RING_OSC (0x1 << 6) #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) #define TX_CUR1_2X (0x1 << 2) #define TX_CUR_16_MA (0x3 << 0) /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ #define CH3_AMP_400_MV (0x0 << 24) #define CH2_AMP_400_MV (0x0 << 16) #define CH1_AMP_400_MV (0x0 << 8) #define CH0_AMP_400_MV (0x0 << 0) /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) /* ANALOGIX_DP_COMMON_INT_STA_1 */ #define VSYNC_DET (0x1 << 7) #define PLL_LOCK_CHG (0x1 << 6) #define SPDIF_ERR (0x1 << 5) #define SPDIF_UNSTBL (0x1 << 4) #define VID_FORMAT_CHG (0x1 << 3) #define AUD_CLK_CHG (0x1 << 2) #define VID_CLK_CHG (0x1 << 1) #define SW_INT (0x1 << 0) /* ANALOGIX_DP_COMMON_INT_STA_2 */ #define ENC_EN_CHG (0x1 << 6) #define HW_BKSV_RDY (0x1 << 3) #define HW_SHA_DONE (0x1 << 2) #define HW_AUTH_STATE_CHG (0x1 << 1) #define HW_AUTH_DONE (0x1 << 0) /* ANALOGIX_DP_COMMON_INT_STA_3 */ #define AFIFO_UNDER (0x1 << 7) #define AFIFO_OVER (0x1 << 6) #define R0_CHK_FLAG (0x1 << 5) /* ANALOGIX_DP_COMMON_INT_STA_4 */ #define PSR_ACTIVE (0x1 << 7) #define PSR_INACTIVE (0x1 << 6) #define SPDIF_BI_PHASE_ERR (0x1 << 5) #define HOTPLUG_CHG (0x1 << 2) #define HPD_LOST (0x1 << 1) #define PLUG (0x1 << 0) /* ANALOGIX_DP_INT_STA */ #define INT_HPD (0x1 << 6) #define HW_TRAINING_FINISH (0x1 << 5) #define RPLY_RECEIV (0x1 << 1) #define AUX_ERR (0x1 << 0) /* ANALOGIX_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) #define INT_POL1 (0x1 << 1) #define INT_POL0 (0x1 << 0) /* ANALOGIX_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2) #define FORCE_DET (0x1 << 1) #define DET_CTRL (0x1 << 0) /* ANALOGIX_DP_SYS_CTL_2 */ #define CHA_CRI(x) (((x) & 0xf) << 4) #define CHA_STA (0x1 << 2) #define FORCE_CHA (0x1 << 1) #define CHA_CTRL (0x1 << 0) /* ANALOGIX_DP_SYS_CTL_3 */ #define HPD_STATUS (0x1 << 6) #define F_HPD (0x1 << 5) #define HPD_CTRL (0x1 << 4) #define HDCP_RDY (0x1 << 3) #define STRM_VALID (0x1 << 2) #define F_VALID (0x1 << 1) #define VALID_CTRL (0x1 << 0) /* ANALOGIX_DP_SYS_CTL_4 */ #define FIX_M_AUD (0x1 << 4) #define ENHANCED (0x1 << 3) #define FIX_M_VID (0x1 << 2) #define M_VID_UPDATE_CTRL (0x3 << 0) /* ANALOGIX_DP_TRAINING_PTN_SET */ #define SCRAMBLER_TYPE (0x1 << 9) #define HW_LINK_TRAINING_PATTERN (0x1 << 8) #define SCRAMBLING_DISABLE (0x1 << 5) #define SCRAMBLING_ENABLE (0x0 << 5) #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ #define PRE_EMPHASIS_SET_MASK (0x3 << 3) #define PRE_EMPHASIS_SET_SHIFT (3) /* ANALOGIX_DP_DEBUG_CTL */ #define PLL_LOCK (0x1 << 4) #define F_PLL_LOCK (0x1 << 3) #define PLL_LOCK_CTRL (0x1 << 2) #define PN_INV (0x1 << 0) /* ANALOGIX_DP_PLL_CTL */ #define DP_PLL_PD (0x1 << 7) #define DP_PLL_RESET (0x1 << 6) #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) /* ANALOGIX_DP_PHY_PD */ #define DP_PHY_PD (0x1 << 5) #define AUX_PD (0x1 << 4) #define CH3_PD (0x1 << 3) #define CH2_PD (0x1 << 2) #define CH1_PD (0x1 << 1) #define CH0_PD (0x1 << 0) /* ANALOGIX_DP_PHY_TEST */ #define MACRO_RST (0x1 << 5) #define CH1_TEST (0x1 << 1) #define CH0_TEST (0x1 << 0) /* ANALOGIX_DP_AUX_CH_STA */ #define AUX_BUSY (0x1 << 4) #define AUX_STATUS_MASK (0xf << 0) /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ #define DEFER_CTRL_EN (0x1 << 7) #define DEFER_COUNT(x) (((x) & 0x7f) << 0) /* ANALOGIX_DP_AUX_RX_COMM */ #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) /* ANALOGIX_DP_BUFFER_DATA_CTL */ #define BUF_CLR (0x1 << 7) #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) /* ANALOGIX_DP_AUX_CH_CTL_1 */ #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) #define AUX_TX_COMM_MASK (0xf << 0) #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) #define AUX_TX_COMM_MOT (0x1 << 2) #define AUX_TX_COMM_WRITE (0x0 << 0) #define AUX_TX_COMM_READ (0x1 << 0) /* ANALOGIX_DP_AUX_ADDR_7_0 */ #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) /* ANALOGIX_DP_AUX_ADDR_15_8 */ #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) /* ANALOGIX_DP_AUX_ADDR_19_16 */ #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) /* ANALOGIX_DP_AUX_CH_CTL_2 */ #define ADDR_ONLY (0x1 << 1) #define AUX_EN (0x1 << 0) /* ANALOGIX_DP_SOC_GENERAL_CTL */ #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) #define AUDIO_MODE_MASTER_MODE (0x0 << 8) #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) #define VIDEO_MASTER_CLK_SEL (0x1 << 2) #define VIDEO_MASTER_MODE_EN (0x1 << 1) #define VIDEO_MODE_MASK (0x1 << 0) #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) #define VIDEO_MODE_MASTER_MODE (0x0 << 0) #define DP_TIMEOUT_LOOP_COUNT 100 #define MAX_CR_LOOP 5 #define MAX_EQ_LOOP 5 /* I2C EDID Chip ID, Slave Address */ #define I2C_EDID_DEVICE_ADDR 0x50 #define I2C_E_EDID_DEVICE_ADDR 0x30 #define EDID_BLOCK_LENGTH 0x80 #define EDID_HEADER_PATTERN 0x00 #define EDID_EXTENSION_FLAG 0x7e #define EDID_CHECKSUM 0x7f /* DP_MAX_LANE_COUNT */ #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) /* DP_LANE_COUNT_SET */ #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) /* DP_TRAINING_LANE0_SET */ #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) enum link_lane_count_type { LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4 }; enum link_training_state { START, CLOCK_RECOVERY, EQUALIZER_TRAINING, FINISHED, FAILED }; enum voltage_swing_level { VOLTAGE_LEVEL_0, VOLTAGE_LEVEL_1, VOLTAGE_LEVEL_2, VOLTAGE_LEVEL_3, }; enum pre_emphasis_level { PRE_EMPHASIS_LEVEL_0, PRE_EMPHASIS_LEVEL_1, PRE_EMPHASIS_LEVEL_2, PRE_EMPHASIS_LEVEL_3, }; enum pattern_set { PRBS7, D10_2, TRAINING_PTN1, TRAINING_PTN2, DP_NONE }; enum color_space { COLOR_RGB, COLOR_YCBCR422, COLOR_YCBCR444 }; enum color_depth { COLOR_6, COLOR_8, COLOR_10, COLOR_12 }; enum color_coefficient { COLOR_YCBCR601, COLOR_YCBCR709 }; enum dynamic_range { VESA, CEA }; enum pll_status { PLL_UNLOCKED, PLL_LOCKED }; enum clock_recovery_m_value_type { CALCULATED_M, REGISTER_M }; enum video_timing_recognition_type { VIDEO_TIMING_FROM_CAPTURE, VIDEO_TIMING_FROM_REGISTER }; enum analog_power_block { AUX_BLOCK, CH0_BLOCK, CH1_BLOCK, CH2_BLOCK, CH3_BLOCK, ANALOG_TOTAL, POWER_ALL }; enum dp_irq_type { DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), DP_IRQ_TYPE_HP_CHANGE = BIT(2), DP_IRQ_TYPE_UNKNOWN = BIT(3), }; struct video_info { char *name; bool h_sync_polarity; bool v_sync_polarity; bool interlaced; enum color_space color_space; enum dynamic_range dynamic_range; enum color_coefficient ycbcr_coeff; enum color_depth color_depth; int max_link_rate; enum link_lane_count_type max_lane_count; }; struct link_train { int eq_loop; int cr_loop[4]; u8 link_rate; u8 lane_count; u8 training_lane[4]; enum link_training_state lt_state; }; enum analogix_dp_devtype { EXYNOS_DP, ROCKCHIP_DP, }; enum analogix_dp_sub_devtype { RK3288_DP, RK3368_EDP, RK3399_EDP, }; struct analogix_dp_plat_data { enum analogix_dp_devtype dev_type; enum analogix_dp_sub_devtype subdev_type; }; struct analogix_dp_device { struct udevice *dev; void *reg_base; void *grf; struct reset_ctl reset; struct gpio_desc hpd_gpio; struct video_info video_info; struct link_train link_train; struct drm_display_mode *mode; struct analogix_dp_plat_data plat_data; unsigned char edid[EDID_BLOCK_LENGTH * 2]; }; /* analogix_dp_reg.c */ void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); void analogix_dp_stop_video(struct analogix_dp_device *dp); void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); void analogix_dp_init_analog_param(struct analogix_dp_device *dp); void analogix_dp_init_interrupt(struct analogix_dp_device *dp); void analogix_dp_reset(struct analogix_dp_device *dp); void analogix_dp_swreset(struct analogix_dp_device *dp); void analogix_dp_config_interrupt(struct analogix_dp_device *dp); void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, enum analog_power_block block, bool enable); void analogix_dp_init_analog_func(struct analogix_dp_device *dp); void analogix_dp_init_hpd(struct analogix_dp_device *dp); void analogix_dp_force_hpd(struct analogix_dp_device *dp); enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); void analogix_dp_reset_aux(struct analogix_dp_device *dp); void analogix_dp_init_aux(struct analogix_dp_device *dp); int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, unsigned int reg_addr, unsigned char data); int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, unsigned int reg_addr, unsigned char *data); int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, unsigned int reg_addr, unsigned int count, unsigned char data[]); int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, unsigned int reg_addr, unsigned int count, unsigned char data[]); int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, unsigned int device_addr, unsigned int reg_addr); int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, unsigned int device_addr, unsigned int reg_addr, unsigned int *data); int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, unsigned int device_addr, unsigned int reg_addr, unsigned int count, unsigned char edid[]); void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable); void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, enum pattern_set pattern); void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level); void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level); void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level); void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level); void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, u32 training_lane); void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, u32 training_lane); void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, u32 training_lane); void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, u32 training_lane); u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); void analogix_dp_reset_macro(struct analogix_dp_device *dp); void analogix_dp_init_video(struct analogix_dp_device *dp); void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, enum clock_recovery_m_value_type type, u32 m_value, u32 n_value); void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable); void analogix_dp_start_video(struct analogix_dp_device *dp); int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); #endif /* __DRM_ANALOGIX_DP__ */