/*
 * Copyright (c) 2025, Mediatek Inc. All rights reserved
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef MT6316_LOWPOWER_REG_H
#define MT6316_LOWPOWER_REG_H

#define MT6316_RG_LDO_VDIG18_SW_OP_EN_ADDR	0x197
#define MT6316_RG_LDO_VDIG18_HW0_OP_EN_ADDR	0x197
#define MT6316_RG_LDO_VDIG18_HW2_OP_EN_ADDR	0x197
#define MT6316_RG_LDO_VDIG18_RC0_OP_EN_ADDR	0x197
#define MT6316_RG_LDO_VDIG18_BUCK_OP_EN_ADDR	0x197
#define MT6316_RG_LDO_VDIG18_HW0_OP_MODE_ADDR	0x198
#define MT6316_RG_LDO_VDIG18_HW2_OP_MODE_ADDR	0x198
#define MT6316_RG_LDO_VDIG18_RC0_OP_MODE_ADDR	0x198
#define MT6316_RG_LDO_VDIG18_BUCK_OP_MODE_ADDR	0x198
#define MT6316_RG_VDIG18_PWROFF_OP_EN_ADDR	0x199
#define MT6316_RG_LDO_VDIG12_SW_OP_EN_ADDR	0x19B
#define MT6316_RG_LDO_VDIG12_HW0_OP_EN_ADDR	0x19B
#define MT6316_RG_LDO_VDIG12_HW2_OP_EN_ADDR	0x19B
#define MT6316_RG_LDO_VDIG12_RC0_OP_EN_ADDR	0x19B
#define MT6316_RG_LDO_VDIG12_BUCK_OP_EN_ADDR	0x19B
#define MT6316_RG_LDO_VDIG12_HW0_OP_MODE_ADDR	0x19C
#define MT6316_RG_LDO_VDIG12_HW2_OP_MODE_ADDR	0x19C
#define MT6316_RG_LDO_VDIG12_RC0_OP_MODE_ADDR	0x19C
#define MT6316_RG_LDO_VDIG12_BUCK_OP_MODE_ADDR	0x19C
#define MT6316_RG_VDIG12_PWROFF_OP_EN_ADDR	0x19D
#define MT6316_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR	0x148
#define MT6316_RG_BUCK_VBUCK1_ONLV_EN_ADDR	0x148
#define MT6316_RG_BUCK_VBUCK1_ONLV_EN_SHIFT	4
#define MT6316_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_SW_OP_EN_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR	0x149
#define MT6316_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR	0x150
#define MT6316_RG_BUCK_VBUCK2_ONLV_EN_ADDR	0x150
#define MT6316_RG_BUCK_VBUCK2_ONLV_EN_SHIFT	4
#define MT6316_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_SW_OP_EN_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR	0x151
#define MT6316_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR	0x158
#define MT6316_RG_BUCK_VBUCK3_ONLV_EN_ADDR	0x158
#define MT6316_RG_BUCK_VBUCK3_ONLV_EN_SHIFT	4
#define MT6316_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_SW_OP_EN_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR	0x159
#define MT6316_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR	0x160
#define MT6316_RG_BUCK_VBUCK4_ONLV_EN_ADDR	0x160
#define MT6316_RG_BUCK_VBUCK4_ONLV_EN_SHIFT	4
#define MT6316_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_SW_OP_EN_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR	0x161
#define MT6316_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR	0x161

#endif /* MT6316_LOWPOWER_REG_H */