/* * Copyright (c) 2025, Mediatek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /**************************************************************** * Auto generated by DE, please DO NOT modify this file directly. ****************************************************************/ #ifndef MT_SPM_REG_H #define MT_SPM_REG_H #include #include /************************************** * Define and Declare **************************************/ #define POWERON_CONFIG_EN (SPM_BASE + 0x000) #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x00C) #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x010) #define PCM_PWR_IO_EN (SPM_BASE + 0x014) #define PCM_CON0 (SPM_BASE + 0x018) #define PCM_CON1 (SPM_BASE + 0x01C) #define SPM_SRAM_SLEEP_CTRL (SPM_BASE + 0x020) #define SPM_CLK_CON (SPM_BASE + 0x024) #define SPM_CLK_SETTLE (SPM_BASE + 0x028) #define SPM_CLK_CON_1 (SPM_BASE + 0x02C) #define SPM_SW_RST_CON (SPM_BASE + 0x040) #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) #define R_SEC_READ_MASK (SPM_BASE + 0x050) #define R_ONE_TIME_LOCK_L (SPM_BASE + 0x054) #define R_ONE_TIME_LOCK_M (SPM_BASE + 0x058) #define R_ONE_TIME_LOCK_H (SPM_BASE + 0x05C) #define SSPM_CLK_CON (SPM_BASE + 0x084) #define SCP_CLK_CON (SPM_BASE + 0x088) #define SPM_SWINT (SPM_BASE + 0x090) #define SPM_SWINT_SET (SPM_BASE + 0x094) #define SPM_SWINT_CLR (SPM_BASE + 0x098) #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) #define MD32PCM_SCU_CTRL0 (SPM_BASE + 0x100) #define MD32PCM_SCU_CTRL1 (SPM_BASE + 0x104) #define MD32PCM_SCU_CTRL2 (SPM_BASE + 0x108) #define MD32PCM_SCU_CTRL3 (SPM_BASE + 0x10C) #define MD32PCM_SCU_STA0 (SPM_BASE + 0x110) #define SPM_IRQ_STA (SPM_BASE + 0x128) #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) #define MD32PCM_EVENT_STA (SPM_BASE + 0x134) #define SPM_WAKEUP_MISC (SPM_BASE + 0x140) #define SPM_CK_STA (SPM_BASE + 0x164) #define MD32PCM_STA (SPM_BASE + 0x190) #define MD32PCM_PC (SPM_BASE + 0x194) #define SPM_AP_STANDBY_CON (SPM_BASE + 0x200) #define CPU_WFI_EN (SPM_BASE + 0x204) #define CPU_WFI_EN_SET (SPM_BASE + 0x208) #define CPU_WFI_EN_CLR (SPM_BASE + 0x20C) #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210) #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214) #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218) #define MCUSYS_IDLE_STA (SPM_BASE + 0x21C) #define CPU_PWR_STATUS (SPM_BASE + 0x220) #define SW2SPM_WAKEUP (SPM_BASE + 0x224) #define SW2SPM_WAKEUP_SET (SPM_BASE + 0x228) #define SW2SPM_WAKEUP_CLR (SPM_BASE + 0x22C) #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x230) #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x234) #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x238) #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x23C) #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x240) #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x244) #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x248) #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x24C) #define SPM2MCUPM_CON (SPM_BASE + 0x250) #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x260) #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x264) #define SPM_CPU0_PWR_CON (SPM_BASE + 0x268) #define SPM_CPU1_PWR_CON (SPM_BASE + 0x26C) #define SPM_CPU2_PWR_CON (SPM_BASE + 0x270) #define SPM_CPU3_PWR_CON (SPM_BASE + 0x274) #define SPM_CPU4_PWR_CON (SPM_BASE + 0x278) #define SPM_CPU5_PWR_CON (SPM_BASE + 0x27C) #define SPM_CPU6_PWR_CON (SPM_BASE + 0x280) #define SPM_CPU7_PWR_CON (SPM_BASE + 0x284) #define SPM_MCUPM_SPMC_CON (SPM_BASE + 0x288) #define SPM_DPM_P2P_STA (SPM_BASE + 0x2A0) #define SPM_DPM_P2P_CON (SPM_BASE + 0x2A4) #define SPM_DPM_INTF_STA (SPM_BASE + 0x2A8) #define SPM_DPM_WB_CON (SPM_BASE + 0x2AC) #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x2B0) #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x2B4) #define SPM_PWRAP_CON (SPM_BASE + 0x300) #define SPM_PWRAP_CON_STA (SPM_BASE + 0x304) #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x308) #define SPM_PWRAP_CMD0 (SPM_BASE + 0x310) #define SPM_PWRAP_CMD1 (SPM_BASE + 0x314) #define SPM_PWRAP_CMD2 (SPM_BASE + 0x318) #define SPM_PWRAP_CMD3 (SPM_BASE + 0x31C) #define SPM_PWRAP_CMD4 (SPM_BASE + 0x320) #define SPM_PWRAP_CMD5 (SPM_BASE + 0x324) #define SPM_PWRAP_CMD6 (SPM_BASE + 0x328) #define SPM_PWRAP_CMD7 (SPM_BASE + 0x32C) #define SPM_PWRAP_CMD8 (SPM_BASE + 0x330) #define SPM_PWRAP_CMD9 (SPM_BASE + 0x334) #define SPM_PWRAP_CMD10 (SPM_BASE + 0x338) #define SPM_PWRAP_CMD11 (SPM_BASE + 0x33C) #define SPM_PWRAP_CMD12 (SPM_BASE + 0x340) #define SPM_PWRAP_CMD13 (SPM_BASE + 0x344) #define SPM_PWRAP_CMD14 (SPM_BASE + 0x348) #define SPM_PWRAP_CMD15 (SPM_BASE + 0x34C) #define SPM_PWRAP_CMD16 (SPM_BASE + 0x350) #define SPM_PWRAP_CMD17 (SPM_BASE + 0x354) #define SPM_PWRAP_CMD18 (SPM_BASE + 0x358) #define SPM_PWRAP_CMD19 (SPM_BASE + 0x35C) #define SPM_PWRAP_CMD20 (SPM_BASE + 0x360) #define SPM_PWRAP_CMD21 (SPM_BASE + 0x364) #define SPM_PWRAP_CMD22 (SPM_BASE + 0x368) #define SPM_PWRAP_CMD23 (SPM_BASE + 0x36C) #define SPM_PWRAP_CMD24 (SPM_BASE + 0x370) #define SPM_PWRAP_CMD25 (SPM_BASE + 0x374) #define SPM_PWRAP_CMD26 (SPM_BASE + 0x378) #define SPM_PWRAP_CMD27 (SPM_BASE + 0x37C) #define SPM_PWRAP_CMD28 (SPM_BASE + 0x380) #define SPM_PWRAP_CMD29 (SPM_BASE + 0x384) #define SPM_PWRAP_CMD30 (SPM_BASE + 0x388) #define SPM_PWRAP_CMD31 (SPM_BASE + 0x38C) #define DVFSRC_EVENT_STA (SPM_BASE + 0x390) #define SPM_FORCE_DVFS (SPM_BASE + 0x394) #define SPM_DVFS_STA (SPM_BASE + 0x398) #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x39C) #define SPM_DVFS_LEVEL (SPM_BASE + 0x3A0) #define SPM_DVFS_OPP (SPM_BASE + 0x3A4) #define SPM_ULTRA_REQ (SPM_BASE + 0x3A8) #define SPM_DVFS_CON (SPM_BASE + 0x3AC) #define SPM_SRAMRC_CON (SPM_BASE + 0x3B0) #define SPM_SRCLKENRC_CON (SPM_BASE + 0x3B4) #define SPM_DPSW_CON (SPM_BASE + 0x3B8) #define ULPOSC_CON (SPM_BASE + 0x400) #define AP_MDSRC_REQ (SPM_BASE + 0x404) #define SPM2MD_SWITCH_CTRL (SPM_BASE + 0x408) #define RC_SPM_CTRL (SPM_BASE + 0x40C) #define SPM2GPUPM_CON (SPM_BASE + 0x410) #define SPM2APU_CON (SPM_BASE + 0x414) #define SPM2EFUSE_CON (SPM_BASE + 0x418) #define SPM2DFD_CON (SPM_BASE + 0x41C) #define RSV_PLL_CON (SPM_BASE + 0x420) #define EMI_SLB_CON (SPM_BASE + 0x424) #define SPM_SUSPEND_FLAG_CON (SPM_BASE + 0x428) #define SPM2PMSR_CON (SPM_BASE + 0x42C) #define SPM_TOPCK_RTFF_CON (SPM_BASE + 0x430) #define EMI_SHF_CON (SPM_BASE + 0x434) #define CIRQ_BYPASS_CON (SPM_BASE + 0x438) #define AOC_VCORE_SRAM_CON (SPM_BASE + 0x43C) #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0 (SPM_BASE + 0x460) #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1 (SPM_BASE + 0x464) #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2 (SPM_BASE + 0x468) #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3 (SPM_BASE + 0x46C) #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0 (SPM_BASE + 0x470) #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1 (SPM_BASE + 0x474) #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2 (SPM_BASE + 0x478) #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3 (SPM_BASE + 0x47C) #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0 (SPM_BASE + 0x480) #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1 (SPM_BASE + 0x484) #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2 (SPM_BASE + 0x488) #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3 (SPM_BASE + 0x48C) #define REG_MODULE_SW_CG_F26M_REQ_MASK_0 (SPM_BASE + 0x490) #define REG_MODULE_SW_CG_F26M_REQ_MASK_1 (SPM_BASE + 0x494) #define REG_MODULE_SW_CG_F26M_REQ_MASK_2 (SPM_BASE + 0x498) #define REG_MODULE_SW_CG_F26M_REQ_MASK_3 (SPM_BASE + 0x49C) #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0 (SPM_BASE + 0x4A0) #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1 (SPM_BASE + 0x4A4) #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2 (SPM_BASE + 0x4A8) #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3 (SPM_BASE + 0x4AC) #define REG_PWR_STATUS_DDREN_REQ_MASK (SPM_BASE + 0x4B0) #define REG_PWR_STATUS_VRF18_REQ_MASK (SPM_BASE + 0x4B4) #define REG_PWR_STATUS_INFRA_REQ_MASK (SPM_BASE + 0x4B8) #define REG_PWR_STATUS_F26M_REQ_MASK (SPM_BASE + 0x4BC) #define REG_PWR_STATUS_PMIC_REQ_MASK (SPM_BASE + 0x4C0) #define REG_PWR_STATUS_VCORE_REQ_MASK (SPM_BASE + 0x4C4) #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK (SPM_BASE + 0x4C8) #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK (SPM_BASE + 0x4CC) #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK (SPM_BASE + 0x4D0) #define REG_PWR_STATUS_MSB_F26M_REQ_MASK (SPM_BASE + 0x4D4) #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK (SPM_BASE + 0x4D8) #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK (SPM_BASE + 0x4DC) #define REG_MODULE_BUSY_DDREN_REQ_MASK (SPM_BASE + 0x4E0) #define REG_MODULE_BUSY_VRF18_REQ_MASK (SPM_BASE + 0x4E4) #define REG_MODULE_BUSY_INFRA_REQ_MASK (SPM_BASE + 0x4E8) #define REG_MODULE_BUSY_F26M_REQ_MASK (SPM_BASE + 0x4EC) #define REG_MODULE_BUSY_PMIC_REQ_MASK (SPM_BASE + 0x4F0) #define REG_MODULE_BUSY_VCORE_REQ_MASK (SPM_BASE + 0x4F4) #define SYS_TIMER_CON (SPM_BASE + 0x500) #define SYS_TIMER_VALUE_L (SPM_BASE + 0x504) #define SYS_TIMER_VALUE_H (SPM_BASE + 0x508) #define SYS_TIMER_START_L (SPM_BASE + 0x50C) #define SYS_TIMER_START_H (SPM_BASE + 0x510) #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x514) #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x518) #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x51C) #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x520) #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x524) #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x528) #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x52C) #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x530) #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x534) #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x538) #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x53C) #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x540) #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x544) #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x548) #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x54C) #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x550) #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x554) #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x558) #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x55C) #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x560) #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x564) #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x568) #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x56C) #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x570) #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x574) #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x578) #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x57C) #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x580) #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x584) #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x588) #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x58C) #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x590) #define PCM_TIMER_VAL (SPM_BASE + 0x594) #define PCM_TIMER_OUT (SPM_BASE + 0x598) #define SPM_COUNTER_0 (SPM_BASE + 0x59C) #define SPM_COUNTER_1 (SPM_BASE + 0x5A0) #define SPM_COUNTER_2 (SPM_BASE + 0x5A4) #define PCM_WDT_VAL (SPM_BASE + 0x5A8) #define PCM_WDT_OUT (SPM_BASE + 0x5AC) #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) #define SPM_SW_RSV_0 (SPM_BASE + 0x610) #define SPM_SW_RSV_1 (SPM_BASE + 0x614) #define SPM_SW_RSV_2 (SPM_BASE + 0x618) #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) #define SPM_SW_RSV_4 (SPM_BASE + 0x620) #define SPM_SW_RSV_5 (SPM_BASE + 0x624) #define SPM_SW_RSV_6 (SPM_BASE + 0x628) #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) #define SPM_SW_RSV_8 (SPM_BASE + 0x630) #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) #define SPM_RSV_CON_0 (SPM_BASE + 0x650) #define SPM_RSV_CON_1 (SPM_BASE + 0x654) #define SPM_RSV_STA_0 (SPM_BASE + 0x658) #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) #define SPM_SPARE_CON (SPM_BASE + 0x660) #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) #define SPM_DDREN_ACK_SEL_CON (SPM_BASE + 0x680) #define SPM_SW_FLAG_2 (SPM_BASE + 0x684) #define SPM_SW_DEBUG_2 (SPM_BASE + 0x688) #define SPM_DV_CON_0 (SPM_BASE + 0x68C) #define SPM_DV_CON_1 (SPM_BASE + 0x690) #define SPM_SEMA_M0 (SPM_BASE + 0x69C) #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) #define VCORE_RTFF_CTRL_MASK_SET (SPM_BASE + 0x6C4) #define VCORE_RTFF_CTRL_MASK_CLR (SPM_BASE + 0x6C8) #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) #define SPM2SCP_MAILBOX (SPM_BASE + 0x6EC) #define SCP2SPM_MAILBOX (SPM_BASE + 0x6F0) #define SCP_AOV_BUS_CON (SPM_BASE + 0x6F4) #define VCORE_RTFF_CTRL_MASK (SPM_BASE + 0x6F8) #define SPM_SRAM_SRCLKENO_MASK (SPM_BASE + 0x6FC) #define EMI_PDN_REQ (SPM_BASE + 0x700) #define EMI_BUSY_REQ (SPM_BASE + 0x704) #define EMI_RESERVED_STA (SPM_BASE + 0x708) #define SC_UNIVPLL_DIV_RST_B (SPM_BASE + 0x70C) #define ECO_ARMPLL_DIV_CLOCK_OFF (SPM_BASE + 0x710) #define SPM_MCDSR_CG_CHECK_X1 (SPM_BASE + 0x714) #define SPM_SODI2_CG_CHECK_X1 (SPM_BASE + 0x718) #define SPM_WAKEUP_STA (SPM_BASE + 0x800) #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x804) #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x808) #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x80C) #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x810) #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x814) #define SPM_SRC_REQ (SPM_BASE + 0x818) #define SPM_SRC_MASK_0 (SPM_BASE + 0x81C) #define SPM_SRC_MASK_1 (SPM_BASE + 0x820) #define SPM_SRC_MASK_2 (SPM_BASE + 0x824) #define SPM_SRC_MASK_3 (SPM_BASE + 0x828) #define SPM_SRC_MASK_4 (SPM_BASE + 0x82C) #define SPM_SRC_MASK_5 (SPM_BASE + 0x830) #define SPM_SRC_MASK_6 (SPM_BASE + 0x834) #define SPM_SRC_MASK_7 (SPM_BASE + 0x838) #define SPM_SRC_MASK_8 (SPM_BASE + 0x83C) #define SPM_SRC_MASK_9 (SPM_BASE + 0x840) #define SPM_SRC_MASK_10 (SPM_BASE + 0x844) #define SPM_SRC_MASK_11 (SPM_BASE + 0x848) #define SPM_SRC_MASK_12 (SPM_BASE + 0x84C) #define SPM_REQ_STA_0 (SPM_BASE + 0x850) #define SPM_REQ_STA_1 (SPM_BASE + 0x854) #define SPM_REQ_STA_2 (SPM_BASE + 0x858) #define SPM_REQ_STA_3 (SPM_BASE + 0x85C) #define SPM_REQ_STA_4 (SPM_BASE + 0x860) #define SPM_REQ_STA_5 (SPM_BASE + 0x864) #define SPM_REQ_STA_6 (SPM_BASE + 0x868) #define SPM_REQ_STA_7 (SPM_BASE + 0x86C) #define SPM_REQ_STA_8 (SPM_BASE + 0x870) #define SPM_REQ_STA_9 (SPM_BASE + 0x874) #define SPM_REQ_STA_10 (SPM_BASE + 0x878) #define SPM_REQ_STA_11 (SPM_BASE + 0x87C) #define SPM_REQ_STA_12 (SPM_BASE + 0x880) #define SPM_IPC_WAKEUP_REQ (SPM_BASE + 0x884) #define IPC_WAKEUP_REQ_MASK_STA (SPM_BASE + 0x888) #define SPM_EVENT_CON_MISC (SPM_BASE + 0x88C) #define DDREN_DBC_CON (SPM_BASE + 0x890) #define SPM_RESOURCE_ACK_CON_0 (SPM_BASE + 0x894) #define SPM_RESOURCE_ACK_CON_1 (SPM_BASE + 0x898) #define SPM_RESOURCE_ACK_MASK_0 (SPM_BASE + 0x89C) #define SPM_RESOURCE_ACK_MASK_1 (SPM_BASE + 0x8A0) #define SPM_RESOURCE_ACK_MASK_2 (SPM_BASE + 0x8A4) #define SPM_RESOURCE_ACK_MASK_3 (SPM_BASE + 0x8A8) #define SPM_RESOURCE_ACK_MASK_4 (SPM_BASE + 0x8AC) #define SPM_RESOURCE_ACK_MASK_5 (SPM_BASE + 0x8B0) #define SPM_RESOURCE_ACK_MASK_6 (SPM_BASE + 0x8B4) #define SPM_EVENT_COUNTER_CLEAR (SPM_BASE + 0x8B8) #define SPM_VCORE_EVENT_COUNT_STA (SPM_BASE + 0x8BC) #define SPM_PMIC_EVENT_COUNT_STA (SPM_BASE + 0x8C0) #define SPM_SRCCLKENA_EVENT_COUNT_STA (SPM_BASE + 0x8C4) #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x8C8) #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x8CC) #define SPM_EMI_EVENT_COUNT_STA (SPM_BASE + 0x8D0) #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x8D4) #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x8D8) #define PCM_WDT_LATCH_0 (SPM_BASE + 0x8DC) #define PCM_WDT_LATCH_1 (SPM_BASE + 0x8E0) #define PCM_WDT_LATCH_2 (SPM_BASE + 0x8E4) #define PCM_WDT_LATCH_3 (SPM_BASE + 0x8E8) #define PCM_WDT_LATCH_4 (SPM_BASE + 0x8EC) #define PCM_WDT_LATCH_5 (SPM_BASE + 0x8F0) #define PCM_WDT_LATCH_6 (SPM_BASE + 0x8F4) #define PCM_WDT_LATCH_7 (SPM_BASE + 0x8F8) #define PCM_WDT_LATCH_8 (SPM_BASE + 0x8FC) #define PCM_WDT_LATCH_9 (SPM_BASE + 0x900) #define PCM_WDT_LATCH_10 (SPM_BASE + 0x904) #define PCM_WDT_LATCH_11 (SPM_BASE + 0x908) #define PCM_WDT_LATCH_12 (SPM_BASE + 0x90C) #define PCM_WDT_LATCH_13 (SPM_BASE + 0x910) #define PCM_WDT_LATCH_14 (SPM_BASE + 0x914) #define PCM_WDT_LATCH_15 (SPM_BASE + 0x918) #define PCM_WDT_LATCH_16 (SPM_BASE + 0x91C) #define PCM_WDT_LATCH_17 (SPM_BASE + 0x920) #define PCM_WDT_LATCH_18 (SPM_BASE + 0x924) #define PCM_WDT_LATCH_19 (SPM_BASE + 0x928) #define PCM_WDT_LATCH_20 (SPM_BASE + 0x92C) #define PCM_WDT_LATCH_21 (SPM_BASE + 0x930) #define PCM_WDT_LATCH_22 (SPM_BASE + 0x934) #define PCM_WDT_LATCH_23 (SPM_BASE + 0x938) #define PCM_WDT_LATCH_24 (SPM_BASE + 0x93C) #define PCM_WDT_LATCH_25 (SPM_BASE + 0x940) #define PCM_WDT_LATCH_26 (SPM_BASE + 0x944) #define PCM_WDT_LATCH_27 (SPM_BASE + 0x948) #define PCM_WDT_LATCH_28 (SPM_BASE + 0x94C) #define PCM_WDT_LATCH_29 (SPM_BASE + 0x950) #define PCM_WDT_LATCH_30 (SPM_BASE + 0x954) #define PCM_WDT_LATCH_31 (SPM_BASE + 0x958) #define PCM_WDT_LATCH_32 (SPM_BASE + 0x95C) #define PCM_WDT_LATCH_33 (SPM_BASE + 0x960) #define PCM_WDT_LATCH_34 (SPM_BASE + 0x964) #define PCM_WDT_LATCH_35 (SPM_BASE + 0x968) #define PCM_WDT_LATCH_36 (SPM_BASE + 0x96C) #define PCM_WDT_LATCH_37 (SPM_BASE + 0x970) #define PCM_WDT_LATCH_38 (SPM_BASE + 0x974) #define PCM_WDT_LATCH_39 (SPM_BASE + 0x978) #define PCM_WDT_LATCH_40 (SPM_BASE + 0x97C) #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x980) #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x984) #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x988) #define PCM_WDT_LATCH_SPARE_3 (SPM_BASE + 0x98C) #define PCM_WDT_LATCH_SPARE_4 (SPM_BASE + 0x990) #define PCM_WDT_LATCH_SPARE_5 (SPM_BASE + 0x994) #define PCM_WDT_LATCH_SPARE_6 (SPM_BASE + 0x998) #define PCM_WDT_LATCH_SPARE_7 (SPM_BASE + 0x99C) #define PCM_WDT_LATCH_SPARE_8 (SPM_BASE + 0x9A0) #define PCM_WDT_LATCH_SPARE_9 (SPM_BASE + 0x9A4) #define DRAMC_GATING_ERR_LATCH_0 (SPM_BASE + 0x9A8) #define DRAMC_GATING_ERR_LATCH_1 (SPM_BASE + 0x9AC) #define DRAMC_GATING_ERR_LATCH_2 (SPM_BASE + 0x9B0) #define DRAMC_GATING_ERR_LATCH_3 (SPM_BASE + 0x9B4) #define DRAMC_GATING_ERR_LATCH_4 (SPM_BASE + 0x9B8) #define DRAMC_GATING_ERR_LATCH_5 (SPM_BASE + 0x9BC) #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x9C0) #define SPM_DEBUG_CON (SPM_BASE + 0x9C4) #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x9C8) #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x9CC) #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x9D0) #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x9D4) #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x9D8) #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x9DC) #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x9E0) #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x9E4) #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x9E8) #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x9EC) #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x9F0) #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x9F4) #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x9F8) #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x9FC) #define MD1_PWR_CON (SPM_BASE + 0xE00) #define CONN_PWR_CON (SPM_BASE + 0xE04) #define IFR_PWR_CON (SPM_BASE + 0xE08) #define PERI_PWR_CON (SPM_BASE + 0xE0C) #define UFS0_PWR_CON (SPM_BASE + 0xE10) #define UFS0_PHY_PWR_CON (SPM_BASE + 0xE14) #define AUDIO_PWR_CON (SPM_BASE + 0xE18) #define ADSP_TOP_PWR_CON (SPM_BASE + 0xE1C) #define ADSP_INFRA_PWR_CON (SPM_BASE + 0xE20) #define ADSP_AO_PWR_CON (SPM_BASE + 0xE24) #define ISP_IMG1_PWR_CON (SPM_BASE + 0xE28) #define ISP_IMG2_PWR_CON (SPM_BASE + 0xE2C) #define ISP_IPE_PWR_CON (SPM_BASE + 0xE30) #define ISP_VCORE_PWR_CON (SPM_BASE + 0xE34) #define VDE0_PWR_CON (SPM_BASE + 0xE38) #define VDE1_PWR_CON (SPM_BASE + 0xE3C) #define VEN0_PWR_CON (SPM_BASE + 0xE40) #define VEN1_PWR_CON (SPM_BASE + 0xE44) #define CAM_MAIN_PWR_CON (SPM_BASE + 0xE48) #define CAM_MRAW_PWR_CON (SPM_BASE + 0xE4C) #define CAM_SUBA_PWR_CON (SPM_BASE + 0xE50) #define CAM_SUBB_PWR_CON (SPM_BASE + 0xE54) #define CAM_SUBC_PWR_CON (SPM_BASE + 0xE58) #define CAM_VCORE_PWR_CON (SPM_BASE + 0xE5C) #define CAM_CCU_PWR_CON (SPM_BASE + 0xE60) #define CAM_CCU_AO_PWR_CON (SPM_BASE + 0xE64) #define MDP0_PWR_CON (SPM_BASE + 0xE68) #define MDP1_PWR_CON (SPM_BASE + 0xE6C) #define DIS0_PWR_CON (SPM_BASE + 0xE70) #define DIS1_PWR_CON (SPM_BASE + 0xE74) #define MM_INFRA_PWR_CON (SPM_BASE + 0xE78) #define MM_PROC_PWR_CON (SPM_BASE + 0xE7C) #define DP_TX_PWR_CON (SPM_BASE + 0xE80) #define SCP_CORE_PWR_CON (SPM_BASE + 0xE84) #define SCP_PERI_PWR_CON (SPM_BASE + 0xE88) #define DPM0_PWR_CON (SPM_BASE + 0xE8C) #define DPM1_PWR_CON (SPM_BASE + 0xE90) #define EMI0_PWR_CON (SPM_BASE + 0xE94) #define EMI1_PWR_CON (SPM_BASE + 0xE98) #define CSI_RX_PWR_CON (SPM_BASE + 0xE9C) #define SSRSYS_PWR_CON (SPM_BASE + 0xEA0) #define SSPM_PWR_CON (SPM_BASE + 0xEA4) #define SSUSB_PWR_CON (SPM_BASE + 0xEA8) #define SSUSB_PHY_PWR_CON (SPM_BASE + 0xEAC) #define CPUEB_PWR_CON (SPM_BASE + 0xEB0) #define MFG0_PWR_CON (SPM_BASE + 0xEB4) #define MFG1_PWR_CON (SPM_BASE + 0xEB8) #define MFG2_PWR_CON (SPM_BASE + 0xEBC) #define MFG3_PWR_CON (SPM_BASE + 0xEC0) #define MFG4_PWR_CON (SPM_BASE + 0xEC4) #define MFG5_PWR_CON (SPM_BASE + 0xEC8) #define MFG6_PWR_CON (SPM_BASE + 0xECC) #define MFG7_PWR_CON (SPM_BASE + 0xED0) #define ADSP_HRE_SRAM_CON (SPM_BASE + 0xED4) #define CCU_SLEEP_SRAM_CON (SPM_BASE + 0xED8) #define EFUSE_SRAM_CON (SPM_BASE + 0xEDC) #define EMI_HRE_SRAM_CON (SPM_BASE + 0xEE0) #define EMI_SLB_SRAM_CON (SPM_BASE + 0xEE4) #define INFRA_HRE_SRAM_CON (SPM_BASE + 0xEE8) #define INFRA_SLEEP_SRAM_CON (SPM_BASE + 0xEEC) #define MM_HRE_SRAM_CON (SPM_BASE + 0xEF0) #define NTH_EMI_SLB_SRAM_CON (SPM_BASE + 0xEF4) #define NTH_EMI_SLB_SRAM_ACK (SPM_BASE + 0xEF8) #define PERI_SLEEP_SRAM_CON (SPM_BASE + 0xEFC) #define SPM_SRAM_CON (SPM_BASE + 0xF00) #define SSPM_SRAM_CON (SPM_BASE + 0xF04) #define SSR_SLEEP_SRAM_CON (SPM_BASE + 0xF08) #define STH_EMI_SLB_SRAM_CON (SPM_BASE + 0xF0C) #define STH_EMI_SLB_SRAM_ACK (SPM_BASE + 0xF10) #define UFS_PDN_SRAM_CON (SPM_BASE + 0xF14) #define UFS_SLEEP_SRAM_CON (SPM_BASE + 0xF18) #define UNIPRO_PDN_SRAM_CON (SPM_BASE + 0xF1C) #define CPU_BUCK_ISO_CON (SPM_BASE + 0xF20) #define MD_BUCK_ISO_CON (SPM_BASE + 0xF24) #define SOC_BUCK_ISO_CON (SPM_BASE + 0xF28) #define SOC_BUCK_ISO_CON_SET (SPM_BASE + 0xF2C) #define SOC_BUCK_ISO_CON_CLR (SPM_BASE + 0xF30) #define SOC_BUCK_ISO_CON_2 (SPM_BASE + 0xF34) #define SOC_BUCK_ISO_CON_2_SET (SPM_BASE + 0xF38) #define SOC_BUCK_ISO_CON_2_CLR (SPM_BASE + 0xF3C) #define PWR_STATUS (SPM_BASE + 0xF40) #define PWR_STATUS_2ND (SPM_BASE + 0xF44) #define PWR_STATUS_MSB (SPM_BASE + 0xF48) #define PWR_STATUS_MSB_2ND (SPM_BASE + 0xF4C) #define XPU_PWR_STATUS (SPM_BASE + 0xF50) #define XPU_PWR_STATUS_2ND (SPM_BASE + 0xF54) #define DFD_SOC_PWR_LATCH (SPM_BASE + 0xF58) #define SUBSYS_PM_BYPASS (SPM_BASE + 0xF5C) #define VADSP_HRE_SRAM_CON (SPM_BASE + 0xF60) #define VADSP_HRE_SRAM_ACK (SPM_BASE + 0xF64) #define GCPU_SRAM_CON (SPM_BASE + 0xF68) #define GCPU_SRAM_ACK (SPM_BASE + 0xF6C) #define EDP_TX_PWR_CON (SPM_BASE + 0xF70) #define PCIE_PWR_CON (SPM_BASE + 0xF74) #define PCIE_PHY_PWR_CON (SPM_BASE + 0xF78) #define SPM_TWAM_CON (SPM_BASE + 0xF80) #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0xF84) #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0xF88) #define SPM_TWAM_LAST_STA_0 (SPM_BASE + 0xF8C) #define SPM_TWAM_LAST_STA_1 (SPM_BASE + 0xF90) #define SPM_TWAM_LAST_STA_2 (SPM_BASE + 0xF94) #define SPM_TWAM_LAST_STA_3 (SPM_BASE + 0xF98) #define SPM_TWAM_CURR_STA_0 (SPM_BASE + 0xF9C) #define SPM_TWAM_CURR_STA_1 (SPM_BASE + 0xFA0) #define SPM_TWAM_CURR_STA_2 (SPM_BASE + 0xFA4) #define SPM_TWAM_CURR_STA_3 (SPM_BASE + 0xFA8) #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0xFAC) #define EC_SUSPEND_PIN 140 /* POWERON_CONFIG_EN (0x1C001000+0x000) */ #define BCLK_CG_EN_LSB BIT(0) /* 1b */ #define PROJECT_CODE_LSB BIT(16) /* 16b */ /* SPM_POWER_ON_VAL0 (0x1C001000+0x004) */ #define POWER_ON_VAL0_LSB BIT(0) /* 32b */ /* SPM_POWER_ON_VAL1 (0x1C001000+0x008) */ #define POWER_ON_VAL1_LSB BIT(0) /* 32b */ /* SPM_POWER_ON_VAL2 (0x1C001000+0x00C) */ #define POWER_ON_VAL2_LSB BIT(0) /* 32b */ /* SPM_POWER_ON_VAL3 (0x1C001000+0x010) */ #define POWER_ON_VAL3_LSB BIT(0) /* 32b */ /* PCM_PWR_IO_EN (0x1C001000+0x014) */ #define PCM_PWR_IO_EN_LSB BIT(0) /* 8b */ /* PCM_CON0 (0x1C001000+0x018) */ #define PCM_CK_EN_LSB BIT(2) /* 1b */ #define PCM_SW_RESET_LSB BIT(15) /* 1b */ #define PCM_CON0_PROJECT_CODE_LSB BIT(16) /* 16b */ /* PCM_CON1 (0x1C001000+0x01C) */ #define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) /* 1b */ #define REG_PCM_TIMER_EN_LSB BIT(5) /* 1b */ #define REG_PCM_WDT_EN_LSB BIT(8) /* 1b */ #define REG_PCM_WDT_WAKE_LSB BIT(9) /* 1b */ #define REG_SSPM_APB_P2P_EN_LSB BIT(10) /* 1b */ #define REG_MCUPM_APB_P2P_EN_LSB BIT(11) /* 1b */ #define REG_RSV_APB_P2P_EN_LSB BIT(12) /* 1b */ #define RG_PCM_IRQ_MSK_LSB BIT(15) /* 1b */ #define PCM_CON1_PROJECT_CODE_LSB BIT(16) /* 16b */ /* SPM_SRAM_SLEEP_CTRL (0x1C001000+0x020) */ #define REG_SRAM_ISO_ACTIVE_LSB BIT(0) /* 8b */ #define REG_SRAM_SLP2ISO_TIME_LSB BIT(8) /* 8b */ #define REG_SPM_SRAM_CTRL_MUX_LSB BIT(16) /* 1b */ #define REG_SRAM_SLEEP_TIME_LSB BIT(24) /* 8b */ /* SPM_CLK_CON (0x1C001000+0x024) */ #define REG_SPM_LOCK_INFRA_DCM_LSB BIT(0) /* 1b */ #define REG_CXO32K_REMOVE_EN_LSB BIT(1) /* 1b */ #define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB BIT(4) /* 3b */ #define REG_SRCLKENO0_SRC_MASK_B_LSB BIT(8) /* 8b */ #define REG_SRCLKENO1_SRC_MASK_B_LSB BIT(16) /* 8b */ #define REG_SRCLKENO2_SRC_MASK_B_LSB BIT(24) /* 8b */ /* SPM_CLK_SETTLE (0x1C001000+0x028) */ #define SYSCLK_SETTLE_LSB IT(0) /* 28b */ /* SPM_SW_RST_CON (0x1C001000+0x040) */ #define SPM_SW_RST_CON_LSB BIT(0) /* 16b */ #define SPM_SW_RST_CON_PROJECT_CODE_LSB BIT(16) /* 16b */ /* SPM_SW_RST_CON_SET (0x1C001000+0x044) */ #define SPM_SW_RST_CON_SET_LSB BIT(0) /* 16b */ #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB BIT(16) /* 16b */ /* SPM_SW_RST_CON_CLR (0x1C001000+0x048) */ #define SPM_SW_RST_CON_CLR_LSB BIT(0) /* 16b */ #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB BIT(16) /* 16b */ /* R_SEC_READ_MASK (0x1C001000+0x050) */ #define SPM_SEC_READ_MASK_LSB BIT(0) /* 1b */ /* R_ONE_TIME_LOCK_L (0x1C001000+0x054) */ #define SPM_ONE_TIME_LOCK_L_LSB BIT(0) /* 32b */ /* R_ONE_TIME_LOCK_M (0x1C001000+0x058) */ #define SPM_ONE_TIME_LOCK_M_LSB BIT(0) /* 32b */ /* R_ONE_TIME_LOCK_H (0x1C001000+0x05C) */ #define SPM_ONE_TIME_LOCK_H_LSB BIT(0) /* 32b */ /* SSPM_CLK_CON (0x1C001000+0x084) */ #define REG_SSPM_26M_CK_SEL_LSB BIT(0) /* 1b */ #define REG_SSPM_DCM_EN_LSB BIT(1) /* 1b */ /* SCP_CLK_CON (0x1C001000+0x088) */ #define REG_SCP_26M_CK_SEL_LSB BIT(0) /* 1b */ #define REG_SCP_DCM_EN_LSB BIT(1) /* 1b */ #define SCP_SECURE_VREQ_MASK_LSB BIT(2) /* 1b */ #define SCP_SLP_REQ_LSB BIT(3) /* 1b */ #define SCP_SLP_ACK_LSB BIT(4) /* 1b */ /* SPM_SWINT (0x1C001000+0x090) */ #define SPM_SWINT_LSB BIT(0) /* 32b */ /* SPM_SWINT_SET (0x1C001000+0x094) */ #define SPM_SWINT_SET_LSB BIT(0) /* 32b */ /* SPM_SWINT_CLR (0x1C001000+0x098) */ #define SPM_SWINT_CLR_LSB BIT(0) /* 32b */ /* SPM_CPU_WAKEUP_EVENT (0x1C001000+0x0B0) */ #define REG_CPU_WAKEUP_LSB BIT(0) /* 1b */ /* SPM_IRQ_MASK (0x1C001000+0x0B4) */ #define REG_SPM_IRQ_MASK_LSB BIT(0) /* 32b */ /* MD32PCM_SCU_CTRL0 (0x1C001000+0x100) */ #define MD32PCM_CTRL0_LSB BIT(0) /* 32b */ /* MD32PCM_SCU_CTRL1 (0x1C001000+0x104) */ #define MD32PCM_CTRL1_LSB BIT(0) /* 32b */ /* MD32PCM_SCU_CTRL2 (0x1C001000+0x108) */ #define MD32PCM_CTRL2_LSB BIT(0) /* 32b */ /* MD32PCM_SCU_CTRL3 (0x1C001000+0x10C) */ #define MD32PCM_CTRL3_LSB BIT(0) /* 32b */ /* MD32PCM_SCU_STA0 (0x1C001000+0x110) */ #define MD32PCM_STA0_LSB BIT(0) /* 32b */ /* SPM_IRQ_STA (0x1C001000+0x128) */ #define PCM_IRQ_LSB BIT(3) /* 1b */ /* MD32PCM_WAKEUP_STA (0x1C001000+0x130) */ #define MD32PCM_WAKEUP_STA_LSB BIT(0) /* 32b */ /* MD32PCM_EVENT_STA (0x1C001000+0x134) */ #define MD32PCM_EVENT_STA_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_MISC (0x1C001000+0x140) */ #define SRCLKEN_RC_ERR_INT_LSB BIT(0) /* 1b */ #define SPM_TIMEOUT_WAKEUP_0_LSB BIT(1) /* 1b */ #define SPM_TIMEOUT_WAKEUP_1_LSB BIT(2) /* 1b */ #define SPM_TIMEOUT_WAKEUP_2_LSB BIT(3) /* 1b */ #define DVFSRC_IRQ_LSB BIT(4) /* 1b */ #define TWAM_IRQ_B_LSB BIT(5) /* 1b */ #define SPM_ACK_CHK_WAKEUP_0_LSB BIT(6) /* 1b */ #define SPM_ACK_CHK_WAKEUP_1_LSB BIT(7) /* 1b */ #define SPM_ACK_CHK_WAKEUP_2_LSB BIT(8) /* 1b */ #define SPM_ACK_CHK_WAKEUP_3_LSB BIT(9) /* 1b */ #define SPM_ACK_CHK_WAKEUP_ALL_LSB BIT(10) /* 1b */ #define VLP_BUS_TIMEOUT_IRQ_LSB BIT(11) /* 1b */ #define PCM_TIMER_EVENT_LSB BIT(16) /* 1b */ #define PMIC_EINT_OUT_LSB BIT(19) /* 2b */ #define PMIC_IRQ_ACK_LSB BIT(30) /* 1b */ #define PMIC_SCP_IRQ_LSB BIT(31) /* 1b */ /* SPM_CK_STA (0x1C001000+0x164) */ #define PCM_CK_SEL_O_LSB BIT(0) /* 4b */ #define EXT_SRC_STA_LSB BIT(4) /* 3b */ #define CK_SLEEP_EN_LSB BIT(8) /* 1b */ #define SPM_SRAM_CTRL_CK_SEL_LSB BIT(9) /* 1b */ /* MD32PCM_STA (0x1C001000+0x190) */ #define MD32PCM_HALT_LSB BIT(0) /* 1b */ #define MD32PCM_GATED_LSB BIT(1) /* 1b */ /* MD32PCM_PC (0x1C001000+0x194) */ #define MON_PC_LSB BIT(0) /* 32b */ /* SPM_AP_STANDBY_CON (0x1C001000+0x200) */ #define REG_WFI_OP_LSB BIT(0) /* 1b */ #define REG_WFI_TYPE_LSB BIT(1) /* 1b */ #define REG_MP0_CPUTOP_IDLE_MASK_LSB BIT(2) /* 1b */ #define REG_MP1_CPUTOP_IDLE_MASK_LSB BIT(3) /* 1b */ #define REG_MCUSYS_IDLE_MASK_LSB BIT(4) /* 1b */ #define REG_CSYSPWRUP_REQ_MASK_LSB BIT(5) /* 1b */ #define WFI_AF_SEL_LSB BIT(16) /* 8b */ #define CPU_SLEEP_WFI_LSB BIT(31) /* 1b */ /* CPU_WFI_EN (0x1C001000+0x204) */ #define CPU_WFI_EN_LSB BIT(0) /* 8b */ /* CPU_WFI_EN_SET (0x1C001000+0x208) */ #define CPU_WFI_EN_SET_LSB BIT(0) /* 8b */ /* CPU_WFI_EN_CLR (0x1C001000+0x20C) */ #define CPU_WFI_EN_CLR_LSB BIT(0) /* 8b */ /* EXT_INT_WAKEUP_REQ (0x1C001000+0x210) */ #define EXT_INT_WAKEUP_REQ_LSB BIT(0) /* 10b */ /* EXT_INT_WAKEUP_REQ_SET (0x1C001000+0x214) */ #define EXT_INT_WAKEUP_REQ_SET_LSB BIT(0) /* 10b */ /* EXT_INT_WAKEUP_REQ_CLR (0x1C001000+0x218) */ #define EXT_INT_WAKEUP_REQ_CLR_LSB BIT(0) /* 10b */ /* MCUSYS_IDLE_STA (0x1C001000+0x21C) */ #define MCUSYS_DDREN_LSB BIT(0) /* 8b */ #define ARMBUS_IDLE_TO_26M_LSB BIT(8) /* 1b */ #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB BIT(9) /* 1b */ #define MP0_CPU_IDLE_TO_PWR_OFF_LSB BIT(16) /* 8b */ /* CPU_PWR_STATUS (0x1C001000+0x220) */ #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(0) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(1) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(2) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(3) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(4) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(5) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(6) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(7) /* 1b */ #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(8) /* 1b */ #define MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(9) /* 1b */ /* SW2SPM_WAKEUP (0x1C001000+0x224) */ #define SW2SPM_WAKEUP_LSB BIT(0) /* 4b */ /* SW2SPM_WAKEUP_SET (0x1C001000+0x228) */ #define SW2SPM_WAKEUP_SET_LSB BIT(0) /* 4b */ /* SW2SPM_WAKEUP_CLR (0x1C001000+0x22C) */ #define SW2SPM_WAKEUP_CLR_LSB BIT(0) /* 4b */ /* SW2SPM_MAILBOX_0 (0x1C001000+0x230) */ #define SW2SPM_MAILBOX_0_LSB BIT(0) /* 32b */ /* SW2SPM_MAILBOX_1 (0x1C001000+0x234) */ #define SW2SPM_MAILBOX_1_LSB BIT(0) /* 32b */ /* SW2SPM_MAILBOX_2 (0x1C001000+0x238) */ #define SW2SPM_MAILBOX_2_LSB BIT(0) /* 32b */ /* SW2SPM_MAILBOX_3 (0x1C001000+0x23C) */ #define SW2SPM_MAILBOX_3_LSB BIT(0) /* 32b */ /* SPM2SW_MAILBOX_0 (0x1C001000+0x240) */ #define SPM2SW_MAILBOX_0_LSB BIT(0) /* 32b */ /* SPM2SW_MAILBOX_1 (0x1C001000+0x244) */ #define SPM2SW_MAILBOX_1_LSB BIT(0) /* 32b */ /* SPM2SW_MAILBOX_2 (0x1C001000+0x248) */ #define SPM2SW_MAILBOX_2_LSB BIT(0) /* 32b */ /* SPM2SW_MAILBOX_3 (0x1C001000+0x24C) */ #define SPM2SW_MAILBOX_3_LSB BIT(0) /* 32b */ /* SPM2MCUPM_CON (0x1C001000+0x250) */ #define SPM2MCUPM_SW_RST_B_LSB BIT(0) /* 1b */ #define SPM2MCUPM_SW_INT_LSB BIT(1) /* 1b */ #define MCUPM_WFI_LSB BIT(16) /* 1b */ /* SPM_MCUSYS_PWR_CON (0x1C001000+0x260) */ #define MCUSYS_SPMC_PWR_ON_LSB BIT(2) /* 1b */ #define MCUSYS_SPMC_RESET_PWRON_CONFIG_LSB BIT(5) /* 1b */ #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(31) /* 1b */ /* SPM_CPUTOP_PWR_CON (0x1C001000+0x264) */ #define MP0_SPMC_PWR_ON_CPUTOP_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPUTOP_LSB BIT(5) /* 1b */ #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(31) /* 1b */ /* SPM_CPU0_PWR_CON (0x1C001000+0x268) */ #define MP0_SPMC_PWR_ON_CPU0_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU0_LSB BIT(5) /* 1b */ #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(31) /* 1b */ /* SPM_CPU1_PWR_CON (0x1C001000+0x26C) */ #define MP0_SPMC_PWR_ON_CPU1_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU1_LSB BIT(5) /* 1b */ #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(31) /* 1b */ /* SPM_CPU2_PWR_CON (0x1C001000+0x270) */ #define MP0_SPMC_PWR_ON_CPU2_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU2_LSB BIT(5) /* 1b */ #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(31) /* 1b */ /* SPM_CPU3_PWR_CON (0x1C001000+0x274) */ #define MP0_SPMC_PWR_ON_CPU3_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU3_LSB BIT(5) /* 1b */ #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(31) /* 1b */ /* SPM_CPU4_PWR_CON (0x1C001000+0x278) */ #define MP0_SPMC_PWR_ON_CPU4_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU4_LSB BIT(5) /* 1b */ #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(31) /* 1b */ /* SPM_CPU5_PWR_CON (0x1C001000+0x27C) */ #define MP0_SPMC_PWR_ON_CPU5_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU5_LSB BIT(5) /* 1b */ #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(31) /* 1b */ /* SPM_CPU6_PWR_CON (0x1C001000+0x280) */ #define MP0_SPMC_PWR_ON_CPU6_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU6_LSB BIT(5) /* 1b */ #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(31) /* 1b */ /* SPM_CPU7_PWR_CON (0x1C001000+0x284) */ #define MP0_SPMC_PWR_ON_CPU7_LSB BIT(2) /* 1b */ #define MP0_SPMC_RESET_PWRON_CONFIG_CPU7_LSB BIT(5) /* 1b */ #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(31) /* 1b */ /* SPM_MCUPM_SPMC_CON (0x1C001000+0x288) */ #define CPUEB_STATE_VALID_LSB BIT(0) /* 1b */ #define REQ_PWR_ON_LSB BIT(1) /* 1b */ #define REQ_MEM_RET_LSB BIT(2) /* 1b */ #define RESET_PWR_ON_LSB BIT(4) /* 1b */ #define RESET_MEM_RET_LSB BIT(5) /* 1b */ #define CPUEB_STATE_FINISH_ACK_LSB BIT(31) /* 1b */ /* SPM_DPM_P2P_STA (0x1C001000+0x2A0) */ #define P2P_TX_STA_LSB BIT(0) /* 32b */ /* SPM_DPM_P2P_CON (0x1C001000+0x2A4) */ #define REG_P2P_TX_ERROR_FLAG_EN_LSB BIT(0) /* 1b */ /* SPM_DPM_INTF_STA (0x1C001000+0x2A8) */ #define SC_HW_S1_REQ_LSB BIT(0) /* 1b */ #define REG_HW_S1_ACK_MASK_LSB BIT(4) /* 4b */ #define SC_HW_S1_ACK_LSB BIT(8) /* 4b */ /* SPM_DPM_WB_CON (0x1C001000+0x2AC) */ #define REG_DPM_WB_EN_LSB BIT(0) /* 1b */ /* SPM_ACK_CHK_TIMER_3 (0x1C001000+0x2B0) */ #define SPM_ACK_CHK_TIMER_VAL_3_LSB BIT(0) /* 16b */ #define SPM_ACK_CHK_TIMER_3_LSB BIT(16) /* 16b */ /* SPM_ACK_CHK_STA_3 (0x1C001000+0x2B4) */ #define SPM_ACK_CHK_STA_3_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CON (0x1C001000+0x300) */ #define SPM_PWRAP_CON_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CON_STA (0x1C001000+0x304) */ #define SPM_PWRAP_CON_STA_LSB BIT(0) /* 32b */ /* SPM_PMIC_SPMI_CON (0x1C001000+0x308) */ #define SPM_PMIC_SPMI_CMD_LSB BIT(0) /* 2b */ #define SPM_PMIC_SPMI_SLAVEID_LSB BIT(2) /* 4b */ #define SPM_PMIC_SPMI_PMIFID_LSB BIT(6) /* 1b */ #define SPM_PMIC_SPMI_DBCNT_LSB BIT(7) /* 1b */ /* SPM_PWRAP_CMD0 (0x1C001000+0x310) */ #define SPM_PWRAP_CMD0_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD1 (0x1C001000+0x314) */ #define SPM_PWRAP_CMD1_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD2 (0x1C001000+0x318) */ #define SPM_PWRAP_CMD2_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD3 (0x1C001000+0x31C) */ #define SPM_PWRAP_CMD3_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD4 (0x1C001000+0x320) */ #define SPM_PWRAP_CMD4_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD5 (0x1C001000+0x324) */ #define SPM_PWRAP_CMD5_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD6 (0x1C001000+0x328) */ #define SPM_PWRAP_CMD6_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD7 (0x1C001000+0x32C) */ #define SPM_PWRAP_CMD7_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD8 (0x1C001000+0x330) */ #define SPM_PWRAP_CMD8_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD9 (0x1C001000+0x334) */ #define SPM_PWRAP_CMD9_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD10 (0x1C001000+0x338) */ #define SPM_PWRAP_CMD10_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD11 (0x1C001000+0x33C) */ #define SPM_PWRAP_CMD11_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD12 (0x1C001000+0x340) */ #define SPM_PWRAP_CMD12_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD13 (0x1C001000+0x344) */ #define SPM_PWRAP_CMD13_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD14 (0x1C001000+0x348) */ #define SPM_PWRAP_CMD14_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD15 (0x1C001000+0x34C) */ #define SPM_PWRAP_CMD15_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD16 (0x1C001000+0x350) */ #define SPM_PWRAP_CMD16_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD17 (0x1C001000+0x354) */ #define SPM_PWRAP_CMD17_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD18 (0x1C001000+0x358) */ #define SPM_PWRAP_CMD18_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD19 (0x1C001000+0x35C) */ #define SPM_PWRAP_CMD19_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD20 (0x1C001000+0x360) */ #define SPM_PWRAP_CMD20_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD21 (0x1C001000+0x364) */ #define SPM_PWRAP_CMD21_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD22 (0x1C001000+0x368) */ #define SPM_PWRAP_CMD22_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD23 (0x1C001000+0x36C) */ #define SPM_PWRAP_CMD23_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD24 (0x1C001000+0x370) */ #define SPM_PWRAP_CMD24_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD25 (0x1C001000+0x374) */ #define SPM_PWRAP_CMD25_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD26 (0x1C001000+0x378) */ #define SPM_PWRAP_CMD26_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD27 (0x1C001000+0x37C) */ #define SPM_PWRAP_CMD27_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD28 (0x1C001000+0x380) */ #define SPM_PWRAP_CMD28_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD29 (0x1C001000+0x384) */ #define SPM_PWRAP_CMD29_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD30 (0x1C001000+0x388) */ #define SPM_PWRAP_CMD30_LSB BIT(0) /* 32b */ /* SPM_PWRAP_CMD31 (0x1C001000+0x38C) */ #define SPM_PWRAP_CMD31_LSB BIT(0) /* 32b */ /* DVFSRC_EVENT_STA (0x1C001000+0x390) */ #define DVFSRC_EVENT_LSB BIT(0) /* 32b */ /* SPM_FORCE_DVFS (0x1C001000+0x394) */ #define FORCE_DVFS_LEVEL_LSB BIT(0) /* 32b */ /* SPM_DVFS_STA (0x1C001000+0x398) */ #define TARGET_DVFS_LEVEL_LSB BIT(0) /* 32b */ /* SPM_DVS_DFS_LEVEL (0x1C001000+0x39C) */ #define SPM_DFS_LEVEL_LSB BIT(0) /* 16b */ #define SPM_DVS_LEVEL_LSB BIT(16) /* 16b */ /* SPM_DVFS_LEVEL (0x1C001000+0x3A0) */ #define SPM_DVFS_LEVEL_LSB BIT(0) /* 32b */ /* SPM_DVFS_OPP (0x1C001000+0x3A4) */ #define SPM_DVFS_OPP_LSB BIT(0) /* 5b */ /* SPM_ULTRA_REQ (0x1C001000+0x3A8) */ #define SPM2MM_FORCE_ULTRA_LSB BIT(0) /* 1b */ #define SPM2MM_DBL_OSTD_ACT_LSB BIT(1) /* 1b */ #define SPM2MM_ULTRAREQ_LSB BIT(2) /* 1b */ #define SPM2MD_ULTRAREQ_LSB BIT(3) /* 1b */ #define SPM2ISP_ULTRAREQ_LSB BIT(4) /* 1b */ #define SPM2ISP_ULTRAACK_D2T_LSB BIT(18) /* 1b */ #define SPM2MM_ULTRAACK_D2T_LSB BIT(19) /* 1b */ #define SPM2MD_ULTRAACK_D2T_LSB BIT(20) /* 1b */ /* SPM_DVFS_CON (0x1C001000+0x3AC) */ #define SPM_DVFS_FORCE_ENABLE_LSB BIT(2) /* 1b */ #define FORCE_DVFS_WAKE_LSB BIT(3) /* 1b */ #define SPM_DVFSRC_ENABLE_LSB BIT(4) /* 1b */ #define DVFSRC_WAKEUP_EVENT_MASK_LSB BIT(6) /* 1b */ #define SPM2RC_EVENT_ABORT_LSB BIT(7) /* 1b */ #define DVFSRC_LEVEL_ACK_LSB BIT(8) /* 1b */ /* SPM_SRAMRC_CON (0x1C001000+0x3B0) */ #define VSRAM_GEAR_REQ_LSB BIT(0) /* 1b */ #define VSRAM_GEAR_RDY_LSB BIT(4) /* 1b */ #define VSRAM_VAL_LEVEL_LSB BIT(16) /* 8b */ /* SPM_SRCLKENRC_CON (0x1C001000+0x3B4) */ #define SPM_PMIF_VALID_LSB BIT(0) /* 1b */ #define SPM_PMIF_ACK_LSB BIT(4) /* 1b */ /* SPM_DPSW_CON (0x1C001000+0x3B8) */ #define DPSW_VLOGIC_REQ_LSB BIT(0) /* 1b */ #define DPSW_VLOGIC_ISO_LSB BIT(4) /* 1b */ #define DPSW_VLOGIC_ACK_LSB BIT(8) /* 1b */ #define DPSW_VSRAM_ACK_LSB BIT(12) /* 1b */ /* ULPOSC_CON (0x1C001000+0x400) */ #define ULPOSC_EN_LSB BIT(0) /* 1b */ #define ULPOSC_RST_LSB BIT(1) /* 1b */ #define ULPOSC_CG_EN_LSB BIT(2) /* 1b */ #define ULPOSC_CLK_SEL_LSB BIT(3) /* 1b */ /* AP_MDSRC_REQ (0x1C001000+0x404) */ #define AP_MDSMSRC_REQ_LSB BIT(0) /* 1b */ #define AP_L1SMSRC_REQ_LSB BIT(1) /* 1b */ #define AP2MD_PEER_WAKEUP_LSB BIT(3) /* 1b */ #define AP_MDSMSRC_ACK_LSB BIT(4) /* 1b */ #define AP_L1SMSRC_ACK_LSB BIT(5) /* 1b */ /* SPM2MD_SWITCH_CTRL (0x1C001000+0x408) */ #define SPM2MD_SWITCH_CTRL_LSB BIT(0) /* 10b */ /* RC_SPM_CTRL (0x1C001000+0x40C) */ #define SPM_AP_26M_RDY_LSB BIT(0) /* 1b */ #define SPM2RC_DMY_CTRL_LSB BIT(2) /* 6b */ #define RC2SPM_SRCCLKENO_0_ACK_LSB BIT(16) /* 1b */ /* SPM2GPUPM_CON (0x1C001000+0x410) */ #define SPM2GPUEB_SW_RST_B_LSB BIT(0) /* 1b */ #define SPM2GPUEB_SW_INT_LSB BIT(1) /* 1b */ #define SC_MFG_PLL_EN_LSB BIT(4) /* 1b */ #define GPUEB_WFI_LSB BIT(16) /* 1b */ /* SPM2APU_CON (0x1C001000+0x414) */ #define RPC_SRAM_CTRL_MUX_SEL_LSB BIT(0) /* 1b */ #define APU_VCORE_OFF_ISO_EN_LSB BIT(1) /* 1b */ #define APU_ARE_REQ_LSB BIT(4) /* 1b */ #define APU_ARE_ACK_LSB BIT(8) /* 1b */ #define APU_ACTIVE_STATE_LSB BIT(9) /* 1b */ #define APU_AOV_WAKEUP_LSB BIT(16) /* 1b */ /* SPM2EFUSE_CON (0x1C001000+0x418) */ #define AOC_EFUSE_EN_LSB BIT(0) /* 1b */ #define AOC_EFUSE_RESTORE_RDY_LSB BIT(1) /* 1b */ /* SPM2DFD_CON (0x1C001000+0x41C) */ #define DFD_SOC_MTCMOS_ACK_LSB BIT(0) /* 1b */ #define DFD_SOC_MTCMOS_REQ_LSB BIT(1) /* 1b */ /* RSV_PLL_CON (0x1C001000+0x420) */ #define SC_UNIVPLL_EN_LSB BIT(0) /* 1b */ #define SC_MMPLL_EN_LSB BIT(1) /* 1b */ #define SC_RSV_PLL_EN_LSB BIT(2) /* 14b */ #define APU_26M_CLK_EN_LSB BIT(16) /* 1b */ #define IFR_26M_CLK_EN_LSB BIT(17) /* 1b */ #define VLP_26M2ULPOSC_EN_LSB BIT(18) /* 1b */ #define SC_RSV_CLK_EN_LSB BIT(20) /* 12b */ /* EMI_SLB_CON (0x1C001000+0x424) */ #define EMI_SLB_MODE_MASK_LSB BIT(0) /* 1b */ #define SPM2EMI_SLP_PROT_EN_LSB BIT(1) /* 1b */ #define SPM2EMI_SLP_PROT_SRC_LSB BIT(2) /* 1b */ #define EMI_DRAMC_MD32_SLEEP_IDLE_LSB BIT(4) /* 2b */ #define EMI_SLB_ONLY_MODE_LSB BIT(8) /* 2b */ /* SPM_SUSPEND_FLAG_CON (0x1C001000+0x428) */ #define SPM_SUSPEND_RESUME_FLAG_LSB BIT(0) /* 1b */ /* SPM2PMSR_CON (0x1C001000+0x42C) */ #define SPM2PMSR_DRAMC_S0_FLAG_LSB BIT(0) /* 1b */ #define SPM2PMSR_SYSTEM_POWER_STATE_LSB BIT(4) /* 8b */ /* SPM_TOPCK_RTFF_CON (0x1C001000+0x430) */ #define SPM_CKSYS_RTFF_DIVIDER_RST_LSB BIT(0) /* 1b */ #define SPM_32K_VCORE_CLK_EN_LSB BIT(1) /* 1b */ #define SPM_ULPOSC_VCORE_CLK_EN_LSB BIT(2) /* 1b */ /* EMI_SHF_CON (0x1C001000+0x434) */ #define SPM2EMI_SHF_REQ_LSB BIT(0) /* 2b */ #define SPM2EMI_SHF_REQ_ACK_LSB BIT(4) /* 2b */ /* CIRQ_BYPASS_CON (0x1C001000+0x438) */ #define SPM_CIRQ_BYPASS_MODE_EN_LSB BIT(0) /* 1b */ /* AOC_VCORE_SRAM_CON (0x1C001000+0x43C) */ #define AOC_VCORE_SRAM_PDN_EN_LSB BIT(0) /* 1b */ #define AOC_VCORE_SRAM_PDN_SHIFT_LSB BIT(1) /* 1b */ /* REG_MODULE_SW_CG_DDREN_REQ_MASK_0 (0x1C001000+0x460) */ #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_DDREN_REQ_MASK_1 (0x1C001000+0x464) */ #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_DDREN_REQ_MASK_2 (0x1C001000+0x468) */ #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_DDREN_REQ_MASK_3 (0x1C001000+0x46C) */ #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VRF18_REQ_MASK_0 (0x1C001000+0x470) */ #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VRF18_REQ_MASK_1 (0x1C001000+0x474) */ #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VRF18_REQ_MASK_2 (0x1C001000+0x478) */ #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VRF18_REQ_MASK_3 (0x1C001000+0x47C) */ #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_INFRA_REQ_MASK_0 (0x1C001000+0x480) */ #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_INFRA_REQ_MASK_1 (0x1C001000+0x484) */ #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_INFRA_REQ_MASK_2 (0x1C001000+0x488) */ #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_INFRA_REQ_MASK_3 (0x1C001000+0x48C) */ #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_F26M_REQ_MASK_0 (0x1C001000+0x490) */ #define REG_MODULE_SW_CG_F26M_REQ_MASK_0_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_F26M_REQ_MASK_1 (0x1C001000+0x494) */ #define REG_MODULE_SW_CG_F26M_REQ_MASK_1_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_F26M_REQ_MASK_2 (0x1C001000+0x498) */ #define REG_MODULE_SW_CG_F26M_REQ_MASK_2_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_F26M_REQ_MASK_3 (0x1C001000+0x49C) */ #define REG_MODULE_SW_CG_F26M_REQ_MASK_3_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VCORE_REQ_MASK_0 (0x1C001000+0x4A0) */ #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VCORE_REQ_MASK_1 (0x1C001000+0x4A4) */ #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VCORE_REQ_MASK_2 (0x1C001000+0x4A8) */ #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2_LSB BIT(0) /* 32b */ /* REG_MODULE_SW_CG_VCORE_REQ_MASK_3 (0x1C001000+0x4AC) */ #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_DDREN_REQ_MASK (0x1C001000+0x4B0) */ #define REG_PWR_STATUS_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_VRF18_REQ_MASK (0x1C001000+0x4B4) */ #define REG_PWR_STATUS_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_INFRA_REQ_MASK (0x1C001000+0x4B8) */ #define REG_PWR_STATUS_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_F26M_REQ_MASK (0x1C001000+0x4BC) */ #define REG_PWR_STATUS_F26M_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_PMIC_REQ_MASK (0x1C001000+0x4C0) */ #define REG_PWR_STATUS_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_VCORE_REQ_MASK (0x1C001000+0x4C4) */ #define REG_PWR_STATUS_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_DDREN_REQ_MASK (0x1C001000+0x4C8) */ #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_VRF18_REQ_MASK (0x1C001000+0x4CC) */ #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_INFRA_REQ_MASK (0x1C001000+0x4D0) */ #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_F26M_REQ_MASK (0x1C001000+0x4D4) */ #define REG_PWR_STATUS_MSB_F26M_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_PMIC_REQ_MASK (0x1C001000+0x4D8) */ #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_PWR_STATUS_MSB_VCORE_REQ_MASK (0x1C001000+0x4DC) */ #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_DDREN_REQ_MASK (0x1C001000+0x4E0) */ #define REG_MODULE_BUSY_DDREN_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_VRF18_REQ_MASK (0x1C001000+0x4E4) */ #define REG_MODULE_BUSY_VRF18_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_INFRA_REQ_MASK (0x1C001000+0x4E8) */ #define REG_MODULE_BUSY_INFRA_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_F26M_REQ_MASK (0x1C001000+0x4EC) */ #define REG_MODULE_BUSY_F26M_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_PMIC_REQ_MASK (0x1C001000+0x4F0) */ #define REG_MODULE_BUSY_PMIC_REQ_MASK_LSB BIT(0) /* 32b */ /* REG_MODULE_BUSY_VCORE_REQ_MASK (0x1C001000+0x4F4) */ #define REG_MODULE_BUSY_VCORE_REQ_MASK_LSB BIT(0) /* 32b */ /* SYS_TIMER_CON (0x1C001000+0x500) */ #define SYS_TIMER_START_EN_LSB BIT(0) /* 1b */ #define SYS_TIMER_LATCH_EN_LSB BIT(1) /* 1b */ #define SYS_TIMER_ID_LSB BIT(8) /* 8b */ #define SYS_TIMER_VALID_LSB BIT(31) /* 1b */ /* SYS_TIMER_VALUE_L (0x1C001000+0x504) */ #define SYS_TIMER_VALUE_L_LSB BIT(0) /* 32b */ /* SYS_TIMER_VALUE_H (0x1C001000+0x508) */ #define SYS_TIMER_VALUE_H_LSB BIT(0) /* 32b */ /* SYS_TIMER_START_L (0x1C001000+0x50C) */ #define SYS_TIMER_START_L_LSB BIT(0) /* 32b */ /* SYS_TIMER_START_H (0x1C001000+0x510) */ #define SYS_TIMER_START_H_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_00 (0x1C001000+0x514) */ #define SYS_TIMER_LATCH_L_00_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_00 (0x1C001000+0x518) */ #define SYS_TIMER_LATCH_H_00_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_01 (0x1C001000+0x51C) */ #define SYS_TIMER_LATCH_L_01_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_01 (0x1C001000+0x520) */ #define SYS_TIMER_LATCH_H_01_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_02 (0x1C001000+0x524) */ #define SYS_TIMER_LATCH_L_02_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_02 (0x1C001000+0x528) */ #define SYS_TIMER_LATCH_H_02_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_03 (0x1C001000+0x52C) */ #define SYS_TIMER_LATCH_L_03_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_03 (0x1C001000+0x530) */ #define SYS_TIMER_LATCH_H_03_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_04 (0x1C001000+0x534) */ #define SYS_TIMER_LATCH_L_04_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_04 (0x1C001000+0x538) */ #define SYS_TIMER_LATCH_H_04_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_05 (0x1C001000+0x53C) */ #define SYS_TIMER_LATCH_L_05_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_05 (0x1C001000+0x540) */ #define SYS_TIMER_LATCH_H_05_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_06 (0x1C001000+0x544) */ #define SYS_TIMER_LATCH_L_06_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_06 (0x1C001000+0x548) */ #define SYS_TIMER_LATCH_H_06_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_07 (0x1C001000+0x54C) */ #define SYS_TIMER_LATCH_L_07_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_07 (0x1C001000+0x550) */ #define SYS_TIMER_LATCH_H_07_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_08 (0x1C001000+0x554) */ #define SYS_TIMER_LATCH_L_08_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_08 (0x1C001000+0x558) */ #define SYS_TIMER_LATCH_H_08_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_09 (0x1C001000+0x55C) */ #define SYS_TIMER_LATCH_L_09_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_09 (0x1C001000+0x560) */ #define SYS_TIMER_LATCH_H_09_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_10 (0x1C001000+0x564) */ #define SYS_TIMER_LATCH_L_10_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_10 (0x1C001000+0x568) */ #define SYS_TIMER_LATCH_H_10_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_11 (0x1C001000+0x56C) */ #define SYS_TIMER_LATCH_L_11_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_11 (0x1C001000+0x570) */ #define SYS_TIMER_LATCH_H_11_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_12 (0x1C001000+0x574) */ #define SYS_TIMER_LATCH_L_12_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_12 (0x1C001000+0x578) */ #define SYS_TIMER_LATCH_H_12_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_13 (0x1C001000+0x57C) */ #define SYS_TIMER_LATCH_L_13_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_13 (0x1C001000+0x580) */ #define SYS_TIMER_LATCH_H_13_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_14 (0x1C001000+0x584) */ #define SYS_TIMER_LATCH_L_14_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_14 (0x1C001000+0x588) */ #define SYS_TIMER_LATCH_H_14_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_L_15 (0x1C001000+0x58C) */ #define SYS_TIMER_LATCH_L_15_LSB BIT(0) /* 32b */ /* SYS_TIMER_LATCH_H_15 (0x1C001000+0x590) */ #define SYS_TIMER_LATCH_H_15_LSB BIT(0) /* 32b */ /* PCM_TIMER_VAL (0x1C001000+0x594) */ #define REG_PCM_TIMER_VAL_LSB BIT(0) /* 32b */ /* PCM_TIMER_OUT (0x1C001000+0x598) */ #define PCM_TIMER_LSB BIT(0) /* 32b */ /* SPM_COUNTER_0 (0x1C001000+0x59C) */ #define SPM_COUNTER_VAL_0_LSB BIT(0) /* 14b */ #define SPM_COUNTER_OUT_0_LSB BIT(14) /* 14b */ #define SPM_COUNTER_EN_0_LSB BIT(28) /* 1b */ #define SPM_COUNTER_CLR_0_LSB BIT(29) /* 1b */ #define SPM_COUNTER_TIMEOUT_0_LSB BIT(30) /* 1b */ #define SPM_COUNTER_WAKEUP_EN_0_LSB BIT(31) /* 1b */ /* SPM_COUNTER_1 (0x1C001000+0x5A0) */ #define SPM_COUNTER_VAL_1_LSB BIT(0) /* 14b */ #define SPM_COUNTER_OUT_1_LSB BIT(14) /* 14b */ #define SPM_COUNTER_EN_1_LSB BIT(28) /* 1b */ #define SPM_COUNTER_CLR_1_LSB BIT(29) /* 1b */ #define SPM_COUNTER_TIMEOUT_1_LSB BIT(30) /* 1b */ #define SPM_COUNTER_WAKEUP_EN_1_LSB BIT(31) /* 1b */ /* SPM_COUNTER_2 (0x1C001000+0x5A4) */ #define SPM_COUNTER_VAL_2_LSB BIT(0) /* 14b */ #define SPM_COUNTER_OUT_2_LSB BIT(14) /* 14b */ #define SPM_COUNTER_EN_2_LSB BIT(28) /* 1b */ #define SPM_COUNTER_CLR_2_LSB BIT(29) /* 1b */ #define SPM_COUNTER_TIMEOUT_2_LSB BIT(30) /* 1b */ #define SPM_COUNTER_WAKEUP_EN_2_LSB BIT(31) /* 1b */ /* PCM_WDT_VAL (0x1C001000+0x5A8) */ #define REG_PCM_WDT_VAL_LSB BIT(0) /* 32b */ /* PCM_WDT_OUT (0x1C001000+0x5AC) */ #define PCM_WDT_TIMER_VAL_OUT_LSB BIT(0) /* 32b */ /* SPM_SW_FLAG_0 (0x1C001000+0x600) */ #define SPM_SW_FLAG_LSB BIT(0) /* 32b */ /* SPM_SW_DEBUG_0 (0x1C001000+0x604) */ #define SPM_SW_DEBUG_0_LSB BIT(0) /* 32b */ /* SPM_SW_FLAG_1 (0x1C001000+0x608) */ #define SPM_SW_FLAG_1_LSB BIT(0) /* 32b */ /* SPM_SW_DEBUG_1 (0x1C001000+0x60C) */ #define SPM_SW_DEBUG_1_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_0 (0x1C001000+0x610) */ #define SPM_SW_RSV_0_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_1 (0x1C001000+0x614) */ #define SPM_SW_RSV_1_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_2 (0x1C001000+0x618) */ #define SPM_SW_RSV_2_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_3 (0x1C001000+0x61C) */ #define SPM_SW_RSV_3_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_4 (0x1C001000+0x620) */ #define SPM_SW_RSV_4_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_5 (0x1C001000+0x624) */ #define SPM_SW_RSV_5_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_6 (0x1C001000+0x628) */ #define SPM_SW_RSV_6_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_7 (0x1C001000+0x62C) */ #define SPM_SW_RSV_7_LSB BIT(0) /* 32b */ /* SPM_SW_RSV_8 (0x1C001000+0x630) */ #define SPM_SW_RSV_8_LSB BIT(0) /* 32b */ /* SPM_BK_WAKE_EVENT (0x1C001000+0x634) */ #define SPM_BK_WAKE_EVENT_LSB BIT(0) /* 32b */ /* SPM_BK_VTCXO_DUR (0x1C001000+0x638) */ #define SPM_BK_VTCXO_DUR_LSB BIT(0) /* 32b */ /* SPM_BK_WAKE_MISC (0x1C001000+0x63C) */ #define SPM_BK_WAKE_MISC_LSB BIT(0) /* 32b */ /* SPM_BK_PCM_TIMER (0x1C001000+0x640) */ #define SPM_BK_PCM_TIMER_LSB BIT(0) /* 32b */ /* SPM_RSV_CON_0 (0x1C001000+0x650) */ #define SPM_RSV_CON_0_LSB BIT(0) /* 32b */ /* SPM_RSV_CON_1 (0x1C001000+0x654) */ #define SPM_RSV_CON_1_LSB BIT(0) /* 32b */ /* SPM_RSV_STA_0 (0x1C001000+0x658) */ #define SPM_RSV_STA_0_LSB BIT(0) /* 32b */ /* SPM_RSV_STA_1 (0x1C001000+0x65C) */ #define SPM_RSV_STA_1_LSB BIT(0) /* 32b */ /* SPM_SPARE_CON (0x1C001000+0x660) */ #define SPM_SPARE_CON_LSB BIT(0) /* 32b */ /* SPM_SPARE_CON_SET (0x1C001000+0x664) */ #define SPM_SPARE_CON_SET_LSB BIT(0) /* 32b */ /* SPM_SPARE_CON_CLR (0x1C001000+0x668) */ #define SPM_SPARE_CON_CLR_LSB BIT(0) /* 32b */ /* SPM_CROSS_WAKE_M00_REQ (0x1C001000+0x66C) */ #define SPM_M0_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ #define SPM_CROSS_WAKE_M0_CHK_LSB BIT(4) /* 4b */ /* SPM_CROSS_WAKE_M01_REQ (0x1C001000+0x670) */ #define SPM_M1_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ #define SPM_CROSS_WAKE_M1_CHK_LSB BIT(4) /* 4b */ /* SPM_CROSS_WAKE_M02_REQ (0x1C001000+0x674) */ #define SPM_M2_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ #define SPM_CROSS_WAKE_M2_CHK_LSB BIT(4) /* 4b */ /* SPM_CROSS_WAKE_M03_REQ (0x1C001000+0x678) */ #define SPM_M3_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */ #define SPM_CROSS_WAKE_M3_CHK_LSB BIT(4) /* 4b */ /* SCP_VCORE_LEVEL (0x1C001000+0x67C) */ #define SCP_VCORE_LEVEL_LSB BIT(0) /* 16b */ /* SPM_DDREN_ACK_SEL_CON (0x1C001000+0x680) */ #define SPM_DDREN_ACK_SEL_OTHERS_LSB BIT(0) /* 1b */ #define SPM_DDREN_ACK_SEL_MCU_LSB BIT(1) /* 1b */ /* SPM_SW_FLAG_2 (0x1C001000+0x684) */ #define SPM_SW_FLAG_2_LSB BIT(0) /* 32b */ /* SPM_SW_DEBUG_2 (0x1C001000+0x688) */ #define SPM_SW_DEBUG_2_LSB BIT(0) /* 32b */ /* SPM_DV_CON_0 (0x1C001000+0x68C) */ #define SPM_DV_CON_0_LSB BIT(0) /* 32b */ /* SPM_DV_CON_1 (0x1C001000+0x690) */ #define SPM_DV_CON_1_LSB BIT(0) /* 32b */ /* SPM_SEMA_M0 (0x1C001000+0x69C) */ #define SPM_SEMA_M0_LSB BIT(0) /* 8b */ /* SPM_SEMA_M1 (0x1C001000+0x6A0) */ #define SPM_SEMA_M1_LSB BIT(0) /* 8b */ /* SPM_SEMA_M2 (0x1C001000+0x6A4) */ #define SPM_SEMA_M2_LSB BIT(0) /* 8b */ /* SPM_SEMA_M3 (0x1C001000+0x6A8) */ #define SPM_SEMA_M3_LSB BIT(0) /* 8b */ /* SPM_SEMA_M4 (0x1C001000+0x6AC) */ #define SPM_SEMA_M4_LSB BIT(0) /* 8b */ /* SPM_SEMA_M5 (0x1C001000+0x6B0) */ #define SPM_SEMA_M5_LSB BIT(0) /* 8b */ /* SPM_SEMA_M6 (0x1C001000+0x6B4) */ #define SPM_SEMA_M6_LSB BIT(0) /* 8b */ /* SPM_SEMA_M7 (0x1C001000+0x6B8) */ #define SPM_SEMA_M7_LSB BIT(0) /* 8b */ /* SPM2ADSP_MAILBOX (0x1C001000+0x6BC) */ #define SPM2ADSP_MAILBOX_LSB BIT(0) /* 32b */ /* ADSP2SPM_MAILBOX (0x1C001000+0x6C0) */ #define ADSP2SPM_MAILBOX_LSB BIT(0) /* 32b */ /* VCORE_RTFF_CTRL_MASK_SET (0x1C001000+0x6C4) */ #define VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ /* VCORE_RTFF_CTRL_MASK_CLR (0x1C001000+0x6C8) */ #define VCORE_RTFF_CTRL_MASK_CLR_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ /* SPM2PMCU_MAILBOX_0 (0x1C001000+0x6CC) */ #define SPM2PMCU_MAILBOX_0_LSB BIT(0) /* 32b */ /* SPM2PMCU_MAILBOX_1 (0x1C001000+0x6D0) */ #define SPM2PMCU_MAILBOX_1_LSB BIT(0) /* 32b */ /* SPM2PMCU_MAILBOX_2 (0x1C001000+0x6D4) */ #define SPM2PMCU_MAILBOX_2_LSB BIT(0) /* 32b */ /* SPM2PMCU_MAILBOX_3 (0x1C001000+0x6D8) */ #define SPM2PMCU_MAILBOX_3_LSB BIT(0) /* 32b */ /* PMCU2SPM_MAILBOX_0 (0x1C001000+0x6DC) */ #define PMCU2SPM_MAILBOX_0_LSB BIT(0) /* 32b */ /* PMCU2SPM_MAILBOX_1 (0x1C001000+0x6E0) */ #define PMCU2SPM_MAILBOX_1_LSB BIT(0) /* 32b */ /* PMCU2SPM_MAILBOX_2 (0x1C001000+0x6E4) */ #define PMCU2SPM_MAILBOX_2_LSB BIT(0) /* 32b */ /* PMCU2SPM_MAILBOX_3 (0x1C001000+0x6E8) */ #define PMCU2SPM_MAILBOX_3_LSB BIT(0) /* 32b */ /* SPM2SCP_MAILBOX (0x1C001000+0x6EC) */ #define SPM_SCP_MAILBOX_LSB BIT(0) /* 32b */ /* SCP2SPM_MAILBOX (0x1C001000+0x6F0) */ #define SCP_SPM_MAILBOX_LSB BIT(0) /* 32b */ /* SCP_AOV_BUS_CON (0x1C001000+0x6F4) */ #define SCP_AOV_BUS_REQ_LSB BIT(0) /* 1b */ #define SCP_AOV_BUS_ACK_LSB BIT(8) /* 1b */ /* VCORE_RTFF_CTRL_MASK (0x1C001000+0x6F8) */ #define VCORE_RTFF_CTRL_MASK_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */ /* SPM_SRAM_SRCLKENO_MASK (0x1C001000+0x6FC) */ #define SPM_SRAM_SRCLKENO_MASK_LSB BIT(0) /* 1b */ /* EMI_PDN_REQ (0x1C001000+0x700) */ #define EMI_PDN_REQ_LSB BIT(0) /* 32b */ /* EMI_BUSY_REQ (0x1C001000+0x704) */ #define EMI_BUSY_REQ_LSB BIT(0) /* 32b */ /* EMI_RESERVED_STA (0x1C001000+0x708) */ #define EMI_RESERVED_STA_LSB BIT(0) /* 32b */ /* SC_UNIVPLL_DIV_RST_B (0x1C001000+0x70C) */ #define SC_UNIVPLL_DIV_RST_B_LSB BIT(0) /* 32b */ /* ECO_ARMPLL_DIV_CLOCK_OFF (0x1C001000+0x710) */ #define ECO_ARMPLL_DIV_CLOCK_OFF_LSB BIT(0) /* 32b */ /* SPM_MCDSR_CG_CHECK_X1 (0x1C001000+0x714) */ #define SPM_MCDSR_CG_CHECK_X1_LSB BIT(0) /* 32b */ /* SPM_SODI2_CG_CHECK_X1 (0x1C001000+0x718) */ #define SPM_SODI2_CG_CHECK_X1_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_STA (0x1C001000+0x800) */ #define SPM_WAKEUP_EVENT_L_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_EXT_STA (0x1C001000+0x804) */ #define EXT_WAKEUP_EVENT_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_EVENT_MASK (0x1C001000+0x808) */ #define REG_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_EVENT_EXT_MASK (0x1C001000+0x80C) */ #define REG_EXT_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_EVENT_SENS (0x1C001000+0x810) */ #define REG_WAKEUP_EVENT_SENS_LSB BIT(0) /* 32b */ /* SPM_WAKEUP_EVENT_CLEAR (0x1C001000+0x814) */ #define REG_WAKEUP_EVENT_CLR_LSB BIT(0) /* 32b */ /* SPM_SRC_REQ (0x1C001000+0x818) */ #define REG_SPM_ADSP_MAILBOX_REQ_LSB BIT(0) /* 1b */ #define REG_SPM_APSRC_REQ_LSB BIT(1) /* 1b */ #define REG_SPM_DDREN_REQ_LSB BIT(2) /* 1b */ #define REG_SPM_DVFS_REQ_LSB BIT(3) /* 1b */ #define REG_SPM_EMI_REQ_LSB BIT(4) /* 1b */ #define REG_SPM_F26M_REQ_LSB BIT(5) /* 1b */ #define REG_SPM_INFRA_REQ_LSB BIT(6) /* 1b */ #define REG_SPM_PMIC_REQ_LSB BIT(7) /* 1b */ #define REG_SPM_SCP_MAILBOX_REQ_LSB BIT(8) /* 1b */ #define REG_SPM_SSPM_MAILBOX_REQ_LSB BIT(9) /* 1b */ #define REG_SPM_SW_MAILBOX_REQ_LSB BIT(10) /* 1b */ #define REG_SPM_VCORE_REQ_LSB BIT(11) /* 1b */ #define REG_SPM_VRF18_REQ_LSB BIT(12) /* 1b */ #define ADSP_MAILBOX_STATE_LSB BIT(16) /* 1b */ #define APSRC_STATE_LSB BIT(17) /* 1b */ #define DDREN_STATE_LSB BIT(18) /* 1b */ #define DVFS_STATE_LSB BIT(19) /* 1b */ #define EMI_STATE_LSB BIT(20) /* 1b */ #define F26M_STATE_LSB BIT(21) /* 1b */ #define INFRA_STATE_LSB BIT(22) /* 1b */ #define PMIC_STATE_LSB BIT(23) /* 1b */ #define SCP_MAILBOX_STATE_LSB BIT(24) /* 1b */ #define SSPM_MAILBOX_STATE_LSB BIT(25) /* 1b */ #define SW_MAILBOX_STATE_LSB BIT(26) /* 1b */ #define VCORE_STATE_LSB BIT(27) /* 1b */ #define VRF18_STATE_LSB BIT(28) /* 1b */ /* SPM_SRC_MASK_0 (0x1C001000+0x81C) */ #define REG_APU_APSRC_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_APU_DDREN_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_APU_EMI_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_APU_INFRA_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_APU_PMIC_REQ_MASK_B_LSB BIT(4) /* 1b */ #define REG_APU_SRCCLKENA_MASK_B_LSB BIT(5) /* 1b */ #define REG_APU_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */ #define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */ #define REG_AUDIO_DSP_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_AUDIO_DSP_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */ #define REG_AUDIO_DSP_VCORE_REQ_MASK_B_LSB BIT(13) /* 1b */ #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_CAM_APSRC_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_CAM_DDREN_REQ_MASK_B_LSB BIT(16) /* 1b */ #define REG_CAM_EMI_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_CAM_INFRA_REQ_MASK_B_LSB BIT(18) /* 1b */ #define REG_CAM_PMIC_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_CAM_SRCCLKENA_MASK_B_LSB BIT(20) /* 1b */ #define REG_CAM_VRF18_REQ_MASK_B_LSB BIT(21) /* 1b */ /* SPM_SRC_MASK_1 (0x1C001000+0x820) */ #define REG_CCIF_APSRC_REQ_MASK_B_LSB BIT(0) /* 12b */ #define REG_CCIF_EMI_REQ_MASK_B_LSB BIT(12) /* 12b */ /* SPM_SRC_MASK_2 (0x1C001000+0x824) */ #define REG_CCIF_INFRA_REQ_MASK_B_LSB BIT(0) /* 12b */ #define REG_CCIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 12b */ /* SPM_SRC_MASK_3 (0x1C001000+0x828) */ #define REG_CCIF_SRCCLKENA_MASK_B_LSB BIT(0) /* 12b */ #define REG_CCIF_VRF18_REQ_MASK_B_LSB BIT(12) /* 12b */ #define REG_CCU_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_CCU_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_CCU_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_CCU_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_CCU_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */ #define REG_CCU_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */ #define REG_CCU_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */ #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_4 (0x1C001000+0x82C) */ #define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_CG_CHECK_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_CG_CHECK_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_CG_CHECK_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */ #define REG_CG_CHECK_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */ #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ #define REG_CONN_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */ #define REG_CONN_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */ #define REG_CONN_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_CONN_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_CONN_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_CONN_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */ #define REG_CONN_SRCCLKENB_MASK_B_LSB BIT(13) /* 1b */ #define REG_CONN_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_CONN_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_CPUEB_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ #define REG_CPUEB_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_CPUEB_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ #define REG_CPUEB_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_CPUEB_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */ #define REG_CPUEB_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ #define REG_CPUEB_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ #define REG_DISP0_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ #define REG_DISP0_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_DISP0_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_DISP0_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_DISP0_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_DISP0_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */ #define REG_DISP0_VRF18_REQ_MASK_B_LSB BIT(29) /* 1b */ #define REG_DISP1_APSRC_REQ_MASK_B_LSB BIT(30) /* 1b */ #define REG_DISP1_DDREN_REQ_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_5 (0x1C001000+0x830) */ #define REG_DISP1_EMI_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_DISP1_INFRA_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_DISP1_PMIC_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_DISP1_SRCCLKENA_MASK_B_LSB BIT(3) /* 1b */ #define REG_DISP1_VRF18_REQ_MASK_B_LSB BIT(4) /* 1b */ #define REG_DPM_APSRC_REQ_MASK_B_LSB BIT(5) /* 4b */ #define REG_DPM_DDREN_REQ_MASK_B_LSB BIT(9) /* 4b */ #define REG_DPM_EMI_REQ_MASK_B_LSB BIT(13) /* 4b */ #define REG_DPM_INFRA_REQ_MASK_B_LSB BIT(17) /* 4b */ #define REG_DPM_PMIC_REQ_MASK_B_LSB BIT(21) /* 4b */ #define REG_DPM_SRCCLKENA_MASK_B_LSB BIT(25) /* 4b */ /* SPM_SRC_MASK_6 (0x1C001000+0x834) */ #define REG_DPM_VCORE_REQ_MASK_B_LSB BIT(0) /* 4b */ #define REG_DPM_VRF18_REQ_MASK_B_LSB BIT(4) /* 4b */ #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */ #define REG_DPMAIF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_DPMAIF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_DPMAIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */ #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */ #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_DVFSRC_LEVEL_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_EMISYS_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ #define REG_EMISYS_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_EMISYS_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ #define REG_GCE_D_APSRC_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_GCE_D_DDREN_REQ_MASK_B_LSB BIT(20) /* 1b */ #define REG_GCE_D_EMI_REQ_MASK_B_LSB BIT(21) /* 1b */ #define REG_GCE_D_INFRA_REQ_MASK_B_LSB BIT(22) /* 1b */ #define REG_GCE_D_PMIC_REQ_MASK_B_LSB BIT(23) /* 1b */ #define REG_GCE_D_SRCCLKENA_MASK_B_LSB BIT(24) /* 1b */ #define REG_GCE_D_VRF18_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_GCE_M_APSRC_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_GCE_M_DDREN_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_GCE_M_EMI_REQ_MASK_B_LSB BIT(28) /* 1b */ #define REG_GCE_M_INFRA_REQ_MASK_B_LSB BIT(29) /* 1b */ #define REG_GCE_M_PMIC_REQ_MASK_B_LSB BIT(30) /* 1b */ #define REG_GCE_M_SRCCLKENA_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_7 (0x1C001000+0x838) */ #define REG_GCE_M_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_GPUEB_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_GPUEB_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_GPUEB_EMI_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_GPUEB_INFRA_REQ_MASK_B_LSB BIT(4) /* 1b */ #define REG_GPUEB_PMIC_REQ_MASK_B_LSB BIT(5) /* 1b */ #define REG_GPUEB_SRCCLKENA_MASK_B_LSB BIT(6) /* 1b */ #define REG_GPUEB_VRF18_REQ_MASK_B_LSB BIT(7) /* 1b */ #define REG_HWCCF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */ #define REG_HWCCF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_HWCCF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_HWCCF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_HWCCF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */ #define REG_HWCCF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */ #define REG_HWCCF_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_HWCCF_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_IMG_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */ #define REG_IMG_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_IMG_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */ #define REG_IMG_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_IMG_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */ #define REG_IMG_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ #define REG_IMG_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ #define REG_INFRASYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_INFRASYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_IPIC_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_IPIC_VRF18_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_MCU_APSRC_REQ_MASK_B_LSB BIT(28) /* 1b */ #define REG_MCU_DDREN_REQ_MASK_B_LSB BIT(29) /* 1b */ #define REG_MCU_EMI_REQ_MASK_B_LSB BIT(30) /* 1b */ /* SPM_SRC_MASK_8 (0x1C001000+0x83C) */ #define REG_MCUSYS_APSRC_REQ_MASK_B_LSB BIT(0) /* 8b */ #define REG_MCUSYS_DDREN_REQ_MASK_B_LSB BIT(8) /* 8b */ #define REG_MCUSYS_EMI_REQ_MASK_B_LSB BIT(16) /* 8b */ #define REG_MCUSYS_INFRA_REQ_MASK_B_LSB BIT(24) /* 8b */ /* SPM_SRC_MASK_9 (0x1C001000+0x840) */ #define REG_MCUSYS_PMIC_REQ_MASK_B_LSB BIT(0) /* 8b */ #define REG_MCUSYS_SRCCLKENA_MASK_B_LSB BIT(8) /* 8b */ #define REG_MCUSYS_VRF18_REQ_MASK_B_LSB BIT(16) /* 8b */ #define REG_MD_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_MD_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_MD_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_MD_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_MD_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */ #define REG_MD_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */ #define REG_MD_SRCCLKENA1_MASK_B_LSB BIT(30) /* 1b */ #define REG_MD_VCORE_REQ_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_10 (0x1C001000+0x844) */ #define REG_MD_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_MDP_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_MDP_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_MM_PROC_APSRC_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_MM_PROC_DDREN_REQ_MASK_B_LSB BIT(4) /* 1b */ #define REG_MM_PROC_EMI_REQ_MASK_B_LSB BIT(5) /* 1b */ #define REG_MM_PROC_INFRA_REQ_MASK_B_LSB BIT(6) /* 1b */ #define REG_MM_PROC_PMIC_REQ_MASK_B_LSB BIT(7) /* 1b */ #define REG_MM_PROC_SRCCLKENA_MASK_B_LSB BIT(8) /* 1b */ #define REG_MM_PROC_VRF18_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_MMSYS_APSRC_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_MMSYS_DDREN_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_MMSYS_VRF18_REQ_MASK_B_LSB BIT(12) /* 1b */ #define REG_PCIE0_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */ #define REG_PCIE0_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_PCIE0_INFRA_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_PCIE0_SRCCLKENA_MASK_B_LSB BIT(16) /* 1b */ #define REG_PCIE0_VRF18_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_PCIE1_APSRC_REQ_MASK_B_LSB BIT(18) /* 1b */ #define REG_PCIE1_DDREN_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_PCIE1_INFRA_REQ_MASK_B_LSB BIT(20) /* 1b */ #define REG_PCIE1_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */ #define REG_PCIE1_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */ #define REG_PERISYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */ #define REG_PERISYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_PERISYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */ #define REG_PERISYS_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_PERISYS_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_PERISYS_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */ #define REG_PERISYS_VCORE_REQ_MASK_B_LSB BIT(29) /* 1b */ #define REG_PERISYS_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */ #define REG_SCP_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_11 (0x1C001000+0x848) */ #define REG_SCP_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */ #define REG_SCP_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_SCP_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_SCP_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_SCP_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */ #define REG_SCP_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */ #define REG_SCP_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */ #define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB BIT(7) /* 2b */ #define REG_SRCCLKENI_PMIC_REQ_MASK_B_LSB BIT(9) /* 2b */ #define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB BIT(11) /* 2b */ #define REG_SSPM_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */ #define REG_SSPM_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */ #define REG_SSPM_EMI_REQ_MASK_B_LSB BIT(15) /* 1b */ #define REG_SSPM_INFRA_REQ_MASK_B_LSB BIT(16) /* 1b */ #define REG_SSPM_PMIC_REQ_MASK_B_LSB BIT(17) /* 1b */ #define REG_SSPM_SRCCLKENA_MASK_B_LSB BIT(18) /* 1b */ #define REG_SSPM_VRF18_REQ_MASK_B_LSB BIT(19) /* 1b */ #define REG_SSR_APSRC_REQ_MASK_B_LSB BIT(20) /* 1b */ #define REG_SSR_DDREN_REQ_MASK_B_LSB BIT(21) /* 1b */ #define REG_SSR_EMI_REQ_MASK_B_LSB BIT(22) /* 1b */ #define REG_SSR_INFRA_REQ_MASK_B_LSB BIT(23) /* 1b */ #define REG_SSR_PMIC_REQ_MASK_B_LSB BIT(24) /* 1b */ #define REG_SSR_SRCCLKENA_MASK_B_LSB BIT(25) /* 1b */ #define REG_SSR_VRF18_REQ_MASK_B_LSB BIT(26) /* 1b */ #define REG_UFS_APSRC_REQ_MASK_B_LSB BIT(27) /* 1b */ #define REG_UFS_DDREN_REQ_MASK_B_LSB BIT(28) /* 1b */ #define REG_UFS_EMI_REQ_MASK_B_LSB BIT(29) /* 1b */ #define REG_UFS_INFRA_REQ_MASK_B_LSB BIT(30) /* 1b */ #define REG_UFS_PMIC_REQ_MASK_B_LSB BIT(31) /* 1b */ /* SPM_SRC_MASK_12 (0x1C001000+0x84C) */ #define REG_UFS_SRCCLKENA_MASK_B_LSB BIT(0) /* 1b */ #define REG_UFS_VRF18_REQ_MASK_B_LSB BIT(1) /* 1b */ #define REG_VDEC_APSRC_REQ_MASK_B_LSB BIT(2) /* 1b */ #define REG_VDEC_DDREN_REQ_MASK_B_LSB BIT(3) /* 1b */ #define REG_VDEC_EMI_REQ_MASK_B_LSB BIT(4) /* 1b */ #define REG_VDEC_INFRA_REQ_MASK_B_LSB BIT(5) /* 1b */ #define REG_VDEC_PMIC_REQ_MASK_B_LSB BIT(6) /* 1b */ #define REG_VDEC_SRCCLKENA_MASK_B_LSB BIT(7) /* 1b */ #define REG_VDEC_VRF18_REQ_MASK_B_LSB BIT(8) /* 1b */ #define REG_VENC_APSRC_REQ_MASK_B_LSB BIT(9) /* 1b */ #define REG_VENC_DDREN_REQ_MASK_B_LSB BIT(10) /* 1b */ #define REG_VENC_EMI_REQ_MASK_B_LSB BIT(11) /* 1b */ #define REG_VENC_INFRA_REQ_MASK_B_LSB BIT(12) /* 1b */ #define REG_VENC_PMIC_REQ_MASK_B_LSB BIT(13) /* 1b */ #define REG_VENC_SRCCLKENA_MASK_B_LSB BIT(14) /* 1b */ #define REG_VENC_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */ /* SPM_REQ_STA_0 (0x1C001000+0x850) */ #define APU_APSRC_REQ_LSB BIT(0) /* 1b */ #define APU_DDREN_REQ_LSB BIT(1) /* 1b */ #define APU_EMI_REQ_LSB BIT(2) /* 1b */ #define APU_INFRA_REQ_LSB BIT(3) /* 1b */ #define APU_PMIC_REQ_LSB BIT(4) /* 1b */ #define APU_SRCCLKENA_LSB BIT(5) /* 1b */ #define APU_VRF18_REQ_LSB BIT(6) /* 1b */ #define AUDIO_DSP_APSRC_REQ_LSB BIT(7) /* 1b */ #define AUDIO_DSP_DDREN_REQ_LSB BIT(8) /* 1b */ #define AUDIO_DSP_EMI_REQ_LSB BIT(9) /* 1b */ #define AUDIO_DSP_INFRA_REQ_LSB BIT(10) /* 1b */ #define AUDIO_DSP_PMIC_REQ_LSB BIT(11) /* 1b */ #define AUDIO_DSP_SRCCLKENA_LSB BIT(12) /* 1b */ #define AUDIO_DSP_VCORE_REQ_LSB BIT(13) /* 1b */ #define AUDIO_DSP_VRF18_REQ_LSB BIT(14) /* 1b */ #define CAM_APSRC_REQ_LSB BIT(15) /* 1b */ #define CAM_DDREN_REQ_LSB BIT(16) /* 1b */ #define CAM_EMI_REQ_LSB BIT(17) /* 1b */ #define CAM_INFRA_REQ_LSB BIT(18) /* 1b */ #define CAM_PMIC_REQ_LSB BIT(19) /* 1b */ #define CAM_SRCCLKENA_LSB BIT(20) /* 1b */ #define CAM_VRF18_REQ_LSB BIT(21) /* 1b */ /* SPM_REQ_STA_1 (0x1C001000+0x854) */ #define CCIF_APSRC_REQ_LSB BIT(0) /* 12b */ #define CCIF_EMI_REQ_LSB BIT(12) /* 12b */ /* SPM_REQ_STA_2 (0x1C001000+0x858) */ #define CCIF_INFRA_REQ_LSB BIT(0) /* 12b */ #define CCIF_PMIC_REQ_LSB BIT(12) /* 12b */ /* SPM_REQ_STA_3 (0x1C001000+0x85C) */ #define CCIF_SRCCLKENA_LSB BIT(0) /* 12b */ #define CCIF_VRF18_REQ_LSB BIT(12) /* 12b */ #define CCU_APSRC_REQ_LSB BIT(24) /* 1b */ #define CCU_DDREN_REQ_LSB BIT(25) /* 1b */ #define CCU_EMI_REQ_LSB BIT(26) /* 1b */ #define CCU_INFRA_REQ_LSB BIT(27) /* 1b */ #define CCU_PMIC_REQ_LSB BIT(28) /* 1b */ #define CCU_SRCCLKENA_LSB BIT(29) /* 1b */ #define CCU_VRF18_REQ_LSB BIT(30) /* 1b */ #define CG_CHECK_APSRC_REQ_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_4 (0x1C001000+0x860) */ #define CG_CHECK_DDREN_REQ_LSB BIT(0) /* 1b */ #define CG_CHECK_EMI_REQ_LSB BIT(1) /* 1b */ #define CG_CHECK_INFRA_REQ_LSB BIT(2) /* 1b */ #define CG_CHECK_PMIC_REQ_LSB BIT(3) /* 1b */ #define CG_CHECK_SRCCLKENA_LSB BIT(4) /* 1b */ #define CG_CHECK_VCORE_REQ_LSB BIT(5) /* 1b */ #define CG_CHECK_VRF18_REQ_LSB BIT(6) /* 1b */ #define CONN_APSRC_REQ_LSB BIT(7) /* 1b */ #define CONN_DDREN_REQ_LSB BIT(8) /* 1b */ #define CONN_EMI_REQ_LSB BIT(9) /* 1b */ #define CONN_INFRA_REQ_LSB BIT(10) /* 1b */ #define CONN_PMIC_REQ_LSB BIT(11) /* 1b */ #define CONN_SRCCLKENA_LSB BIT(12) /* 1b */ #define CONN_SRCCLKENB_LSB BIT(13) /* 1b */ #define CONN_VCORE_REQ_LSB BIT(14) /* 1b */ #define CONN_VRF18_REQ_LSB BIT(15) /* 1b */ #define CPUEB_APSRC_REQ_LSB BIT(16) /* 1b */ #define CPUEB_DDREN_REQ_LSB BIT(17) /* 1b */ #define CPUEB_EMI_REQ_LSB BIT(18) /* 1b */ #define CPUEB_INFRA_REQ_LSB BIT(19) /* 1b */ #define CPUEB_PMIC_REQ_LSB BIT(20) /* 1b */ #define CPUEB_SRCCLKENA_LSB BIT(21) /* 1b */ #define CPUEB_VRF18_REQ_LSB BIT(22) /* 1b */ #define DISP0_APSRC_REQ_LSB BIT(23) /* 1b */ #define DISP0_DDREN_REQ_LSB BIT(24) /* 1b */ #define DISP0_EMI_REQ_LSB BIT(25) /* 1b */ #define DISP0_INFRA_REQ_LSB BIT(26) /* 1b */ #define DISP0_PMIC_REQ_LSB BIT(27) /* 1b */ #define DISP0_SRCCLKENA_LSB BIT(28) /* 1b */ #define DISP0_VRF18_REQ_LSB BIT(29) /* 1b */ #define DISP1_APSRC_REQ_LSB BIT(30) /* 1b */ #define DISP1_DDREN_REQ_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_5 (0x1C001000+0x864) */ #define DISP1_EMI_REQ_LSB BIT(0) /* 1b */ #define DISP1_INFRA_REQ_LSB BIT(1) /* 1b */ #define DISP1_PMIC_REQ_LSB BIT(2) /* 1b */ #define DISP1_SRCCLKENA_LSB BIT(3) /* 1b */ #define DISP1_VRF18_REQ_LSB BIT(4) /* 1b */ #define DPM_APSRC_REQ_LSB BIT(5) /* 4b */ #define DPM_DDREN_REQ_LSB BIT(9) /* 4b */ #define DPM_EMI_REQ_LSB BIT(13) /* 4b */ #define DPM_INFRA_REQ_LSB BIT(17) /* 4b */ #define DPM_PMIC_REQ_LSB BIT(21) /* 4b */ #define DPM_SRCCLKENA_LSB BIT(25) /* 4b */ /* SPM_REQ_STA_6 (0x1C001000+0x868) */ #define DPM_VCORE_REQ_LSB BIT(0) /* 4b */ #define DPM_VRF18_REQ_LSB BIT(4) /* 4b */ #define DPMAIF_APSRC_REQ_LSB BIT(8) /* 1b */ #define DPMAIF_DDREN_REQ_LSB BIT(9) /* 1b */ #define DPMAIF_EMI_REQ_LSB BIT(10) /* 1b */ #define DPMAIF_INFRA_REQ_LSB BIT(11) /* 1b */ #define DPMAIF_PMIC_REQ_LSB BIT(12) /* 1b */ #define DPMAIF_SRCCLKENA_LSB BIT(13) /* 1b */ #define DPMAIF_VRF18_REQ_LSB BIT(14) /* 1b */ #define DVFSRC_LEVEL_REQ_LSB BIT(15) /* 1b */ #define EMISYS_APSRC_REQ_LSB BIT(16) /* 1b */ #define EMISYS_DDREN_REQ_LSB BIT(17) /* 1b */ #define EMISYS_EMI_REQ_LSB BIT(18) /* 1b */ #define GCE_D_APSRC_REQ_LSB BIT(19) /* 1b */ #define GCE_D_DDREN_REQ_LSB BIT(20) /* 1b */ #define GCE_D_EMI_REQ_LSB BIT(21) /* 1b */ #define GCE_D_INFRA_REQ_LSB BIT(22) /* 1b */ #define GCE_D_PMIC_REQ_LSB BIT(23) /* 1b */ #define GCE_D_SRCCLKENA_LSB BIT(24) /* 1b */ #define GCE_D_VRF18_REQ_LSB BIT(25) /* 1b */ #define GCE_M_APSRC_REQ_LSB BIT(26) /* 1b */ #define GCE_M_DDREN_REQ_LSB BIT(27) /* 1b */ #define GCE_M_EMI_REQ_LSB BIT(28) /* 1b */ #define GCE_M_INFRA_REQ_LSB BIT(29) /* 1b */ #define GCE_M_PMIC_REQ_LSB BIT(30) /* 1b */ #define GCE_M_SRCCLKENA_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_7 (0x1C001000+0x86C) */ #define GCE_M_VRF18_REQ_LSB BIT(0) /* 1b */ #define GPUEB_APSRC_REQ_LSB BIT(1) /* 1b */ #define GPUEB_DDREN_REQ_LSB BIT(2) /* 1b */ #define GPUEB_EMI_REQ_LSB BIT(3) /* 1b */ #define GPUEB_INFRA_REQ_LSB BIT(4) /* 1b */ #define GPUEB_PMIC_REQ_LSB BIT(5) /* 1b */ #define GPUEB_SRCCLKENA_LSB BIT(6) /* 1b */ #define GPUEB_VRF18_REQ_LSB BIT(7) /* 1b */ #define HWCCF_APSRC_REQ_LSB BIT(8) /* 1b */ #define HWCCF_DDREN_REQ_LSB BIT(9) /* 1b */ #define HWCCF_EMI_REQ_LSB BIT(10) /* 1b */ #define HWCCF_INFRA_REQ_LSB BIT(11) /* 1b */ #define HWCCF_PMIC_REQ_LSB BIT(12) /* 1b */ #define HWCCF_SRCCLKENA_LSB BIT(13) /* 1b */ #define HWCCF_VCORE_REQ_LSB BIT(14) /* 1b */ #define HWCCF_VRF18_REQ_LSB BIT(15) /* 1b */ #define IMG_APSRC_REQ_LSB BIT(16) /* 1b */ #define IMG_DDREN_REQ_LSB BIT(17) /* 1b */ #define IMG_EMI_REQ_LSB BIT(18) /* 1b */ #define IMG_INFRA_REQ_LSB BIT(19) /* 1b */ #define IMG_PMIC_REQ_LSB BIT(20) /* 1b */ #define IMG_SRCCLKENA_LSB BIT(21) /* 1b */ #define IMG_VRF18_REQ_LSB BIT(22) /* 1b */ #define INFRASYS_APSRC_REQ_LSB BIT(23) /* 1b */ #define INFRASYS_DDREN_REQ_LSB BIT(24) /* 1b */ #define INFRASYS_EMI_REQ_LSB BIT(25) /* 1b */ #define IPIC_INFRA_REQ_LSB BIT(26) /* 1b */ #define IPIC_VRF18_REQ_LSB BIT(27) /* 1b */ #define MCU_APSRC_REQ_LSB BIT(28) /* 1b */ #define MCU_DDREN_REQ_LSB BIT(29) /* 1b */ #define MCU_EMI_REQ_LSB BIT(30) /* 1b */ /* SPM_REQ_STA_8 (0x1C001000+0x870) */ #define MCUSYS_APSRC_REQ_LSB BIT(0) /* 8b */ #define MCUSYS_DDREN_REQ_LSB BIT(8) /* 8b */ #define MCUSYS_EMI_REQ_LSB BIT(16) /* 8b */ #define MCUSYS_INFRA_REQ_LSB BIT(24) /* 8b */ /* SPM_REQ_STA_9 (0x1C001000+0x874) */ #define MCUSYS_PMIC_REQ_LSB BIT(0) /* 8b */ #define MCUSYS_SRCCLKENA_LSB BIT(8) /* 8b */ #define MCUSYS_VRF18_REQ_LSB BIT(16) /* 8b */ #define MD_APSRC_REQ_LSB BIT(24) /* 1b */ #define MD_DDREN_REQ_LSB BIT(25) /* 1b */ #define MD_EMI_REQ_LSB BIT(26) /* 1b */ #define MD_INFRA_REQ_LSB BIT(27) /* 1b */ #define MD_PMIC_REQ_LSB BIT(28) /* 1b */ #define MD_SRCCLKENA_LSB BIT(29) /* 1b */ #define MD_SRCCLKENA1_LSB BIT(30) /* 1b */ #define MD_VCORE_REQ_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_10 (0x1C001000+0x878) */ #define MD_VRF18_REQ_LSB BIT(0) /* 1b */ #define MDP_APSRC_REQ_LSB BIT(1) /* 1b */ #define MDP_DDREN_REQ_LSB BIT(2) /* 1b */ #define MM_PROC_APSRC_REQ_LSB BIT(3) /* 1b */ #define MM_PROC_DDREN_REQ_LSB BIT(4) /* 1b */ #define MM_PROC_EMI_REQ_LSB BIT(5) /* 1b */ #define MM_PROC_INFRA_REQ_LSB BIT(6) /* 1b */ #define MM_PROC_PMIC_REQ_LSB BIT(7) /* 1b */ #define MM_PROC_SRCCLKENA_LSB BIT(8) /* 1b */ #define MM_PROC_VRF18_REQ_LSB BIT(9) /* 1b */ #define MMSYS_APSRC_REQ_LSB BIT(10) /* 1b */ #define MMSYS_DDREN_REQ_LSB BIT(11) /* 1b */ #define MMSYS_VRF18_REQ_LSB BIT(12) /* 1b */ #define PCIE0_APSRC_REQ_LSB BIT(13) /* 1b */ #define PCIE0_DDREN_REQ_LSB BIT(14) /* 1b */ #define PCIE0_INFRA_REQ_LSB BIT(15) /* 1b */ #define PCIE0_SRCCLKENA_LSB BIT(16) /* 1b */ #define PCIE0_VRF18_REQ_LSB BIT(17) /* 1b */ #define PCIE1_APSRC_REQ_LSB BIT(18) /* 1b */ #define PCIE1_DDREN_REQ_LSB BIT(19) /* 1b */ #define PCIE1_INFRA_REQ_LSB BIT(20) /* 1b */ #define PCIE1_SRCCLKENA_LSB BIT(21) /* 1b */ #define PCIE1_VRF18_REQ_LSB BIT(22) /* 1b */ #define PERISYS_APSRC_REQ_LSB BIT(23) /* 1b */ #define PERISYS_DDREN_REQ_LSB BIT(24) /* 1b */ #define PERISYS_EMI_REQ_LSB BIT(25) /* 1b */ #define PERISYS_INFRA_REQ_LSB BIT(26) /* 1b */ #define PERISYS_PMIC_REQ_LSB BIT(27) /* 1b */ #define PERISYS_SRCCLKENA_LSB BIT(28) /* 1b */ #define PERISYS_VCORE_REQ_LSB BIT(29) /* 1b */ #define PERISYS_VRF18_REQ_LSB BIT(30) /* 1b */ #define SCP_APSRC_REQ_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_11 (0x1C001000+0x87C) */ #define SCP_DDREN_REQ_LSB BIT(0) /* 1b */ #define SCP_EMI_REQ_LSB BIT(1) /* 1b */ #define SCP_INFRA_REQ_LSB BIT(2) /* 1b */ #define SCP_PMIC_REQ_LSB BIT(3) /* 1b */ #define SCP_SRCCLKENA_LSB BIT(4) /* 1b */ #define SCP_VCORE_REQ_LSB BIT(5) /* 1b */ #define SCP_VRF18_REQ_LSB BIT(6) /* 1b */ #define SRCCLKENI_INFRA_REQ_LSB BIT(7) /* 2b */ #define SRCCLKENI_PMIC_REQ_LSB BIT(9) /* 2b */ #define SRCCLKENI_SRCCLKENA_LSB BIT(11) /* 2b */ #define SSPM_APSRC_REQ_LSB BIT(13) /* 1b */ #define SSPM_DDREN_REQ_LSB BIT(14) /* 1b */ #define SSPM_EMI_REQ_LSB BIT(15) /* 1b */ #define SSPM_INFRA_REQ_LSB BIT(16) /* 1b */ #define SSPM_PMIC_REQ_LSB BIT(17) /* 1b */ #define SSPM_SRCCLKENA_LSB BIT(18) /* 1b */ #define SSPM_VRF18_REQ_LSB BIT(19) /* 1b */ #define SSR_APSRC_REQ_LSB BIT(20) /* 1b */ #define SSR_DDREN_REQ_LSB BIT(21) /* 1b */ #define SSR_EMI_REQ_LSB BIT(22) /* 1b */ #define SSR_INFRA_REQ_LSB BIT(23) /* 1b */ #define SSR_PMIC_REQ_LSB BIT(24) /* 1b */ #define SSR_SRCCLKENA_LSB BIT(25) /* 1b */ #define SSR_VRF18_REQ_LSB BIT(26) /* 1b */ #define UFS_APSRC_REQ_LSB BIT(27) /* 1b */ #define UFS_DDREN_REQ_LSB BIT(28) /* 1b */ #define UFS_EMI_REQ_LSB BIT(29) /* 1b */ #define UFS_INFRA_REQ_LSB BIT(30) /* 1b */ #define UFS_PMIC_REQ_LSB BIT(31) /* 1b */ /* SPM_REQ_STA_12 (0x1C001000+0x880) */ #define UFS_SRCCLKENA_LSB BIT(0) /* 1b */ #define UFS_VRF18_REQ_LSB BIT(1) /* 1b */ #define VDEC_APSRC_REQ_LSB BIT(2) /* 1b */ #define VDEC_DDREN_REQ_LSB BIT(3) /* 1b */ #define VDEC_EMI_REQ_LSB BIT(4) /* 1b */ #define VDEC_INFRA_REQ_LSB BIT(5) /* 1b */ #define VDEC_PMIC_REQ_LSB BIT(6) /* 1b */ #define VDEC_SRCCLKENA_LSB BIT(7) /* 1b */ #define VDEC_VRF18_REQ_LSB BIT(8) /* 1b */ #define VENC_APSRC_REQ_LSB BIT(9) /* 1b */ #define VENC_DDREN_REQ_LSB BIT(10) /* 1b */ #define VENC_EMI_REQ_LSB BIT(11) /* 1b */ #define VENC_INFRA_REQ_LSB BIT(12) /* 1b */ #define VENC_PMIC_REQ_LSB BIT(13) /* 1b */ #define VENC_SRCCLKENA_LSB BIT(14) /* 1b */ #define VENC_VRF18_REQ_LSB BIT(15) /* 1b */ /* SPM_IPC_WAKEUP_REQ (0x1C001000+0x884) */ #define SPM2SSPM_WAKEUP_LSB BIT(0) /* 1b */ #define SPM2SCP_WAKEUP_LSB BIT(1) /* 1b */ #define SPM2ADSP_WAKEUP_LSB BIT(2) /* 1b */ /* IPC_WAKEUP_REQ_MASK_STA (0x1C001000+0x888) */ #define REG_SW2SPM_WAKEUP_MASK_B_LSB BIT(0) /* 4b */ #define REG_SSPM2SPM_WAKEUP_MASK_B_LSB BIT(4) /* 1b */ #define REG_SCP2SPM_WAKEUP_MASK_B_LSB BIT(5) /* 1b */ #define REG_ADSP2SPM_WAKEUP_MASK_B_LSB BIT(6) /* 1b */ #define SSPM2SPM_WAKEUP_LSB BIT(20) /* 1b */ #define SCP2SPM_WAKEUP_LSB BIT(21) /* 1b */ #define ADSP2SPM_WAKEUP_LSB BIT(22) /* 1b */ /* SPM_EVENT_CON_MISC (0x1C001000+0x88C) */ #define REG_SRCCLKEN_FAST_RESP_LSB BIT(0) /* 1b */ #define REG_CSYSPWRUP_ACK_MASK_LSB BIT(1) /* 1b */ /* DDREN_DBC_CON (0x1C001000+0x890) */ #define REG_DDREN_DBC_LEN_LSB BIT(0) /* 10b */ #define REG_DDREN_DBC_EN_LSB BIT(16) /* 1b */ /* SPM_RESOURCE_ACK_CON_0 (0x1C001000+0x894) */ #define SPM_VCORE_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */ #define SPM_PMIC_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */ #define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */ #define SPM_INFRA_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */ /* SPM_RESOURCE_ACK_CON_1 (0x1C001000+0x898) */ #define SPM_VRF18_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */ #define SPM_EMI_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */ #define SPM_APSRC_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */ #define SPM_DDREN_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */ /* SPM_RESOURCE_ACK_MASK_0 (0x1C001000+0x89C) */ #define REG_APU_APSRC_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_APU_DDREN_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_APU_EMI_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_APU_INFRA_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_APU_PMIC_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_APU_SRCCLKENA_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_APU_VRF18_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_AUDIO_DSP_EMI_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_AUDIO_DSP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_AUDIO_DSP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_CAM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_CAM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_CAM_EMI_ACK_MASK_LSB BIT(17) /* 1b */ #define REG_CAM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */ #define REG_CAM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */ #define REG_CAM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */ #define REG_CAM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */ #define REG_CCU_APSRC_ACK_MASK_LSB BIT(22) /* 1b */ #define REG_CCU_DDREN_ACK_MASK_LSB BIT(23) /* 1b */ #define REG_CCU_EMI_ACK_MASK_LSB BIT(24) /* 1b */ #define REG_CCU_INFRA_ACK_MASK_LSB BIT(25) /* 1b */ #define REG_CCU_PMIC_ACK_MASK_LSB BIT(26) /* 1b */ #define REG_CCU_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */ #define REG_CCU_VRF18_ACK_MASK_LSB BIT(28) /* 1b */ #define REG_CONN_APSRC_ACK_MASK_LSB BIT(29) /* 1b */ #define REG_CONN_DDREN_ACK_MASK_LSB BIT(30) /* 1b */ #define REG_CONN_EMI_ACK_MASK_LSB BIT(31) /* 1b */ /* SPM_RESOURCE_ACK_MASK_1 (0x1C001000+0x8A0) */ #define REG_CONN_INFRA_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_CONN_PMIC_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_CONN_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_CONN_VCORE_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_CONN_VRF18_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_CPUEB_APSRC_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_CPUEB_DDREN_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_CPUEB_EMI_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_CPUEB_INFRA_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_CPUEB_PMIC_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_CPUEB_SRCCLKENA_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_CPUEB_VRF18_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_DISP0_APSRC_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_DISP0_DDREN_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_DISP0_EMI_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_DISP0_INFRA_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_DISP0_PMIC_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_DISP0_SRCCLKENA_ACK_MASK_LSB BIT(17) /* 1b */ #define REG_DISP0_VRF18_ACK_MASK_LSB BIT(18) /* 1b */ #define REG_DISP1_APSRC_ACK_MASK_LSB BIT(19) /* 1b */ #define REG_DISP1_DDREN_ACK_MASK_LSB BIT(20) /* 1b */ #define REG_DISP1_EMI_ACK_MASK_LSB BIT(21) /* 1b */ #define REG_DISP1_INFRA_ACK_MASK_LSB BIT(22) /* 1b */ #define REG_DISP1_PMIC_ACK_MASK_LSB BIT(23) /* 1b */ #define REG_DISP1_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */ #define REG_DISP1_VRF18_ACK_MASK_LSB BIT(25) /* 1b */ #define REG_DPM_APSRC_ACK_MASK_LSB BIT(26) /* 4b */ /* SPM_RESOURCE_ACK_MASK_2 (0x1C001000+0x8A4) */ #define REG_DPM_DDREN_ACK_MASK_LSB BIT(0) /* 4b */ #define REG_DPM_EMI_ACK_MASK_LSB BIT(4) /* 4b */ #define REG_DPM_INFRA_ACK_MASK_LSB BIT(8) /* 4b */ #define REG_DPM_PMIC_ACK_MASK_LSB BIT(12) /* 4b */ #define REG_DPM_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 4b */ #define REG_DPM_VCORE_ACK_MASK_LSB BIT(20) /* 4b */ #define REG_DPM_VRF18_ACK_MASK_LSB BIT(24) /* 4b */ #define REG_EMISYS_APSRC_ACK_MASK_LSB BIT(28) /* 1b */ #define REG_EMISYS_DDREN_ACK_MASK_LSB BIT(29) /* 1b */ #define REG_EMISYS_EMI_ACK_MASK_LSB BIT(30) /* 1b */ #define REG_GCE_D_APSRC_ACK_MASK_LSB BIT(31) /* 1b */ /* SPM_RESOURCE_ACK_MASK_3 (0x1C001000+0x8A8) */ #define REG_GCE_D_DDREN_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_GCE_D_EMI_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_GCE_D_INFRA_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_GCE_D_PMIC_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_GCE_D_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_GCE_D_VRF18_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_GCE_M_APSRC_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_GCE_M_DDREN_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_GCE_M_EMI_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_GCE_M_INFRA_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_GCE_M_PMIC_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_GCE_M_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_GCE_M_VRF18_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_GPUEB_APSRC_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_GPUEB_DDREN_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_GPUEB_EMI_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_GPUEB_INFRA_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_GPUEB_PMIC_ACK_MASK_LSB BIT(17) /* 1b */ #define REG_GPUEB_SRCCLKENA_ACK_MASK_LSB BIT(18) /* 1b */ #define REG_GPUEB_VRF18_ACK_MASK_LSB BIT(19) /* 1b */ #define REG_HWCCF_APSRC_ACK_MASK_LSB BIT(20) /* 1b */ #define REG_HWCCF_DDREN_ACK_MASK_LSB BIT(21) /* 1b */ #define REG_HWCCF_EMI_ACK_MASK_LSB BIT(22) /* 1b */ #define REG_HWCCF_INFRA_ACK_MASK_LSB BIT(23) /* 1b */ #define REG_HWCCF_PMIC_ACK_MASK_LSB BIT(24) /* 1b */ #define REG_HWCCF_SRCCLKENA_ACK_MASK_LSB BIT(25) /* 1b */ #define REG_HWCCF_VCORE_ACK_MASK_LSB BIT(26) /* 1b */ #define REG_HWCCF_VRF18_ACK_MASK_LSB BIT(27) /* 1b */ #define REG_IMG_APSRC_ACK_MASK_LSB BIT(28) /* 1b */ #define REG_IMG_DDREN_ACK_MASK_LSB BIT(29) /* 1b */ #define REG_IMG_EMI_ACK_MASK_LSB BIT(30) /* 1b */ #define REG_IMG_INFRA_ACK_MASK_LSB BIT(31) /* 1b */ /* SPM_RESOURCE_ACK_MASK_4 (0x1C001000+0x8AC) */ #define REG_IMG_PMIC_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_IMG_SRCCLKENA_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_IMG_VRF18_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_MCU_APSRC_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_MCU_DDREN_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_MCU_EMI_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_MD_APSRC_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_MD_DDREN_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_MD_EMI_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_MD_INFRA_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_MD_PMIC_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_MD_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_MD_VCORE_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_MD_VRF18_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_MM_PROC_APSRC_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_MM_PROC_DDREN_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_MM_PROC_EMI_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_MM_PROC_INFRA_ACK_MASK_LSB BIT(17) /* 1b */ #define REG_MM_PROC_PMIC_ACK_MASK_LSB BIT(18) /* 1b */ #define REG_MM_PROC_SRCCLKENA_ACK_MASK_LSB BIT(19) /* 1b */ #define REG_MM_PROC_VRF18_ACK_MASK_LSB BIT(20) /* 1b */ #define REG_PCIE0_APSRC_ACK_MASK_LSB BIT(21) /* 1b */ #define REG_PCIE0_DDREN_ACK_MASK_LSB BIT(22) /* 1b */ #define REG_PCIE0_INFRA_ACK_MASK_LSB BIT(23) /* 1b */ #define REG_PCIE0_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */ #define REG_PCIE0_VRF18_ACK_MASK_LSB BIT(25) /* 1b */ #define REG_PCIE1_APSRC_ACK_MASK_LSB BIT(26) /* 1b */ #define REG_PCIE1_DDREN_ACK_MASK_LSB BIT(27) /* 1b */ #define REG_PCIE1_INFRA_ACK_MASK_LSB BIT(28) /* 1b */ #define REG_PCIE1_SRCCLKENA_ACK_MASK_LSB BIT(29) /* 1b */ #define REG_PCIE1_VRF18_ACK_MASK_LSB BIT(30) /* 1b */ #define REG_PERISYS_APSRC_ACK_MASK_LSB BIT(31) /* 1b */ /* SPM_RESOURCE_ACK_MASK_5 (0x1C001000+0x8B0) */ #define REG_PERISYS_DDREN_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_PERISYS_EMI_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_PERISYS_INFRA_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_PERISYS_PMIC_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_PERISYS_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_PERISYS_VCORE_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_PERISYS_VRF18_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_SCP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_SCP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_SCP_EMI_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_SCP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_SCP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_SCP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_SCP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_SCP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_SSPM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_SSPM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_SSPM_EMI_ACK_MASK_LSB BIT(17) /* 1b */ #define REG_SSPM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */ #define REG_SSPM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */ #define REG_SSPM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */ #define REG_SSPM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */ #define REG_SSR_APSRC_ACK_MASK_LSB BIT(22) /* 1b */ #define REG_SSR_DDREN_ACK_MASK_LSB BIT(23) /* 1b */ #define REG_SSR_EMI_ACK_MASK_LSB BIT(24) /* 1b */ #define REG_SSR_INFRA_ACK_MASK_LSB BIT(25) /* 1b */ #define REG_SSR_PMIC_ACK_MASK_LSB BIT(26) /* 1b */ #define REG_SSR_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */ #define REG_SSR_VRF18_ACK_MASK_LSB BIT(28) /* 1b */ #define REG_UFS_APSRC_ACK_MASK_LSB BIT(29) /* 1b */ #define REG_UFS_DDREN_ACK_MASK_LSB BIT(30) /* 1b */ #define REG_UFS_EMI_ACK_MASK_LSB BIT(31) /* 1b */ /* SPM_RESOURCE_ACK_MASK_6 (0x1C001000+0x8B4) */ #define REG_UFS_INFRA_ACK_MASK_LSB BIT(0) /* 1b */ #define REG_UFS_PMIC_ACK_MASK_LSB BIT(1) /* 1b */ #define REG_UFS_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */ #define REG_UFS_VRF18_ACK_MASK_LSB BIT(3) /* 1b */ #define REG_VDEC_APSRC_ACK_MASK_LSB BIT(4) /* 1b */ #define REG_VDEC_DDREN_ACK_MASK_LSB BIT(5) /* 1b */ #define REG_VDEC_EMI_ACK_MASK_LSB BIT(6) /* 1b */ #define REG_VDEC_INFRA_ACK_MASK_LSB BIT(7) /* 1b */ #define REG_VDEC_PMIC_ACK_MASK_LSB BIT(8) /* 1b */ #define REG_VDEC_SRCCLKENA_ACK_MASK_LSB BIT(9) /* 1b */ #define REG_VDEC_VRF18_ACK_MASK_LSB BIT(10) /* 1b */ #define REG_VENC_APSRC_ACK_MASK_LSB BIT(11) /* 1b */ #define REG_VENC_DDREN_ACK_MASK_LSB BIT(12) /* 1b */ #define REG_VENC_EMI_ACK_MASK_LSB BIT(13) /* 1b */ #define REG_VENC_INFRA_ACK_MASK_LSB BIT(14) /* 1b */ #define REG_VENC_PMIC_ACK_MASK_LSB BIT(15) /* 1b */ #define REG_VENC_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 1b */ #define REG_VENC_VRF18_ACK_MASK_LSB BIT(17) /* 1b */ /* SPM_EVENT_COUNTER_CLEAR (0x1C001000+0x8B8) */ #define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(0) /* 1b */ /* SPM_VCORE_EVENT_COUNT_STA (0x1C001000+0x8BC) */ #define SPM_VCORE_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_VCORE_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_PMIC_EVENT_COUNT_STA (0x1C001000+0x8C0) */ #define SPM_PMIC_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_PMIC_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_SRCCLKENA_EVENT_COUNT_STA (0x1C001000+0x8C4) */ #define SPM_SRCCLKENA_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_SRCCLKENA_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_INFRA_EVENT_COUNT_STA (0x1C001000+0x8C8) */ #define SPM_INFRA_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_INFRA_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_VRF18_EVENT_COUNT_STA (0x1C001000+0x8CC) */ #define SPM_VRF18_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_VRF18_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_EMI_EVENT_COUNT_STA (0x1C001000+0x8D0) */ #define SPM_EMI_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_EMI_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_APSRC_EVENT_COUNT_STA (0x1C001000+0x8D4) */ #define SPM_APSRC_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_APSRC_WAKE_COUNT_LSB BIT(16) /* 16b */ /* SPM_DDREN_EVENT_COUNT_STA (0x1C001000+0x8D8) */ #define SPM_DDREN_SLEEP_COUNT_LSB BIT(0) /* 16b */ #define SPM_DDREN_WAKE_COUNT_LSB BIT(16) /* 16b */ /* PCM_WDT_LATCH_0 (0x1C001000+0x8DC) */ #define PCM_WDT_LATCH_0_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_1 (0x1C001000+0x8E0) */ #define PCM_WDT_LATCH_1_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_2 (0x1C001000+0x8E4) */ #define PCM_WDT_LATCH_2_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_3 (0x1C001000+0x8E8) */ #define PCM_WDT_LATCH_3_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_4 (0x1C001000+0x8EC) */ #define PCM_WDT_LATCH_4_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_5 (0x1C001000+0x8F0) */ #define PCM_WDT_LATCH_5_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_6 (0x1C001000+0x8F4) */ #define PCM_WDT_LATCH_6_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_7 (0x1C001000+0x8F8) */ #define PCM_WDT_LATCH_7_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_8 (0x1C001000+0x8FC) */ #define PCM_WDT_LATCH_8_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_9 (0x1C001000+0x900) */ #define PCM_WDT_LATCH_9_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_10 (0x1C001000+0x904) */ #define PCM_WDT_LATCH_10_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_11 (0x1C001000+0x908) */ #define PCM_WDT_LATCH_11_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_12 (0x1C001000+0x90C) */ #define PCM_WDT_LATCH_12_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_13 (0x1C001000+0x910) */ #define PCM_WDT_LATCH_13_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_14 (0x1C001000+0x914) */ #define PCM_WDT_LATCH_14_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_15 (0x1C001000+0x918) */ #define PCM_WDT_LATCH_15_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_16 (0x1C001000+0x91C) */ #define PCM_WDT_LATCH_16_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_17 (0x1C001000+0x920) */ #define PCM_WDT_LATCH_17_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_18 (0x1C001000+0x924) */ #define PCM_WDT_LATCH_18_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_19 (0x1C001000+0x928) */ #define PCM_WDT_LATCH_19_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_20 (0x1C001000+0x92C) */ #define PCM_WDT_LATCH_20_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_21 (0x1C001000+0x930) */ #define PCM_WDT_LATCH_21_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_22 (0x1C001000+0x934) */ #define PCM_WDT_LATCH_22_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_23 (0x1C001000+0x938) */ #define PCM_WDT_LATCH_23_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_24 (0x1C001000+0x93C) */ #define PCM_WDT_LATCH_24_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_25 (0x1C001000+0x940) */ #define PCM_WDT_LATCH_25_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_26 (0x1C001000+0x944) */ #define PCM_WDT_LATCH_26_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_27 (0x1C001000+0x948) */ #define PCM_WDT_LATCH_27_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_28 (0x1C001000+0x94C) */ #define PCM_WDT_LATCH_28_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_29 (0x1C001000+0x950) */ #define PCM_WDT_LATCH_29_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_30 (0x1C001000+0x954) */ #define PCM_WDT_LATCH_30_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_31 (0x1C001000+0x958) */ #define PCM_WDT_LATCH_31_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_32 (0x1C001000+0x95C) */ #define PCM_WDT_LATCH_32_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_33 (0x1C001000+0x960) */ #define PCM_WDT_LATCH_33_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_34 (0x1C001000+0x964) */ #define PCM_WDT_LATCH_34_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_35 (0x1C001000+0x968) */ #define PCM_WDT_LATCH_35_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_36 (0x1C001000+0x96C) */ #define PCM_WDT_LATCH_36_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_37 (0x1C001000+0x970) */ #define PCM_WDT_LATCH_37_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_38 (0x1C001000+0x974) */ #define PCM_WDT_LATCH_38_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_39 (0x1C001000+0x978) */ #define PCM_WDT_LATCH_39_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_40 (0x1C001000+0x97C) */ #define PCM_WDT_LATCH_40_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_0 (0x1C001000+0x980) */ #define PCM_WDT_LATCH_SPARE_0_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_1 (0x1C001000+0x984) */ #define PCM_WDT_LATCH_SPARE_1_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_2 (0x1C001000+0x988) */ #define PCM_WDT_LATCH_SPARE_2_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_3 (0x1C001000+0x98C) */ #define PCM_WDT_LATCH_SPARE_3_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_4 (0x1C001000+0x990) */ #define PCM_WDT_LATCH_SPARE_4_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_5 (0x1C001000+0x994) */ #define PCM_WDT_LATCH_SPARE_5_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_6 (0x1C001000+0x998) */ #define PCM_WDT_LATCH_SPARE_6_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_7 (0x1C001000+0x99C) */ #define PCM_WDT_LATCH_SPARE_7_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_8 (0x1C001000+0x9A0) */ #define PCM_WDT_LATCH_SPARE_8_LSB BIT(0) /* 32b */ /* PCM_WDT_LATCH_SPARE_9 (0x1C001000+0x9A4) */ #define PCM_WDT_LATCH_SPARE_9_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_0 (0x1C001000+0x9A8) */ #define DRAMC_GATING_ERR_LATCH_0_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_1 (0x1C001000+0x9AC) */ #define DRAMC_GATING_ERR_LATCH_1_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_2 (0x1C001000+0x9B0) */ #define DRAMC_GATING_ERR_LATCH_2_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_3 (0x1C001000+0x9B4) */ #define DRAMC_GATING_ERR_LATCH_3_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_4 (0x1C001000+0x9B8) */ #define DRAMC_GATING_ERR_LATCH_4_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_5 (0x1C001000+0x9BC) */ #define DRAMC_GATING_ERR_LATCH_5_LSB BIT(0) /* 32b */ /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x1C001000+0x9C0) */ #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB BIT(0) /* 32b */ /* SPM_DEBUG_CON (0x1C001000+0x9C4) */ #define SPM_DEBUG_OUT_ENABLE_LSB BIT(0) /* 1b */ /* SPM_ACK_CHK_CON_0 (0x1C001000+0x9C8) */ #define SPM_ACK_CHK_SW_EN_0_LSB BIT(0) /* 1b */ #define SPM_ACK_CHK_CLR_ALL_0_LSB BIT(1) /* 1b */ #define SPM_ACK_CHK_CLR_TIMER_0_LSB BIT(2) /* 1b */ #define SPM_ACK_CHK_CLR_IRQ_0_LSB BIT(3) /* 1b */ #define SPM_ACK_CHK_STA_EN_0_LSB BIT(4) /* 1b */ #define SPM_ACK_CHK_WAKEUP_EN_0_LSB BIT(5) /* 1b */ #define SPM_ACK_CHK_WDT_EN_0_LSB BIT(6) /* 1b */ #define SPM_ACK_CHK_SWINT_EN_0_LSB BIT(7) /* 1b */ #define SPM_ACK_CHK_HW_EN_0_LSB BIT(8) /* 1b */ #define SPM_ACK_CHK_HW_MODE_0_LSB BIT(9) /* 3b */ #define SPM_ACK_CHK_FAIL_0_LSB BIT(15) /* 1b */ /* SPM_ACK_CHK_SEL_0 (0x1C001000+0x9CC) */ #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB BIT(0) /* 5b */ #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB BIT(5) /* 3b */ #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB BIT(16) /* 5b */ #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB BIT(21) /* 3b */ /* SPM_ACK_CHK_TIMER_0 (0x1C001000+0x9D0) */ #define SPM_ACK_CHK_TIMER_VAL_0_LSB BIT(0) /* 16b */ #define SPM_ACK_CHK_TIMER_0_LSB BIT(16) /* 16b */ /* SPM_ACK_CHK_STA_0 (0x1C001000+0x9D4) */ #define SPM_ACK_CHK_STA_0_LSB BIT(0) /* 32b */ /* SPM_ACK_CHK_CON_1 (0x1C001000+0x9D8) */ #define SPM_ACK_CHK_SW_EN_1_LSB BIT(0) /* 1b */ #define SPM_ACK_CHK_CLR_ALL_1_LSB BIT(1) /* 1b */ #define SPM_ACK_CHK_CLR_TIMER_1_LSB BIT(2) /* 1b */ #define SPM_ACK_CHK_CLR_IRQ_1_LSB BIT(3) /* 1b */ #define SPM_ACK_CHK_STA_EN_1_LSB BIT(4) /* 1b */ #define SPM_ACK_CHK_WAKEUP_EN_1_LSB BIT(5) /* 1b */ #define SPM_ACK_CHK_WDT_EN_1_LSB BIT(6) /* 1b */ #define SPM_ACK_CHK_SWINT_EN_1_LSB BIT(7) /* 1b */ #define SPM_ACK_CHK_HW_EN_1_LSB BIT(8) /* 1b */ #define SPM_ACK_CHK_HW_MODE_1_LSB BIT(9) /* 3b */ #define SPM_ACK_CHK_FAIL_1_LSB BIT(15) /* 1b */ /* SPM_ACK_CHK_SEL_1 (0x1C001000+0x9DC) */ #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB BIT(0) /* 5b */ #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB BIT(5) /* 3b */ #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB BIT(16) /* 5b */ #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB BIT(21) /* 3b */ /* SPM_ACK_CHK_TIMER_1 (0x1C001000+0x9E0) */ #define SPM_ACK_CHK_TIMER_VAL_1_LSB BIT(0) /* 16b */ #define SPM_ACK_CHK_TIMER_1_LSB BIT(16) /* 16b */ /* SPM_ACK_CHK_STA_1 (0x1C001000+0x9E4) */ #define SPM_ACK_CHK_STA_1_LSB BIT(0) /* 32b */ /* SPM_ACK_CHK_CON_2 (0x1C001000+0x9E8) */ #define SPM_ACK_CHK_SW_EN_2_LSB BIT(0) /* 1b */ #define SPM_ACK_CHK_CLR_ALL_2_LSB BIT(1) /* 1b */ #define SPM_ACK_CHK_CLR_TIMER_2_LSB BIT(2) /* 1b */ #define SPM_ACK_CHK_CLR_IRQ_2_LSB BIT(3) /* 1b */ #define SPM_ACK_CHK_STA_EN_2_LSB BIT(4) /* 1b */ #define SPM_ACK_CHK_WAKEUP_EN_2_LSB BIT(5) /* 1b */ #define SPM_ACK_CHK_WDT_EN_2_LSB BIT(6) /* 1b */ #define SPM_ACK_CHK_SWINT_EN_2_LSB BIT(7) /* 1b */ #define SPM_ACK_CHK_HW_EN_2_LSB BIT(8) /* 1b */ #define SPM_ACK_CHK_HW_MODE_2_LSB BIT(9) /* 3b */ #define SPM_ACK_CHK_FAIL_2_LSB BIT(15) /* 1b */ /* SPM_ACK_CHK_SEL_2 (0x1C001000+0x9EC) */ #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB BIT(0) /* 5b */ #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB BIT(5) /* 3b */ #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB BIT(16) /* 5b */ #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB BIT(21) /* 3b */ /* SPM_ACK_CHK_TIMER_2 (0x1C001000+0x9F0) */ #define SPM_ACK_CHK_TIMER_VAL_2_LSB BIT(0) /* 16b */ #define SPM_ACK_CHK_TIMER_2_LSB BIT(16) /* 16b */ /* SPM_ACK_CHK_STA_2 (0x1C001000+0x9F4) */ #define SPM_ACK_CHK_STA_2_LSB BIT(0) /* 32b */ /* SPM_ACK_CHK_CON_3 (0x1C001000+0x9F8) */ #define SPM_ACK_CHK_SW_EN_3_LSB BIT(0) /* 1b */ #define SPM_ACK_CHK_CLR_ALL_3_LSB BIT(1) /* 1b */ #define SPM_ACK_CHK_CLR_TIMER_3_LSB BIT(2) /* 1b */ #define SPM_ACK_CHK_CLR_IRQ_3_LSB BIT(3) /* 1b */ #define SPM_ACK_CHK_STA_EN_3_LSB BIT(4) /* 1b */ #define SPM_ACK_CHK_WAKEUP_EN_3_LSB BIT(5) /* 1b */ #define SPM_ACK_CHK_WDT_EN_3_LSB BIT(6) /* 1b */ #define SPM_ACK_CHK_SWINT_EN_3_LSB BIT(7) /* 1b */ #define SPM_ACK_CHK_HW_EN_3_LSB BIT(8) /* 1b */ #define SPM_ACK_CHK_HW_MODE_3_LSB BIT(9) /* 3b */ #define SPM_ACK_CHK_FAIL_3_LSB BIT(15) /* 1b */ /* SPM_ACK_CHK_SEL_3 (0x1C001000+0x9FC) */ #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB BIT(0) /* 5b */ #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB BIT(5) /* 3b */ #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB BIT(16) /* 5b */ #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB BIT(21) /* 3b */ /* MD1_PWR_CON (0x1C001000+0xE00) */ #define MD1_PWR_RST_B_LSB BIT(0) /* 1b */ #define MD1_PWR_ISO_LSB BIT(1) /* 1b */ #define MD1_PWR_ON_LSB BIT(2) /* 1b */ #define MD1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MD1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MD1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MD1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MD1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MD1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MD1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CONN_PWR_CON (0x1C001000+0xE04) */ #define CONN_PWR_RST_B_LSB BIT(0) /* 1b */ #define CONN_PWR_ISO_LSB BIT(1) /* 1b */ #define CONN_PWR_ON_LSB BIT(2) /* 1b */ #define CONN_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CONN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CONN_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CONN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CONN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CONN_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CONN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* IFR_PWR_CON (0x1C001000+0xE08) */ #define IFR_PWR_RST_B_LSB BIT(0) /* 1b */ #define IFR_PWR_ISO_LSB BIT(1) /* 1b */ #define IFR_PWR_ON_LSB BIT(2) /* 1b */ #define IFR_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define IFR_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define IFR_SRAM_CKISO_LSB BIT(5) /* 1b */ #define IFR_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define IFR_SRAM_PDN_LSB BIT(8) /* 1b */ #define IFR_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_IFR_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_IFR_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define IFR_RTFF_SAVE_LSB BIT(24) /* 1b */ #define IFR_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define IFR_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_IFR_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_IFR_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* PERI_PWR_CON (0x1C001000+0xE0C) */ #define PERI_PWR_RST_B_LSB BIT(0) /* 1b */ #define PERI_PWR_ISO_LSB BIT(1) /* 1b */ #define PERI_PWR_ON_LSB BIT(2) /* 1b */ #define PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define PERI_SRAM_CKISO_LSB BIT(5) /* 1b */ #define PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define PERI_SRAM_PDN_LSB BIT(8) /* 1b */ #define PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define PERI_RTFF_SAVE_LSB BIT(24) /* 1b */ #define PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_PERI_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* UFS0_PWR_CON (0x1C001000+0xE10) */ #define UFS0_PWR_RST_B_LSB BIT(0) /* 1b */ #define UFS0_PWR_ISO_LSB BIT(1) /* 1b */ #define UFS0_PWR_ON_LSB BIT(2) /* 1b */ #define UFS0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define UFS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define UFS0_SRAM_CKISO_LSB BIT(5) /* 1b */ #define UFS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define UFS0_SRAM_PDN_LSB BIT(8) /* 1b */ #define UFS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_UFS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_UFS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define UFS0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define UFS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define UFS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_UFS0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_UFS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* UFS0_PHY_PWR_CON (0x1C001000+0xE14) */ #define UFS0_PHY_PWR_RST_B_LSB BIT(0) /* 1b */ #define UFS0_PHY_PWR_ISO_LSB BIT(1) /* 1b */ #define UFS0_PHY_PWR_ON_LSB BIT(2) /* 1b */ #define UFS0_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define UFS0_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define UFS0_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */ #define UFS0_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define UFS0_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_UFS0_PHY_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_UFS0_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* AUDIO_PWR_CON (0x1C001000+0xE18) */ #define AUDIO_PWR_RST_B_LSB BIT(0) /* 1b */ #define AUDIO_PWR_ISO_LSB BIT(1) /* 1b */ #define AUDIO_PWR_ON_LSB BIT(2) /* 1b */ #define AUDIO_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define AUDIO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define AUDIO_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_AUDIO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define AUDIO_RTFF_SAVE_LSB BIT(24) /* 1b */ #define AUDIO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define AUDIO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_AUDIO_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_AUDIO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ADSP_TOP_PWR_CON (0x1C001000+0xE1C) */ #define ADSP_TOP_PWR_RST_B_LSB BIT(0) /* 1b */ #define ADSP_TOP_PWR_ISO_LSB BIT(1) /* 1b */ #define ADSP_TOP_PWR_ON_LSB BIT(2) /* 1b */ #define ADSP_TOP_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ADSP_TOP_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ADSP_TOP_SRAM_CKISO_LSB BIT(5) /* 1b */ #define ADSP_TOP_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define ADSP_TOP_SRAM_PDN_LSB BIT(8) /* 1b */ #define ADSP_TOP_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_ADSP_TOP_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_ADSP_TOP_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define ADSP_TOP_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ADSP_TOP_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ADSP_TOP_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ADSP_TOP_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ADSP_TOP_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ADSP_INFRA_PWR_CON (0x1C001000+0xE20) */ #define ADSP_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */ #define ADSP_INFRA_PWR_ISO_LSB BIT(1) /* 1b */ #define ADSP_INFRA_PWR_ON_LSB BIT(2) /* 1b */ #define ADSP_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ADSP_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ADSP_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ADSP_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ADSP_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ADSP_INFRA_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ADSP_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ADSP_AO_PWR_CON (0x1C001000+0xE24) */ #define ADSP_AO_PWR_RST_B_LSB BIT(0) /* 1b */ #define ADSP_AO_PWR_ISO_LSB BIT(1) /* 1b */ #define ADSP_AO_PWR_ON_LSB BIT(2) /* 1b */ #define ADSP_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ADSP_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ADSP_AO_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ADSP_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ADSP_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ADSP_AO_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ADSP_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ISP_IMG1_PWR_CON (0x1C001000+0xE28) */ #define ISP_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */ #define ISP_MAIN_PWR_ISO_LSB BIT(1) /* 1b */ #define ISP_MAIN_PWR_ON_LSB BIT(2) /* 1b */ #define ISP_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ISP_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ISP_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_ISP_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define ISP_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ISP_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ISP_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ISP_MAIN_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ISP_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ISP_IMG2_PWR_CON (0x1C001000+0xE2C) */ #define ISP_DIP1_PWR_RST_B_LSB BIT(0) /* 1b */ #define ISP_DIP1_PWR_ISO_LSB BIT(1) /* 1b */ #define ISP_DIP1_PWR_ON_LSB BIT(2) /* 1b */ #define ISP_DIP1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ISP_DIP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ISP_DIP1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_ISP_DIP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define ISP_DIP1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ISP_DIP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ISP_DIP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ISP_DIP1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ISP_DIP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ISP_IPE_PWR_CON (0x1C001000+0xE30) */ #define ISP_IPE_PWR_RST_B_LSB BIT(0) /* 1b */ #define ISP_IPE_PWR_ISO_LSB BIT(1) /* 1b */ #define ISP_IPE_PWR_ON_LSB BIT(2) /* 1b */ #define ISP_IPE_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ISP_IPE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ISP_IPE_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_ISP_IPE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define ISP_IPE_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ISP_IPE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ISP_IPE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ISP_IPE_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ISP_IPE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ISP_VCORE_PWR_CON (0x1C001000+0xE34) */ #define ISP_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */ #define ISP_VCORE_PWR_ISO_LSB BIT(1) /* 1b */ #define ISP_VCORE_PWR_ON_LSB BIT(2) /* 1b */ #define ISP_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define ISP_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define ISP_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */ #define ISP_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define ISP_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_ISP_VCORE_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_ISP_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* VDE0_PWR_CON (0x1C001000+0xE38) */ #define VDE0_PWR_RST_B_LSB BIT(0) /* 1b */ #define VDE0_PWR_ISO_LSB BIT(1) /* 1b */ #define VDE0_PWR_ON_LSB BIT(2) /* 1b */ #define VDE0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define VDE0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define VDE0_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_VDE0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define VDE0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define VDE0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define VDE0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_VDE0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_VDE0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* VDE1_PWR_CON (0x1C001000+0xE3C) */ #define VDE1_PWR_RST_B_LSB BIT(0) /* 1b */ #define VDE1_PWR_ISO_LSB BIT(1) /* 1b */ #define VDE1_PWR_ON_LSB BIT(2) /* 1b */ #define VDE1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define VDE1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define VDE1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_VDE1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define VDE1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define VDE1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define VDE1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_VDE1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_VDE1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* VEN0_PWR_CON (0x1C001000+0xE40) */ #define VEN0_PWR_RST_B_LSB BIT(0) /* 1b */ #define VEN0_PWR_ISO_LSB BIT(1) /* 1b */ #define VEN0_PWR_ON_LSB BIT(2) /* 1b */ #define VEN0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define VEN0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define VEN0_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_VEN0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define VEN0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define VEN0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define VEN0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_VEN0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_VEN0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* VEN1_PWR_CON (0x1C001000+0xE44) */ #define VEN1_PWR_RST_B_LSB BIT(0) /* 1b */ #define VEN1_PWR_ISO_LSB BIT(1) /* 1b */ #define VEN1_PWR_ON_LSB BIT(2) /* 1b */ #define VEN1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define VEN1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define VEN1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_VEN1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define VEN1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define VEN1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define VEN1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_VEN1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_VEN1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_MAIN_PWR_CON (0x1C001000+0xE48) */ #define CAM_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_MAIN_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_MAIN_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_MAIN_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_MRAW_PWR_CON (0x1C001000+0xE4C) */ #define CAM_MRAW_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_MRAW_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_MRAW_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_MRAW_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_MRAW_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_MRAW_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_MRAW_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_MRAW_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_MRAW_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_MRAW_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_MRAW_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_MRAW_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_SUBA_PWR_CON (0x1C001000+0xE50) */ #define CAM_SUBA_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_SUBA_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_SUBA_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_SUBA_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_SUBA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_SUBA_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_SUBA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_SUBA_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_SUBA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_SUBA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_SUBA_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_SUBA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_SUBB_PWR_CON (0x1C001000+0xE54) */ #define CAM_SUBB_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_SUBB_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_SUBB_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_SUBB_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_SUBB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_SUBB_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_SUBB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_SUBB_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_SUBB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_SUBB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_SUBB_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_SUBB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_SUBC_PWR_CON (0x1C001000+0xE58) */ #define CAM_SUBC_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_SUBC_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_SUBC_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_SUBC_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_SUBC_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_SUBC_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_SUBC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_SUBC_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_SUBC_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_SUBC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_SUBC_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_SUBC_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_VCORE_PWR_CON (0x1C001000+0xE5C) */ #define CAM_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_VCORE_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_VCORE_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_VCORE_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_CCU_PWR_CON (0x1C001000+0xE60) */ #define CAM_CCU_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_CCU_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_CCU_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_CCU_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_CCU_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_CCU_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CAM_CCU_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CAM_CCU_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_CCU_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_CCU_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_CCU_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_CCU_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CAM_CCU_AO_PWR_CON (0x1C001000+0xE64) */ #define CAM_CCU_AO_PWR_RST_B_LSB BIT(0) /* 1b */ #define CAM_CCU_AO_PWR_ISO_LSB BIT(1) /* 1b */ #define CAM_CCU_AO_PWR_ON_LSB BIT(2) /* 1b */ #define CAM_CCU_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CAM_CCU_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CAM_CCU_AO_SRAM_CKISO_LSB BIT(5) /* 1b */ #define CAM_CCU_AO_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define CAM_CCU_AO_SRAM_PDN_LSB BIT(8) /* 1b */ #define CAM_CCU_AO_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_CAM_CCU_AO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_CAM_CCU_AO_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define CAM_CCU_AO_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CAM_CCU_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CAM_CCU_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CAM_CCU_AO_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CAM_CCU_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MDP0_PWR_CON (0x1C001000+0xE68) */ #define MDP0_PWR_RST_B_LSB BIT(0) /* 1b */ #define MDP0_PWR_ISO_LSB BIT(1) /* 1b */ #define MDP0_PWR_ON_LSB BIT(2) /* 1b */ #define MDP0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MDP0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MDP0_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MDP0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MDP0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MDP0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MDP0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MDP0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MDP0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MDP1_PWR_CON (0x1C001000+0xE6C) */ #define MDP1_PWR_RST_B_LSB BIT(0) /* 1b */ #define MDP1_PWR_ISO_LSB BIT(1) /* 1b */ #define MDP1_PWR_ON_LSB BIT(2) /* 1b */ #define MDP1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MDP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MDP1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MDP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MDP1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MDP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MDP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MDP1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MDP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* DIS0_PWR_CON (0x1C001000+0xE70) */ #define DIS0_PWR_RST_B_LSB BIT(0) /* 1b */ #define DIS0_PWR_ISO_LSB BIT(1) /* 1b */ #define DIS0_PWR_ON_LSB BIT(2) /* 1b */ #define DIS0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define DIS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define DIS0_SRAM_CKISO_LSB BIT(5) /* 1b */ #define DIS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define DIS0_SRAM_PDN_LSB BIT(8) /* 1b */ #define DIS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_DIS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_DIS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define DIS0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define DIS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define DIS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_DIS0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_DIS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* DIS1_PWR_CON (0x1C001000+0xE74) */ #define DIS1_PWR_RST_B_LSB BIT(0) /* 1b */ #define DIS1_PWR_ISO_LSB BIT(1) /* 1b */ #define DIS1_PWR_ON_LSB BIT(2) /* 1b */ #define DIS1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define DIS1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define DIS1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_DIS1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define DIS1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define DIS1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define DIS1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_DIS1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_DIS1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MM_INFRA_PWR_CON (0x1C001000+0xE78) */ #define MM_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */ #define MM_INFRA_PWR_ISO_LSB BIT(1) /* 1b */ #define MM_INFRA_PWR_ON_LSB BIT(2) /* 1b */ #define MM_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MM_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MM_INFRA_SRAM_CKISO_LSB BIT(5) /* 1b */ #define MM_INFRA_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define MM_INFRA_SRAM_PDN_LSB BIT(8) /* 1b */ #define MM_INFRA_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_MM_INFRA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_MM_INFRA_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define MM_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MM_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MM_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MM_INFRA_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MM_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MM_PROC_PWR_CON (0x1C001000+0xE7C) */ #define MM_PROC_PWR_RST_B_LSB BIT(0) /* 1b */ #define MM_PROC_PWR_ISO_LSB BIT(1) /* 1b */ #define MM_PROC_PWR_ON_LSB BIT(2) /* 1b */ #define MM_PROC_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MM_PROC_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MM_PROC_SRAM_CKISO_LSB BIT(5) /* 1b */ #define MM_PROC_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define MM_PROC_SRAM_PDN_LSB BIT(8) /* 1b */ #define MM_PROC_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_MM_PROC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_MM_PROC_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define MM_PROC_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MM_PROC_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MM_PROC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MM_PROC_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MM_PROC_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* DP_TX_PWR_CON (0x1C001000+0xE80) */ #define DP_TX_PWR_RST_B_LSB BIT(0) /* 1b */ #define DP_TX_PWR_ISO_LSB BIT(1) /* 1b */ #define DP_TX_PWR_ON_LSB BIT(2) /* 1b */ #define DP_TX_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define DP_TX_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define DP_TX_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_DP_TX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define DP_TX_RTFF_SAVE_LSB BIT(24) /* 1b */ #define DP_TX_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define DP_TX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_DP_TX_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_DP_TX_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SCP_CORE_PWR_CON (0x1C001000+0xE84) */ #define SCP_CORE_PWR_RST_B_LSB BIT(0) /* 1b */ #define SCP_CORE_PWR_ISO_LSB BIT(1) /* 1b */ #define SCP_CORE_PWR_ON_LSB BIT(2) /* 1b */ #define SCP_CORE_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SCP_CORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SCP_CORE_SRAM_CKISO_LSB BIT(5) /* 1b */ #define SCP_CORE_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define SCP_CORE_SRAM_PDN_LSB BIT(8) /* 1b */ #define SCP_CORE_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_SCP_CORE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_SCP_CORE_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define SCP_CORE_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SCP_CORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SCP_CORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SCP_CORE_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SCP_CORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SCP_PERI_PWR_CON (0x1C001000+0xE88) */ #define SCP_PERI_PWR_RST_B_LSB BIT(0) /* 1b */ #define SCP_PERI_PWR_ISO_LSB BIT(1) /* 1b */ #define SCP_PERI_PWR_ON_LSB BIT(2) /* 1b */ #define SCP_PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SCP_PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SCP_PERI_SRAM_CKISO_LSB BIT(5) /* 1b */ #define SCP_PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define SCP_PERI_SRAM_PDN_LSB BIT(8) /* 1b */ #define SCP_PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_SCP_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_SCP_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define SCP_PERI_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SCP_PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SCP_PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SCP_PERI_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SCP_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* DPM0_PWR_CON (0x1C001000+0xE8C) */ #define DPM0_PWR_RST_B_LSB BIT(0) /* 1b */ #define DPM0_PWR_ISO_LSB BIT(1) /* 1b */ #define DPM0_PWR_ON_LSB BIT(2) /* 1b */ #define DPM0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define DPM0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define DPM0_SRAM_CKISO_LSB BIT(5) /* 1b */ #define DPM0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define DPM0_SRAM_PDN_LSB BIT(8) /* 1b */ #define DPM0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_DPM0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_DPM0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define DPM0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define DPM0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define DPM0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_DPM0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_DPM0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* DPM1_PWR_CON (0x1C001000+0xE90) */ #define DPM1_PWR_RST_B_LSB BIT(0) /* 1b */ #define DPM1_PWR_ISO_LSB BIT(1) /* 1b */ #define DPM1_PWR_ON_LSB BIT(2) /* 1b */ #define DPM1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define DPM1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define DPM1_SRAM_CKISO_LSB BIT(5) /* 1b */ #define DPM1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define DPM1_SRAM_PDN_LSB BIT(8) /* 1b */ #define DPM1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_DPM1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_DPM1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define DPM1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define DPM1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define DPM1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_DPM1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_DPM1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* EMI0_PWR_CON (0x1C001000+0xE94) */ #define EMI0_PWR_RST_B_LSB BIT(0) /* 1b */ #define EMI0_PWR_ISO_LSB BIT(1) /* 1b */ #define EMI0_PWR_ON_LSB BIT(2) /* 1b */ #define EMI0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define EMI0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define EMI0_SRAM_CKISO_LSB BIT(5) /* 1b */ #define EMI0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define EMI0_SRAM_PDN_LSB BIT(8) /* 1b */ #define EMI0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_EMI0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_EMI0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define EMI0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define EMI0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define EMI0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_EMI0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_EMI0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* EMI1_PWR_CON (0x1C001000+0xE98) */ #define EMI1_PWR_RST_B_LSB BIT(0) /* 1b */ #define EMI1_PWR_ISO_LSB BIT(1) /* 1b */ #define EMI1_PWR_ON_LSB BIT(2) /* 1b */ #define EMI1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define EMI1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define EMI1_SRAM_CKISO_LSB BIT(5) /* 1b */ #define EMI1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define EMI1_SRAM_PDN_LSB BIT(8) /* 1b */ #define EMI1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_EMI1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_EMI1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define EMI1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define EMI1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define EMI1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_EMI1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_EMI1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CSI_RX_PWR_CON (0x1C001000+0xE9C) */ #define CSI_RX_PWR_RST_B_LSB BIT(0) /* 1b */ #define CSI_RX_PWR_ISO_LSB BIT(1) /* 1b */ #define CSI_RX_PWR_ON_LSB BIT(2) /* 1b */ #define CSI_RX_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CSI_RX_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CSI_RX_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CSI_RX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define CSI_RX_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CSI_RX_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CSI_RX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CSI_RX_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CSI_RX_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SSRSYS_PWR_CON (0x1C001000+0xEA0) */ #define SSRSYS_PWR_RST_B_LSB BIT(0) /* 1b */ #define SSRSYS_PWR_ISO_LSB BIT(1) /* 1b */ #define SSRSYS_PWR_ON_LSB BIT(2) /* 1b */ #define SSRSYS_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SSRSYS_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SSRSYS_SRAM_CKISO_LSB BIT(5) /* 1b */ #define SSRSYS_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define SSRSYS_SRAM_PDN_LSB BIT(8) /* 1b */ #define SSRSYS_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_SSRSYS_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_SSRSYS_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define SSRSYS_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SSRSYS_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SSRSYS_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SSRSYS_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SSRSYS_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SSPM_PWR_CON (0x1C001000+0xEA4) */ #define SSPM_PWR_RST_B_LSB BIT(0) /* 1b */ #define SSPM_PWR_ISO_LSB BIT(1) /* 1b */ #define SSPM_PWR_ON_LSB BIT(2) /* 1b */ #define SSPM_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SSPM_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SSPM_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SSPM_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SSPM_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SSPM_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SSPM_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SSUSB_PWR_CON (0x1C001000+0xEA8) */ #define SSUSB_PWR_RST_B_LSB BIT(0) /* 1b */ #define SSUSB_PWR_ISO_LSB BIT(1) /* 1b */ #define SSUSB_PWR_ON_LSB BIT(2) /* 1b */ #define SSUSB_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SSUSB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SSUSB_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_SSUSB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SSUSB_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SSUSB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SSUSB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SSUSB_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SSUSB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* SSUSB_PHY_PWR_CON (0x1C001000+0xEAC) */ #define SSUSB_PHY_PWR_RST_B_LSB BIT(0) /* 1b */ #define SSUSB_PHY_PWR_ISO_LSB BIT(1) /* 1b */ #define SSUSB_PHY_PWR_ON_LSB BIT(2) /* 1b */ #define SSUSB_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define SSUSB_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define SSUSB_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */ #define SSUSB_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define SSUSB_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_SSUSB_PHY_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_SSUSB_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* CPUEB_PWR_CON (0x1C001000+0xEB0) */ #define CPUEB_PWR_RST_B_LSB BIT(0) /* 1b */ #define CPUEB_PWR_ISO_LSB BIT(1) /* 1b */ #define CPUEB_PWR_ON_LSB BIT(2) /* 1b */ #define CPUEB_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define CPUEB_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define CPUEB_SRAM_CKISO_LSB BIT(5) /* 1b */ #define CPUEB_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define CPUEB_SRAM_PDN_LSB BIT(8) /* 1b */ #define CPUEB_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_CPUEB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_CPUEB_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define CPUEB_RTFF_SAVE_LSB BIT(24) /* 1b */ #define CPUEB_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define CPUEB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_CPUEB_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_CPUEB_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG0_PWR_CON (0x1C001000+0xEB4) */ #define MFG0_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG0_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG0_PWR_ON_LSB BIT(2) /* 1b */ #define MFG0_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG0_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG0_SRAM_CKISO_LSB BIT(5) /* 1b */ #define MFG0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */ #define MFG0_SRAM_PDN_LSB BIT(8) /* 1b */ #define MFG0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */ #define SC_MFG0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define SC_MFG0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */ #define MFG0_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG0_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG0_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG0_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG1_PWR_CON (0x1C001000+0xEB8) */ #define MFG1_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG1_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG1_PWR_ON_LSB BIT(2) /* 1b */ #define MFG1_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG1_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG1_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG1_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG1_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG1_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG1_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG2_PWR_CON (0x1C001000+0xEBC) */ #define MFG2_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG2_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG2_PWR_ON_LSB BIT(2) /* 1b */ #define MFG2_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG2_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG2_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG2_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG2_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG2_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG2_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG2_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG2_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG3_PWR_CON (0x1C001000+0xEC0) */ #define MFG3_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG3_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG3_PWR_ON_LSB BIT(2) /* 1b */ #define MFG3_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG3_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG3_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG3_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG3_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG3_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG3_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG3_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG3_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG4_PWR_CON (0x1C001000+0xEC4) */ #define MFG4_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG4_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG4_PWR_ON_LSB BIT(2) /* 1b */ #define MFG4_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG4_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG4_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG4_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG4_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG4_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG4_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG4_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG4_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG5_PWR_CON (0x1C001000+0xEC8) */ #define MFG5_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG5_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG5_PWR_ON_LSB BIT(2) /* 1b */ #define MFG5_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG5_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG5_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG5_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG5_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG5_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG5_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG5_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG5_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG6_PWR_CON (0x1C001000+0xECC) */ #define MFG6_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG6_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG6_PWR_ON_LSB BIT(2) /* 1b */ #define MFG6_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG6_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG6_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG6_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG6_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG6_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG6_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG6_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG6_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* MFG7_PWR_CON (0x1C001000+0xED0) */ #define MFG7_PWR_RST_B_LSB BIT(0) /* 1b */ #define MFG7_PWR_ISO_LSB BIT(1) /* 1b */ #define MFG7_PWR_ON_LSB BIT(2) /* 1b */ #define MFG7_PWR_ON_2ND_LSB BIT(3) /* 1b */ #define MFG7_PWR_CLK_DIS_LSB BIT(4) /* 1b */ #define MFG7_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_MFG7_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ #define MFG7_RTFF_SAVE_LSB BIT(24) /* 1b */ #define MFG7_RTFF_NRESTORE_LSB BIT(25) /* 1b */ #define MFG7_RTFF_CLK_DIS_LSB BIT(28) /* 1b */ #define SC_MFG7_PWR_ACK_LSB BIT(30) /* 1b */ #define SC_MFG7_PWR_ACK_2ND_LSB BIT(31) /* 1b */ /* ADSP_HRE_SRAM_CON (0x1C001000+0xED4) */ #define ADSP_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ #define ADSP_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define ADSP_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define ADSP_HRE_SRAM_PDN_LSB BIT(16) /* 1b */ /* CCU_SLEEP_SRAM_CON (0x1C001000+0xED8) */ #define CCU_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ #define CCU_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define CCU_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define CCU_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_CCU_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ #define SC_CCU_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ /* EFUSE_SRAM_CON (0x1C001000+0xEDC) */ #define EFUSE_SRAM_CKISO_LSB BIT(0) /* 1b */ #define EFUSE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define EFUSE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define EFUSE_SRAM_PDN_LSB BIT(16) /* 1b */ /* EMI_HRE_SRAM_CON (0x1C001000+0xEE0) */ #define EMI_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ #define EMI_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define EMI_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 8b */ #define EMI_HRE_SRAM_PDN_LSB BIT(16) /* 8b */ /* EMI_SLB_SRAM_CON (0x1C001000+0xEE4) */ #define EMI_SLB_SRAM_PDN_LSB BIT(0) /* 12b */ #define SC_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 12b */ /* INFRA_HRE_SRAM_CON (0x1C001000+0xEE8) */ #define INFRA_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ #define INFRA_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 2b */ #define INFRA_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 6b */ #define INFRA_HRE_SRAM_PDN_LSB BIT(16) /* 6b */ /* INFRA_SLEEP_SRAM_CON (0x1C001000+0xEEC) */ #define INFRA_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ #define INFRA_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 2b */ #define INFRA_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 2b */ #define INFRA_SLEEP_SRAM_PDN_LSB BIT(8) /* 2b */ #define SC_INFRA_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 2b */ #define SC_INFRA_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(18) /* 2b */ /* MM_HRE_SRAM_CON (0x1C001000+0xEF0) */ #define MM_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */ #define MM_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 3b */ #define MM_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 3b */ #define MM_HRE_SRAM_PDN_LSB BIT(16) /* 3b */ /* NTH_EMI_SLB_SRAM_CON (0x1C001000+0xEF4) */ #define NTH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */ #define NTH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */ /* NTH_EMI_SLB_SRAM_ACK (0x1C001000+0xEF8) */ #define SC_NTH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */ #define SC_NTH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */ /* PERI_SLEEP_SRAM_CON (0x1C001000+0xEFC) */ #define PERI_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ #define PERI_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define PERI_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define PERI_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_PERI_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ #define SC_PERI_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ /* SPM_SRAM_CON (0x1C001000+0xF00) */ #define SPM_SRAM_CKISO_LSB BIT(0) /* 1b */ #define REG_SPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define REG_SPM_SRAM_SLEEP_B_LSB BIT(4) /* 4b */ #define SPM_SRAM_PDN_LSB BIT(16) /* 4b */ /* SSPM_SRAM_CON (0x1C001000+0xF04) */ #define SSPM_SRAM_CKISO_LSB BIT(0) /* 1b */ #define SSPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define SSPM_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define SSPM_SRAM_PDN_LSB BIT(16) /* 1b */ /* SSR_SLEEP_SRAM_CON (0x1C001000+0xF08) */ #define SSR_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ #define SSR_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define SSR_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define SSR_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_SSR_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ #define SC_SSR_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ /* STH_EMI_SLB_SRAM_CON (0x1C001000+0xF0C) */ #define STH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */ #define STH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */ /* STH_EMI_SLB_SRAM_ACK (0x1C001000+0xF10) */ #define SC_STH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */ #define SC_STH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */ /* UFS_PDN_SRAM_CON (0x1C001000+0xF14) */ #define UFS_PDN_SRAM_PDN_LSB BIT(0) /* 1b */ #define SC_UFS_PDN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */ /* UFS_SLEEP_SRAM_CON (0x1C001000+0xF18) */ #define UFS_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */ #define UFS_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */ #define UFS_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */ #define UFS_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */ #define SC_UFS_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */ #define SC_UFS_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */ /* UNIPRO_PDN_SRAM_CON (0x1C001000+0xF1C) */ #define UNIPRO_PDN_SRAM_PDN_LSB BIT(0) /* 1b */ #define SC_UNIPRO_PDN_SRAM_PDN_ACK_LSB BIT(8) /* 1b */ /* CPU_BUCK_ISO_CON (0x1C001000+0xF20) */ #define MCUSYS_VPROC_EXT_OFF_LSB BIT(0) /* 1b */ #define MP0_VPROC_EXT_OFF_LSB BIT(1) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU0_LSB BIT(2) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU1_LSB BIT(3) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU2_LSB BIT(4) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU3_LSB BIT(5) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU4_LSB BIT(6) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU5_LSB BIT(7) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU6_LSB BIT(8) /* 1b */ #define MP0_VPROC_EXT_OFF_CPU7_LSB BIT(9) /* 1b */ #define MP0_VSRAM_EXT_OFF_LSB BIT(10) /* 1b */ /* MD_BUCK_ISO_CON (0x1C001000+0xF24) */ #define VMD_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define AOC_VMD_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define AOC_VMD_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define AOC_VMD_ANA_ISO_LSB BIT(3) /* 1b */ #define VMODEM_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define AOC_VMODEM_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define AOC_VMODEM_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define AOC_VMODEM_ANA_ISO_LSB BIT(7) /* 1b */ /* SOC_BUCK_ISO_CON (0x1C001000+0xF28) */ #define SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ #define VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ #define VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ #define AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ #define AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ #define AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ #define VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ #define AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ #define AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ #define AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ #define VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ #define AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ #define AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ #define AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ #define VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ #define AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ #define AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ #define AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ #define VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ #define AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ #define AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ #define AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ #define VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ #define AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ #define AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ #define AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ /* SOC_BUCK_ISO_CON_SET (0x1C001000+0xF2C) */ #define SOC_BUCK_ISO_CON_SET_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ #define SOC_BUCK_ISO_CON_SET_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ /* SOC_BUCK_ISO_CON_CLR (0x1C001000+0xF30) */ #define SOC_BUCK_ISO_CON_CLR_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */ #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */ /* SOC_BUCK_ISO_CON_2 (0x1C001000+0xF34) */ #define VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ #define VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ /* SOC_BUCK_ISO_CON_2_SET (0x1C001000+0xF38) */ #define SOC_BUCK_ISO_CON_2_SET_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ /* SOC_BUCK_ISO_CON_2_CLR (0x1C001000+0xF3C) */ #define SOC_BUCK_ISO_CON_2_CLR_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */ #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */ /* PWR_STATUS (0x1C001000+0xF40) */ #define PWR_STATUS_LSB BIT(0) /* 32b */ /* PWR_STATUS_2ND (0x1C001000+0xF44) */ #define PWR_STATUS_2ND_LSB BIT(0) /* 32b */ /* PWR_STATUS_MSB (0x1C001000+0xF48) */ #define PWR_STATUS_MSB_LSB BIT(0) /* 32b */ /* PWR_STATUS_MSB_2ND (0x1C001000+0xF4C) */ #define PWR_STATUS_MSB_2ND_LSB BIT(0) /* 32b */ /* XPU_PWR_STATUS (0x1C001000+0xF50) */ #define XPU_PWR_STATUS_LSB BIT(0) /* 32b */ /* XPU_PWR_STATUS_2ND (0x1C001000+0xF54) */ #define XPU_PWR_STATUS_2ND_LSB BIT(0) /* 32b */ /* DFD_SOC_PWR_LATCH (0x1C001000+0xF58) */ #define DFD_SOC_PWR_LATCH_LSB BIT(0) /* 32b */ /* SUBSYS_PM_BYPASS (0x1C001000+0xF5C) */ #define PM_BYPASS_MODE_LSB BIT(0) /* 16b */ /* SPM_TWAM_CON (0x1C001000+0xF80) */ #define REG_TWAM_ENABLE_LSB BIT(0) /* 1b */ #define REG_TWAM_SPEED_MODE_EN_LSB BIT(1) /* 1b */ #define SPM_TWAM_EVENT_CLEAR_LSB BIT(2) /* 1b */ #define REG_TWAM_IRQ_MASK_LSB BIT(3) /* 1b */ #define REG_TWAM_MON_TYPE_0_LSB BIT(4) /* 2b */ #define REG_TWAM_MON_TYPE_1_LSB BIT(6) /* 2b */ #define REG_TWAM_MON_TYPE_2_LSB BIT(8) /* 2b */ #define REG_TWAM_MON_TYPE_3_LSB BIT(10) /* 2b */ #define REG_TWAM_IRQ_CLEAR_LSB BIT(16) /* 1b */ #define TWAM_IRQ_LSB BIT(24) /* 1b */ /* SPM_TWAM_WINDOW_LEN (0x1C001000+0xF84) */ #define REG_TWAM_WINDOW_LEN_LSB BIT(0) /* 32b */ /* SPM_TWAM_IDLE_SEL (0x1C001000+0xF88) */ #define REG_TWAM_SIG_SEL_0_LSB BIT(0) /* 7b */ #define REG_TWAM_SIG_SEL_1_LSB BIT(8) /* 7b */ #define REG_TWAM_SIG_SEL_2_LSB BIT(16) /* 7b */ #define REG_TWAM_SIG_SEL_3_LSB BIT(24) /* 7b */ /* SPM_TWAM_LAST_STA_0 (0x1C001000+0xF8C) */ #define TWAM_LAST_IDLE_CNT_0_LSB BIT(0) /* 32b */ /* SPM_TWAM_LAST_STA_1 (0x1C001000+0xF90) */ #define TWAM_LAST_IDLE_CNT_1_LSB BIT(0) /* 32b */ /* SPM_TWAM_LAST_STA_2 (0x1C001000+0xF94) */ #define TWAM_LAST_IDLE_CNT_2_LSB BIT(0) /* 32b */ /* SPM_TWAM_LAST_STA_3 (0x1C001000+0xF98) */ #define TWAM_LAST_IDLE_CNT_3_LSB BIT(0) /* 32b */ /* SPM_TWAM_CURR_STA_0 (0x1C001000+0xF9C) */ #define TWAM_CURRENT_IDLE_CNT_0_LSB BIT(0) /* 32b */ /* SPM_TWAM_CURR_STA_1 (0x1C001000+0xFA0) */ #define TWAM_CURRENT_IDLE_CNT_1_LSB BIT(0) /* 32b */ /* SPM_TWAM_CURR_STA_2 (0x1C001000+0xFA4) */ #define TWAM_CURRENT_IDLE_CNT_2_LSB BIT(0) /* 32b */ /* SPM_TWAM_CURR_STA_3 (0x1C001000+0xFA8) */ #define TWAM_CURRENT_IDLE_CNT_3_LSB BIT(0) /* 32b */ /* SPM_TWAM_TIMER_OUT (0x1C001000+0xFAC) */ #define TWAM_TIMER_LSB BIT(0) /* 32b */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) #endif