// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2023-2025 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */

#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/firewall/stm32mp25-rif.h>
#include <dt-bindings/firewall/stm32mp25-rifsc.h>
#include <dt-bindings/firewall/stm32mp25-risaf.h>
#include <dt-bindings/firewall/stm32mp25-risab.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a35";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	intc: interrupt-controller@4ac00000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x4ac10000 0x0 0x1000>,
		      <0x0 0x4ac20000 0x0 0x2000>,
		      <0x0 0x4ac40000 0x0 0x2000>,
		      <0x0 0x4ac60000 0x0 0x2000>;
		#address-cells = <1>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_msi: clk-msi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};

		clk_i2sin: clk-i2sin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_rcbsec: clk-rcbsec {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges = <0x0 0x0 0x0 0x80000000>;

		hpdma1: dma-controller@40400000 {
			compatible = "st,stm32-dma3";
			reg = <0x40400000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA1>;
			resets = <&rcc HPDMA1_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		hpdma2: dma-controller@40410000 {
			compatible = "st,stm32-dma3";
			reg = <0x40410000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA2>;
			resets = <&rcc HPDMA2_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		hpdma3: dma-controller@40420000 {
			compatible = "st,stm32-dma3";
			reg = <0x40420000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA3>;
			resets = <&rcc HPDMA3_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		ipcc1: mailbox@40490000 {
			compatible = "st,stm32mp25-ipcc";
			reg = <0x40490000 0x400>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "rx";
			clocks = <&rcc CK_BUS_IPCC1>;
			status = "disabled";
		};

		ommanager: ommanager@40500000 {
			compatible = "st,stm32mp25-omm";
			reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
			reg-names = "regs", "memory_map";
			ranges = <0 0 0x40430000 0x400>,
				 <1 0 0x40440000 0x400>;
			clocks = <&rcc CK_BUS_OSPIIOM>;
			resets = <&rcc OSPIIOM_R>;
			#address-cells = <2>;
			#size-cells = <1>;
			st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
			status = "disabled";

			ospi1: spi@0 {
				compatible = "st,stm32mp25-ospi";
				reg = <0 0 0x400>;
				clocks = <&rcc CK_KER_OSPI1>;
				resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>;
				status = "disabled";
			};

			ospi2: spi@1 {
				compatible = "st,stm32mp25-ospi";
				reg = <1 0 0x400>;
				clocks = <&rcc CK_KER_OSPI2>;
				resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>;
				status = "disabled";
			};
		};

		rifsc: rifsc@42080000 {
			compatible = "st,stm32mp25-rifsc", "simple-bus";
			reg = <0x42080000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			#access-controller-cells = <1>;

			usart2: serial@400e0000 {
				compatible = "st,stm32h7-uart";
				reg = <0x400e0000 0x400>;
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART2>;
				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
				status = "disabled";
			};

			rng: rng@42020000 {
				compatible = "st,stm32mp25-rng";
				reg = <0x42020000 0x400>;
				clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>;
				clock-names = "rng_clk", "rng_hclk";
				resets = <&rcc RNG_R>;
				access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>;
			};

			iwdg1: watchdog@44010000 {
				compatible = "st,stm32mp1-iwdg";
				reg = <0x44010000 0x400>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>;
				clock-names = "pclk", "lsi";
				access-controllers = <&rifsc STM32MP25_RIFSC_IWDG1_ID>;
				status = "disabled";
			};

			iwdg2: watchdog@44020000 {
				compatible = "st,stm32mp1-iwdg";
				reg = <0x44020000 0x400>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>;
				clock-names = "pclk", "lsi";
				resets = <&rcc IWDG2_SYS_R>;
				access-controllers = <&rifsc STM32MP25_RIFSC_IWDG2_ID>;
				status = "disabled";
			};
		};

		iac: iac@42090000 {
			compatible = "st,stm32mp25-iac";
			reg = <0x42090000 0x400>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
		};

		risaf1: risaf@420a0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420a0000 0x1000>;
			clocks = <&rcc CK_BUS_BKPSRAM>;
			st,mem-map = <0x0 0x42000000 0x0 0x2000>;
			#access-controller-cells = <1>;
		};

		risaf2: risaf@420b0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420b0000 0x1000>;
			clocks = <&rcc CK_KER_OSPI1>;
			st,mem-map = <0x0 0x60000000 0x0 0x10000000>;
			#access-controller-cells = <1>;
			status = "disabled";
		};

		risaf4: risaf@420d0000 {
			compatible = "st,stm32mp25-risaf-enc";
			reg = <0x420d0000 0x1000>;
			clocks = <&rcc CK_BUS_RISAF4>;
			st,mem-map = <0x0 0x80000000 0x1 0x00000000>;
			#access-controller-cells = <1>;
		};

		risaf5: risaf@420e0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420e0000 0x1000>;
			clocks = <&rcc CK_BUS_PCIE>;
			st,mem-map = <0x0 0x10000000 0x0 0x10000000>;
			#access-controller-cells = <1>;
			status = "disabled";
		};

		risab1: risab@420f0000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x420f0000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa000000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab2: risab@42100000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42100000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa020000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab3: risab@42110000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42110000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa040000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab4: risab@42120000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42120000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa060000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab5: risab@42130000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42130000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa080000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab6: risab@42140000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42140000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa0a0000 0x20000>;
			#access-controller-cells = <1>;
			status = "disabled";
		};

		serc: serc@44080000 {
			compatible = "st,stm32mp25-serc";
			reg = <0x44080000 0x1000>;
			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc CK_BUS_SERC>;
		};

		rcc: rcc@44200000 {
			compatible = "st,stm32mp25-rcc", "syscon";
			reg = <0x44200000 0x10000>;
			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
			clock-names = "clk-hse", "clk-hsi", "clk-lse",
				      "clk-lsi", "clk-msi", "clk-i2sin";

			hsi_calibration: hsi-calibration {
				compatible = "st,hsi-cal";
				st,cal_hsi_dev = <31>;
				st,cal_hsi_ref = <1953>;
				status = "disabled";
			};

			msi_calibration: msi-calibration {
				compatible = "st,msi-cal";
				status = "disabled";
			};
		};

		exti1: interrupt-controller@44220000 {
			compatible = "st,stm32mp1-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x44220000 0x400>;
			interrupts-extended =
				<&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
				<&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
				<&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_20 */
				<&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
				<&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_40 */
				<&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_60 */
				<&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_70 */
				<0>,
				<&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_80 */
				<0>,
				<0>,
				<&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
		};

		syscfg: syscon@44230000 {
			reg = <0x44230000 0x10000>;
			status = "disabled";
		};

		pinctrl: pinctrl@44240000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-pinctrl";
			ranges = <0 0x44240000 0xa0400>;

			gpioa: gpio@44240000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x0 0x400>;
				clocks = <&rcc CK_BUS_GPIOA>;
				st,bank-name = "GPIOA";
				status = "disabled";
			};

			gpiob: gpio@44250000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x10000 0x400>;
				clocks = <&rcc CK_BUS_GPIOB>;
				st,bank-name = "GPIOB";
				status = "disabled";
			};

			gpioc: gpio@44260000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x20000 0x400>;
				clocks = <&rcc CK_BUS_GPIOC>;
				st,bank-name = "GPIOC";
				status = "disabled";
			};

			gpiod: gpio@44270000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x30000 0x400>;
				clocks = <&rcc CK_BUS_GPIOD>;
				st,bank-name = "GPIOD";
				status = "disabled";
			};

			gpioe: gpio@44280000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x40000 0x400>;
				clocks = <&rcc CK_BUS_GPIOE>;
				st,bank-name = "GPIOE";
				status = "disabled";
			};

			gpiof: gpio@44290000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x50000 0x400>;
				clocks = <&rcc CK_BUS_GPIOF>;
				st,bank-name = "GPIOF";
				status = "disabled";
			};

			gpiog: gpio@442a0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x60000 0x400>;
				clocks = <&rcc CK_BUS_GPIOG>;
				st,bank-name = "GPIOG";
				status = "disabled";
			};

			gpioh: gpio@442b0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x70000 0x400>;
				clocks = <&rcc CK_BUS_GPIOH>;
				st,bank-name = "GPIOH";
				status = "disabled";
			};

			gpioi: gpio@442c0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x80000 0x400>;
				clocks = <&rcc CK_BUS_GPIOI>;
				st,bank-name = "GPIOI";
				status = "disabled";
			};

			gpioj: gpio@442d0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0x90000 0x400>;
				clocks = <&rcc CK_BUS_GPIOJ>;
				st,bank-name = "GPIOJ";
				status = "disabled";
			};

			gpiok: gpio@442e0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0xa0000 0x400>;
				clocks = <&rcc CK_BUS_GPIOK>;
				st,bank-name = "GPIOK";
				status = "disabled";
			};
		};

		rtc: rtc@46000000 {
			compatible = "st,stm32mp25-rtc";
			reg = <0x46000000 0x400>;
			clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>;
			clock-names = "pclk", "rtc_ck";
			wakeup-source;
			interrupts-extended = <&exti2 22 IRQ_TYPE_EDGE_RISING>;
		};

		tamp: tamp@46010000 {
			compatible = "st,stm32mp25-tamp";
			reg = <0x46010000 0x400>;
			clocks = <&rcc CK_BUS_RTC>;
			interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			st,backup-zones = <24 24 24 24 12 12 8>;
		};

		pinctrl_z: pinctrl-z@46200000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-z-pinctrl";
			ranges = <0 0x46200000 0x400>;

			gpioz: gpio@46200000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				reg = <0 0x400>;
				clocks = <&rcc CK_BUS_GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				status = "disabled";
			};
		};

		exti2: interrupt-controller@46230000 {
			compatible = "st,stm32mp1-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x46230000 0x400>;
			interrupts-extended =
				<&intc GIC_SPI 17  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
				<&intc GIC_SPI 18  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 19  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 20  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 21  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 22  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 23  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 24  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 25  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 26  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 27  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
				<&intc GIC_SPI 28  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 29  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 30  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 31  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 32  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 12  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 13  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,						/* EXTI_20 */
				<&intc GIC_SPI 14  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 15  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
				<&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_40 */
				<0>,
				<0>,
				<&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 11  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 5   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 4   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 6   IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
				<&intc GIC_SPI 7   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 2   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 3   IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,						/* EXTI_60 */
				<&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;	/* EXTI_70 */
		};

		hsem: hwspinlock@46240000 {
			compatible = "st,stm32mp25-hsem";
			reg = <0x46240000 0x400>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc CK_BUS_HSEM>;
			status = "disabled";
		};

		ipcc2: mailbox@46250000 {
			compatible = "st,stm32mp25-ipcc";
			reg = <0x46250000 0x400>;
			clocks = <&rcc CK_BUS_IPCC2>;
			status = "disabled";
		};

		stgenc: stgen@48080000 {
			compatible = "st,stm32mp25-stgen";
			reg = <0x48080000 0x1000>;
			clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>;
			clock-names = "bus", "stgen_clk";
		};

		fmc: memory-controller@48200000 {
			compatible = "st,stm32mp25-fmc2-ebi";
			reg = <0x48200000 0x400>;
			ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */
				 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */
				 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */
				 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */
				 <4 0 0x48810000 0x00001000>; /* NAND */
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&rcc CK_KER_FMC>;
			resets = <&rcc FMC_R>;
			status = "disabled";
		};
	};
};