// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */

#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/firewall/stm32mp25-rif.h>
#include <dt-bindings/firewall/stm32mp25-rifsc.h>
#include <dt-bindings/firewall/stm32mp25-risaf.h>
#include <dt-bindings/firewall/stm32mp25-risab.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a35";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	intc: interrupt-controller@4ac00000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x4ac10000 0x0 0x1000>,
		      <0x0 0x4ac20000 0x0 0x2000>,
		      <0x0 0x4ac40000 0x0 0x2000>,
		      <0x0 0x4ac60000 0x0 0x2000>;
		#address-cells = <1>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_msi: clk-msi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};

		clk_i2sin: clk-i2sin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_rcbsec: clk-rcbsec {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges = <0x0 0x0 0x0 0x80000000>;

		hpdma1: dma-controller@40400000 {
			compatible = "st,stm32-dma3";
			reg = <0x40400000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA1>;
			resets = <&rcc HPDMA1_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		hpdma2: dma-controller@40410000 {
			compatible = "st,stm32-dma3";
			reg = <0x40410000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA2>;
			resets = <&rcc HPDMA2_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		hpdma3: dma-controller@40420000 {
			compatible = "st,stm32-dma3";
			reg = <0x40420000 0x1000>;
			clocks = <&rcc CK_BUS_HPDMA3>;
			resets = <&rcc HPDMA3_R>;
			#dma-cells = <4>;
			status = "disabled";
		};

		ipcc1: mailbox@40490000 {
			compatible = "st,stm32mp25-ipcc";
			reg = <0x40490000 0x400>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "rx";
			clocks = <&rcc CK_BUS_IPCC1>;
			status = "disabled";
		};

		rifsc: rifsc@42080000 {
			compatible = "st,stm32mp25-rifsc", "simple-bus";
			reg = <0x42080000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			#access-controller-cells = <1>;

			usart2: serial@400e0000 {
				compatible = "st,stm32h7-uart";
				reg = <0x400e0000 0x400>;
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_KER_USART2>;
				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
				status = "disabled";
			};

			rng: rng@42020000 {
				compatible = "st,stm32mp25-rng";
				reg = <0x42020000 0x400>;
				clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>;
				clock-names = "rng_clk", "rng_hclk";
				resets = <&rcc RNG_R>;
				access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>;
			};
		};

		iac: iac@42090000 {
			compatible = "st,stm32mp25-iac";
			reg = <0x42090000 0x400>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
		};

		risaf1: risaf@420a0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420a0000 0x1000>;
			clocks = <&rcc CK_BUS_BKPSRAM>;
			st,mem-map = <0x0 0x42000000 0x0 0x2000>;
		};

		risaf2: risaf@420b0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420b0000 0x1000>;
			clocks = <&rcc CK_KER_OSPI1>;
			st,mem-map = <0x0 0x60000000 0x0 0x10000000>;
			status = "disabled";
		};

		risaf4: risaf@420d0000 {
			compatible = "st,stm32mp25-risaf-enc";
			reg = <0x420d0000 0x1000>;
			clocks = <&rcc CK_BUS_RISAF4>;
			st,mem-map = <0x0 0x80000000 0x1 0x00000000>;
		};

		risaf5: risaf@420e0000 {
			compatible = "st,stm32mp25-risaf";
			reg = <0x420e0000 0x1000>;
			clocks = <&rcc CK_BUS_PCIE>;
			st,mem-map = <0x0 0x10000000 0x0 0x10000000>;
			status = "disabled";
		};

		risab1: risab@420f0000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x420f0000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa000000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab2: risab@42100000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42100000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa020000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab3: risab@42110000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42110000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa040000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab4: risab@42120000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42120000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa060000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab5: risab@42130000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42130000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa080000 0x20000>;
			#access-controller-cells = <1>;
		};

		risab6: risab@42140000 {
			compatible = "st,stm32mp25-risab";
			reg = <0x42140000 0x1000>;
			clocks = <&rcc CK_ICN_LS_MCU>;
			st,mem-map = <0xa0a0000 0x20000>;
			#access-controller-cells = <1>;
			status = "disabled";
		};

		serc: serc@44080000 {
			compatible = "st,stm32mp25-serc";
			reg = <0x44080000 0x1000>;
			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc CK_BUS_SERC>;
		};

		rcc: rcc@44200000 {
			compatible = "st,stm32mp25-rcc", "syscon";
			reg = <0x44200000 0x10000>;
			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
			clock-names = "clk-hse", "clk-hsi", "clk-lse",
				      "clk-lsi", "clk-msi", "clk-i2sin";

			hsi_calibration: hsi-calibration {
				compatible = "st,hsi-cal";
				st,cal_hsi_dev = <31>;
				st,cal_hsi_ref = <1953>;
				status = "disabled";
			};

			msi_calibration: msi-calibration {
				compatible = "st,msi-cal";
				status = "disabled";
			};
		};

		pinctrl: pinctrl@44240000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-pinctrl";
			ranges = <0 0x44240000 0xa0400>;
			pins-are-numbered;

			gpioa: gpio@44240000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc CK_BUS_GPIOA>;
				st,bank-name = "GPIOA";
				status = "disabled";
			};

			gpiob: gpio@44250000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x10000 0x400>;
				clocks = <&rcc CK_BUS_GPIOB>;
				st,bank-name = "GPIOB";
				status = "disabled";
			};

			gpioc: gpio@44260000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x20000 0x400>;
				clocks = <&rcc CK_BUS_GPIOC>;
				st,bank-name = "GPIOC";
				status = "disabled";
			};

			gpiod: gpio@44270000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x30000 0x400>;
				clocks = <&rcc CK_BUS_GPIOD>;
				st,bank-name = "GPIOD";
				status = "disabled";
			};

			gpioe: gpio@44280000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x40000 0x400>;
				clocks = <&rcc CK_BUS_GPIOE>;
				st,bank-name = "GPIOE";
				status = "disabled";
			};

			gpiof: gpio@44290000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x50000 0x400>;
				clocks = <&rcc CK_BUS_GPIOF>;
				st,bank-name = "GPIOF";
				status = "disabled";
			};

			gpiog: gpio@442a0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x60000 0x400>;
				clocks = <&rcc CK_BUS_GPIOG>;
				st,bank-name = "GPIOG";
				status = "disabled";
			};

			gpioh: gpio@442b0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x70000 0x400>;
				clocks = <&rcc CK_BUS_GPIOH>;
				st,bank-name = "GPIOH";
				status = "disabled";
			};

			gpioi: gpio@442c0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x80000 0x400>;
				clocks = <&rcc CK_BUS_GPIOI>;
				st,bank-name = "GPIOI";
				status = "disabled";
			};

			gpioj: gpio@442d0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x90000 0x400>;
				clocks = <&rcc CK_BUS_GPIOJ>;
				st,bank-name = "GPIOJ";
				status = "disabled";
			};

			gpiok: gpio@442e0000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xa0000 0x400>;
				clocks = <&rcc CK_BUS_GPIOK>;
				st,bank-name = "GPIOK";
				status = "disabled";
			};
		};

		tamp: tamp@46010000 {
			compatible = "st,stm32mp25-tamp";
			reg = <0x46010000 0x400>;
			clocks = <&rcc CK_BUS_RTC>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			st,backup-zones = <24 24 24 24 12 12 8>;
		};

		pinctrl_z: pinctrl-z@46200000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp257-z-pinctrl";
			ranges = <0 0x46200000 0x400>;
			pins-are-numbered;

			gpioz: gpio@46200000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x400>;
				clocks = <&rcc CK_BUS_GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				status = "disabled";
			};
		};

		hsem: hwspinlock@46240000 {
			compatible = "st,stm32mp25-hsem";
			reg = <0x46240000 0x400>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc CK_BUS_HSEM>;
			status = "disabled";
		};

		ipcc2: mailbox@46250000 {
			compatible = "st,stm32mp25-ipcc";
			reg = <0x46250000 0x400>;
			clocks = <&rcc CK_BUS_IPCC2>;
			status = "disabled";
		};

		fmc: memory-controller@48200000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "st,stm32mp25-fmc2-ebi";
			reg = <0x48200000 0x400>;
			clocks = <&rcc CK_KER_FMC>;
			resets = <&rcc FMC_R>;
			status = "disabled";

			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
				 <4 0 0x80000000 0x10000000>; /* NAND */
		};
	};
};