// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2021-2025 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */

#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/clock/stm32mp13-clksrc.h>
#include <dt-bindings/firewall/stm32mp13-etzpc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include <dt-bindings/reset/stm32mp13-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clocks = <&rcc CK_MPU>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu0_opp_table>;
			nvmem-cells = <&part_number_otp>;
			nvmem-cell-names = "part_number";
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";

		/* Non‑overdrive OPP mission profile */
		opp-650000000 {
			opp-hz = /bits/ 64 <650000000>;
			opp-microvolt = <1250000>;
			opp-supported-hw = <0x3>;
			st,opp-default;
		};

		/* Overdrive OPP: 10‑year life activity @100% activity rate */
		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <1350000>;
			opp-supported-hw = <0x2>;
			st,opp-default;
		};

		/* Overdrive OPP: 10‑year life activity @25% activity rate */
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1350000>;
			opp-supported-hw = <0x2>;
		};
	};

	hse_monitor: hse-monitor {
		compatible = "st,freq-monitor";
		counter = <&lptimer3 1 1 0 0>;
		status = "disabled";
	};

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};

		clk_i2sin: clk-i2sin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <19000000>;
		};

	};

	sdmmc1_io: sdmmc1_io {
		compatible = "st,stm32mp13-iod";
		regulator-name = "sdmmc1_io";
		regulator-always-on;
	};

	sdmmc2_io: sdmmc2_io {
		compatible = "st,stm32mp13-iod";
		regulator-name = "sdmmc2_io";
		regulator-always-on;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		usart3: serial@4000f000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000f000 0x400>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART3_K>;
			resets = <&rcc USART3_R>;
			status = "disabled";
		};

		uart4: serial@40010000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40010000 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART4_K>;
			resets = <&rcc UART4_R>;
			status = "disabled";
		};

		uart5: serial@40011000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART5_K>;
			resets = <&rcc UART5_R>;
			status = "disabled";
		};

		i2c1: i2c@40012000 {
			compatible = "st,stm32mp13-i2c";
			reg = <0x40012000 0x400>;
			clocks = <&rcc I2C1_K>;
			resets = <&rcc I2C1_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x1>;
			i2c-analog-filter;
			status = "disabled";
		};

		i2c2: i2c@40013000 {
			compatible = "st,stm32mp13-i2c";
			reg = <0x40013000 0x400>;
			clocks = <&rcc I2C2_K>;
			resets = <&rcc I2C2_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x2>;
			i2c-analog-filter;
			status = "disabled";
		};

		uart7: serial@40018000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40018000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART7_K>;
			resets = <&rcc UART7_R>;
			status = "disabled";
		};

		uart8: serial@40019000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40019000 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART8_K>;
			resets = <&rcc UART8_R>;
			status = "disabled";
		};

		usart6: serial@44003000 {
			compatible = "st,stm32h7-uart";
			reg = <0x44003000 0x400>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART6_K>;
			resets = <&rcc USART6_R>;
			status = "disabled";
		};

		rcc: rcc@50000000 {
			compatible = "st,stm32mp13-rcc", "syscon";
			reg = <0x50000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>;
			clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin";
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupt-names = "wakeup";
		};

		pwr_regulators: pwr@50001000 {
			compatible = "st,stm32mp1-pwr-reg";
			reg = <0x50001000 0x10>;

			reg11: reg11 {
				regulator-name = "reg11";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
			};

			reg18: reg18 {
				regulator-name = "reg18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			usb33: usb33 {
				regulator-name = "usb33";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};

		pwr_irq: pwr@50001010 {
			compatible = "st,stm32mp1,pwr-irq";
			status = "disabled";
		};

		exti: interrupt-controller@5000d000 {
			compatible = "st,stm32mp1-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x5000d000 0x400>;
			interrupts-extended =
				<&intc GIC_SPI 6   IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
				<&intc GIC_SPI 7   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 8   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 9   IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 24  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 65  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 66  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 67  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 68  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 41  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
				<&intc GIC_SPI 43  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 77  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 78  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 3   IRQ_TYPE_LEVEL_HIGH>,
				<0>,						/* EXTI_20 */
				<&intc GIC_SPI 32  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 34  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 73  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 93  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 38  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 39  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 40  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 72  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 53  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
				<&intc GIC_SPI 54  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 83  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 84  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,						/* EXTI_40 */
				<0>,
				<&intc GIC_SPI 75  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 75  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 96  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<&intc GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
				<0>,
				<&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,						/* EXTI_60 */
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<0>,
				<&intc GIC_SPI 63  IRQ_TYPE_LEVEL_HIGH>,
				<0>,
				<&intc GIC_SPI 98  IRQ_TYPE_LEVEL_HIGH>;	/* EXTI_70 */
		};

		syscfg: syscon@50020000 {
			compatible = "st,stm32mp157-syscfg", "syscon";
			reg = <0x50020000 0x400>;
		};

		iwdg2: watchdog@5a002000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5a002000 0x400>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		rtc: rtc@5c004000 {
			compatible = "st,stm32mp13-rtc";
			reg = <0x5c004000 0x400>;
			clocks = <&rcc RTCAPB>, <&rcc RTC>;
			clock-names = "pclk", "rtc_ck";
			status = "disabled";
		};

		bsec: efuse@5c005000 {
			compatible = "st,stm32mp13-bsec";
			reg = <0x5c005000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;

			cfg0_otp: cfg0_otp@0 {
				reg = <0x0 0x2>;
			};
			part_number_otp: part_number_otp@4 {
				reg = <0x4 0x2>;
				bits = <0 12>;
			};
			monotonic_otp: monotonic_otp@10 {
				reg = <0x10 0x4>;
			};
			nand_otp: cfg9_otp@24 {
				reg = <0x24 0x4>;
			};
			uid_otp: uid_otp@34 {
				reg = <0x34 0xc>;
			};
			hw2_otp: hw2_otp@48 {
				reg = <0x48 0x4>;
			};
			ts_cal1: calib@5c {
				reg = <0x5c 0x2>;
			};
			ts_cal2: calib@5e {
				reg = <0x5e 0x2>;
			};
			pkh_otp: pkh_otp@60 {
				reg = <0x60 0x20>;
			};
			ethernet_mac1_address: mac1@e4 {
				reg = <0xe4 0xc>;
				st,non-secure-otp;
			};
			oem_enc_key: oem_enc_key@170 {
				reg = <0x170 0x10>;
			};
		};

		tzc400: tzc@5c006000 {
			compatible = "st,stm32mp1-tzc";
			reg = <0x5c006000 0x1000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			st,mem-map = <0xc0000000 0x40000000>;
			clocks = <&rcc TZC>;
		};

		tamp: tamp@5c00a000 {
			compatible = "st,stm32mp13-tamp";
			reg = <0x5c00a000 0x400>;
			interrupts-extended = <&exti 18 IRQ_TYPE_EDGE_RISING>;
			clocks = <&rcc RTCAPB>;
			st,backup-zones = <10 5 17>;
		};

		pinctrl: pin-controller@50002000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp135-pinctrl";
			ranges = <0 0x50002000 0x8400>;

			gpioa: gpio@50002000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOA>;
				reg = <0x0 0x400>;
				st,bank-name = "GPIOA";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 0 16>;
			};

			gpiob: gpio@50003000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOB>;
				reg = <0x1000 0x400>;
				st,bank-name = "GPIOB";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 16 16>;
			};

			gpioc: gpio@50004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOC>;
				reg = <0x2000 0x400>;
				st,bank-name = "GPIOC";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 32 16>;
			};

			gpiod: gpio@50005000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOD>;
				reg = <0x3000 0x400>;
				st,bank-name = "GPIOD";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 48 16>;
			};

			gpioe: gpio@50006000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOE>;
				reg = <0x4000 0x400>;
				st,bank-name = "GPIOE";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 64 16>;
			};

			gpiof: gpio@50007000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOF>;
				reg = <0x5000 0x400>;
				st,bank-name = "GPIOF";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 80 16>;
			};

			gpiog: gpio@50008000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOG>;
				reg = <0x6000 0x400>;
				st,bank-name = "GPIOG";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 96 16>;
			};

			gpioh: gpio@50009000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOH>;
				reg = <0x7000 0x400>;
				st,bank-name = "GPIOH";
				ngpios = <15>;
				gpio-ranges = <&pinctrl 0 112 15>;
			};

			gpioi: gpio@5000a000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#access-controller-cells = <1>;
				clocks = <&rcc GPIOI>;
				reg = <0x8000 0x400>;
				st,bank-name = "GPIOI";
				ngpios = <8>;
				gpio-ranges = <&pinctrl 0 128 8>;
			};
		};

		etzpc: etzpc@5c007000 {
			compatible = "st,stm32-etzpc", "simple-bus";
			reg = <0x5C007000 0x400>;
			clocks = <&rcc TZPC>;
			#address-cells = <1>;
			#size-cells = <1>;
			#access-controller-cells = <1>;

			adc_2: adc@48004000 {
				reg = <0x48004000 0x400>;
				compatible = "st,stm32mp13-adc-core";
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
				clock-names = "bus", "adc";
				interrupt-controller;
				#interrupt-cells = <1>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>;
				status = "disabled";

				adc2: adc@0 {
					compatible = "st,stm32mp13-adc";
					reg = <0x0>;
					#io-channel-cells = <1>;
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&adc_2>;
					interrupts = <0>;
					status = "disabled";

					channel@13 {
						reg = <13>;
						label = "vrefint";
					};

					channel@14 {
						reg = <14>;
						label = "vddcore";
					};

					channel@16 {
						reg = <16>;
						label = "vddcpu";
					};

					channel@17 {
						reg = <17>;
						label = "vddq_ddr";
					};
				};
			};

			usart1: serial@4c000000 {
				compatible = "st,stm32h7-uart";
				reg = <0x4c000000 0x400>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc USART1_K>;
				resets = <&rcc USART1_R>;
				access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>;
				status = "disabled";
			};

			usart2: serial@4c001000 {
				compatible = "st,stm32h7-uart";
				reg = <0x4c001000 0x400>;
				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc USART2_K>;
				resets = <&rcc USART2_R>;
				access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>;
				status = "disabled";
			};

			i2c3: i2c@4c004000 {
				compatible = "st,stm32mp13-i2c";
				reg = <0x4c004000 0x400>;
				clocks = <&rcc I2C3_K>;
				resets = <&rcc I2C3_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				st,syscfg-fmp = <&syscfg 0x4 0x4>;
				i2c-analog-filter;
				access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>;
				status = "disabled";
			};

			i2c4: i2c@4c005000 {
				compatible = "st,stm32mp13-i2c";
				reg = <0x4c005000 0x400>;
				clocks = <&rcc I2C4_K>;
				resets = <&rcc I2C4_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				st,syscfg-fmp = <&syscfg 0x4 0x8>;
				i2c-analog-filter;
				access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>;
				status = "disabled";
			};

			i2c5: i2c@4c006000 {
				compatible = "st,stm32mp13-i2c";
				reg = <0x4c006000 0x400>;
				clocks = <&rcc I2C5_K>;
				resets = <&rcc I2C5_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				st,syscfg-fmp = <&syscfg 0x4 0x10>;
				i2c-analog-filter;
				access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>;
				status = "disabled";
			};

			timers12: timer@4c007000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c007000 0x400>;
				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc TIM12_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>;
				status = "disabled";

				counter {
					compatible = "st,stm32-timer-counter";
					status = "disabled";
				};
			};

			timers13: timer@4c008000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c008000 0x400>;
				clocks = <&rcc TIM13_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>;
				status = "disabled";
			};

			timers14: timer@4c009000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c009000 0x400>;
				clocks = <&rcc TIM14_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>;
				status = "disabled";
			};

			timers15: timer@4c00a000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c00a000 0x400>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc TIM15_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>;
				status = "disabled";

				counter {
					compatible = "st,stm32-timer-counter";
					status = "disabled";
				};
			};

			timers16: timer@4c00b000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c00b000 0x400>;
				clocks = <&rcc TIM16_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>;
				status = "disabled";
			};

			timers17: timer@4c00c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-timers";
				reg = <0x4c00c000 0x400>;
				clocks = <&rcc TIM17_K>;
				clock-names = "int";
				access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>;
				status = "disabled";
			};

			lptimer2: timer@50021000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-lptimer";
				reg = <0x50021000 0x400>;
				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc LPTIM2_K>;
				clock-names = "mux";
				access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>;
				status = "disabled";
			};

			lptimer3: timer@50022000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32-lptimer";
				reg = <0x50022000 0x400>;
				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc LPTIM3_K>;
				clock-names = "mux";
				access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>;
				status = "disabled";

				counter {
					compatible = "st,stm32-lptimer-counter";
					status = "disabled";
				};
			};

			vrefbuf: vrefbuf@50025000 {
				compatible = "st,stm32mp13-vrefbuf";
				reg = <0x50025000 0x8>;
				regulator-name = "vrefbuf";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <2500000>;
				clocks = <&rcc VREF>;
				access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>;
				status = "disabled";
			};

			hash: hash@54003000 {
				compatible = "st,stm32mp13-hash";
				reg = <0x54003000 0x400>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc HASH1>;
				resets = <&rcc HASH1_R>;
				access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>;
				status = "disabled";
			};

			rng: rng@54004000 {
				compatible = "st,stm32mp13-rng";
				reg = <0x54004000 0x400>;
				clocks = <&rcc RNG1_K>;
				resets = <&rcc RNG1_R>;
				access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>;
				status = "disabled";
			};

			iwdg1: watchdog@5c003000 {
				compatible = "st,stm32mp1-iwdg";
				reg = <0x5C003000 0x400>;
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
				clock-names = "pclk", "lsi";
				access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>;
				status = "disabled";
			};

			stgen: stgen@5c008000 {
				compatible = "st,stm32-stgen";
				reg = <0x5C008000 0x1000>;
				access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>;
			};
		};
	};
};