Lines Matching refs:__u32
156 typedef __u32 uclong; /* 32 bits, unsigned */
176 __u32 fpga_id; /* FPGA Identification Register */
177 __u32 fpga_version; /* FPGA Version Number Register */
178 __u32 cpu_start; /* CPU start Register (write) */
179 __u32 cpu_stop; /* CPU stop Register (write) */
180 __u32 misc_reg; /* Miscellaneous Register */
181 __u32 idt_mode; /* IDT mode Register */
182 __u32 uart_irq_status; /* UART IRQ status Register */
183 __u32 clear_timer0_irq; /* Clear timer interrupt Register */
184 __u32 clear_timer1_irq; /* Clear timer interrupt Register */
185 __u32 clear_timer2_irq; /* Clear timer interrupt Register */
186 __u32 test_register; /* Test Register */
187 __u32 test_count; /* Test Count Register */
188 __u32 timer_select; /* Timer select register */
189 __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
190 __u32 ram_wait_state; /* RAM wait-state Register */
191 __u32 uart_wait_state; /* UART wait-state Register */
192 __u32 timer_wait_state; /* timer wait-state Register */
193 __u32 ack_wait_state; /* ACK wait State Register */
203 __u32 loc_addr_range; /* 00h - Local Address Range */
204 __u32 loc_addr_base; /* 04h - Local Address Base */
205 __u32 loc_arbitr; /* 08h - Local Arbitration */
206 __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */
207 __u32 loc_rom_range; /* 10h - Local ROM Range */
208 __u32 loc_rom_base; /* 14h - Local ROM Base */
209 __u32 loc_bus_descr; /* 18h - Local Bus descriptor */
210 __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */
211 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */
212 __u32 loc_range_io; /* 24h - Local Range for Master IO */
213 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */
214 __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */
215 __u32 filler1; /* 30h */
216 __u32 filler2; /* 34h */
217 __u32 filler3; /* 38h */
218 __u32 filler4; /* 3Ch */
219 __u32 mail_box_0; /* 40h - Mail Box 0 */
220 __u32 mail_box_1; /* 44h - Mail Box 1 */
221 __u32 mail_box_2; /* 48h - Mail Box 2 */
222 __u32 mail_box_3; /* 4Ch - Mail Box 3 */
223 __u32 filler5; /* 50h */
224 __u32 filler6; /* 54h */
225 __u32 filler7; /* 58h */
226 __u32 filler8; /* 5Ch */
227 __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */
228 __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */
229 __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */
230 __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
272 __u32 signature; /* ZFIRM/U signature */
273 __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */
410 __u32 op_mode; /* operation mode */
411 __u32 intr_enable; /* interrupt masking */
412 __u32 sw_flow; /* SW flow control */
413 __u32 flow_status; /* output flow status */
414 __u32 comm_baud; /* baud rate - numerically specified */
415 __u32 comm_parity; /* parity */
416 __u32 comm_data_l; /* data length/stop */
417 __u32 comm_flags; /* other flags */
418 __u32 hw_flow; /* HW flow control */
419 __u32 rs_control; /* RS-232 outputs */
420 __u32 rs_status; /* RS-232 inputs */
421 __u32 flow_xon; /* xon char */
422 __u32 flow_xoff; /* xoff char */
423 __u32 hw_overflow; /* hw overflow counter */
424 __u32 sw_overflow; /* sw overflow counter */
425 __u32 comm_error; /* frame/parity error counter */
426 __u32 ichar;
427 __u32 filler[7];
437 __u32 flag_dma; /* buffers are in Host memory */
438 __u32 tx_bufaddr; /* address of the tx buffer */
439 __u32 tx_bufsize; /* tx buffer size */
440 __u32 tx_threshold; /* tx low water mark */
441 __u32 tx_get; /* tail index tx buf */
442 __u32 tx_put; /* head index tx buf */
443 __u32 rx_bufaddr; /* address of the rx buffer */
444 __u32 rx_bufsize; /* rx buffer size */
445 __u32 rx_threshold; /* rx high water mark */
446 __u32 rx_get; /* tail index rx buf */
447 __u32 rx_put; /* head index rx buf */
448 __u32 filler[5]; /* filler to align structures */
459 __u32 n_channel; /* number of channels */
460 __u32 fw_version; /* firmware version */
463 __u32 op_system; /* op_system id */
464 __u32 dr_version; /* driver version */
467 __u32 inactivity; /* inactivity control */
470 __u32 hcmd_channel; /* channel number */
471 __u32 hcmd_param; /* pointer to parameters */
474 __u32 fwcmd_channel; /* channel number */
475 __u32 fwcmd_param; /* pointer to parameters */
476 __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */
479 __u32 filler[6];