Lines Matching refs:E_INT_FIQ_0x60_START

31383     E_INT_FIQ_0x60_START = 0x60,
31384     E_INT_FIQ_IR_INT_RC = E_INT_FIQ_0x60_START+0,
31385     E_INT_FIQ_HDMITX_IRQ_EDGE = E_INT_FIQ_0x60_START+1,
31386     E_INT_FIQ_UP_IRQ_UART_CA = E_INT_FIQ_0x60_START+2,
31387     E_INT_FIQ_UP_IRQ_EMM_ECM = E_INT_FIQ_0x60_START+3,
31388     E_INT_FIQ_PVR2MI_INT0 = E_INT_FIQ_0x60_START+4,
31389     E_INT_IRQ_CA_RSA_INT0 = E_INT_FIQ_0x60_START+4,
31390     E_INT_FIQ_PVR2MI_INT1 = E_INT_FIQ_0x60_START+5,
31391     E_INT_IRQ_FIQ_INT = E_INT_FIQ_0x60_START+6,
31392     E_INT_IRQ_UART3 = E_INT_FIQ_0x60_START+7,
31393     E_INT_FIQ_AEON_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+8,
31394     E_INT_FIQ_AEON_TO_MIPS_VPE1 = E_INT_FIQ_0x60_START+9,
31395     E_INT_FIQ_SECEMAC = E_INT_FIQ_0x60_START+10,
31396     E_INT_FIQ_IR2_INT = E_INT_FIQ_0x60_START+11,
31397     E_INT_FIQ_MIPS_VPE1_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+12,
31398     E_INT_FIQ_MIPS_VPE1_TO_AEON = E_INT_FIQ_0x60_START+13,
31399     E_INT_FIQ_MIPS_VPE1_TO_8051 = E_INT_FIQ_0x60_START+14,
31400     E_INT_FIQ_IR2_INT_RC = E_INT_FIQ_0x60_START+15,