Lines Matching refs:E_INT_FIQ_0xC0_START
364 E_INT_FIQ_0xC0_START = 0xC0, enumerator
365 E_INT_FIQ_DMARD = E_INT_FIQ_0xC0_START+0, //U3
366 E_INT_FIQ_AU_DMA_BUF_INT = E_INT_FIQ_0xC0_START+1, //T3
367 E_INT_FIQ_8051_TO_MIPS_VPE1 = E_INT_FIQ_0xC0_START+2, //T3
368 E_INT_FIQ_DVI_DET = E_INT_FIQ_0xC0_START+3, //M10
369 E_INT_FIQ_PM_GPIO0 = E_INT_FIQ_0xC0_START+4, //M10
370 E_INT_FIQ_PM_GPIO1 = E_INT_FIQ_0xC0_START+5, //M10
371 E_INT_FIQ_PM_GPIO2 = E_INT_FIQ_0xC0_START+6, //M10
372 E_INT_FIQ_PM_GPIO3 = E_INT_FIQ_0xC0_START+7, //M10
373 E_INT_FIQ_PM_XIU_TIMEOUT = E_INT_FIQ_0xC0_START+8, //M10
374 E_INT_FIQ_PWM_RP_RP_L = E_INT_FIQ_0xC0_START+9, //M10
375 E_INT_FIQ_PWM_RP_FP_L = E_INT_FIQ_0xC0_START+10, //M10
376 E_INT_FIQ_PWM_RP_RP_R = E_INT_FIQ_0xC0_START+11, //M10
377 E_INT_FIQ_PWM_RP_FP_R = E_INT_FIQ_0xC0_START+12, //M10
378 E_INT_FIQ_8051_TO_MIPS_VPE0 = E_INT_FIQ_0xC0_START+13, //A5
379 E_INT_FIQ_FRC_R2_TO_MIPS = E_INT_FIQ_0xC0_START+14,
380 E_INT_FIQ_VP6 = E_INT_FIQ_0xC0_START+15, //A3