Lines Matching refs:HAL_UpdateIrqTable
416 static void HAL_UpdateIrqTable(MS_U32 dwHardwareIndex, MS_U32 dwSoftwareIndex) in HAL_UpdateIrqTable() function
444 HAL_UpdateIrqTable(E_IRQ_00, E_INT_IRQ_UART0); //int_uart0 in HAL_InitIrqTable()
445 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_PMSLEEP); //pm_sleep_int in HAL_InitIrqTable()
446 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_VD_EVD_R22HI_INT);//irq_vd_evd_r22hi (*) in HAL_InitIrqTable()
447 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int in HAL_InitIrqTable()
448 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_PS); //ps_int in HAL_InitIrqTable()
449 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_NFIE); //nfie_int in HAL_InitIrqTable()
450 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_USB); //usb_int in HAL_InitIrqTable()
451 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_UHC); //uhc_int in HAL_InitIrqTable()
452 HAL_UpdateIrqTable(E_IRQ_08, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
453 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_EMAC); //emac_int in HAL_InitIrqTable()
454 HAL_UpdateIrqTable(E_IRQ_10, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
455 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_MSPI0); //mspi_int in HAL_InitIrqTable()
456 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_GE); //ge_int in HAL_InitIrqTable()
457 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int in HAL_InitIrqTable()
458 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_COMB); //comb_int / vbi_int in HAL_InitIrqTable()
459 HAL_UpdateIrqTable(E_IRQ_15, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
461 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int in HAL_InitIrqTable()
462 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_CEC); //cec_int_pm in HAL_InitIrqTable()
463 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_DISP); //disp_int in HAL_InitIrqTable()
464 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int in HAL_InitIrqTable()
465 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int in HAL_InitIrqTable()
466 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_SCDC_PM_INT); //scdc_int_pm (*) in HAL_InitIrqTable()
467 HAL_UpdateIrqTable(E_IRQ_22, E_INT_IRQ_SMART); //smart card int in HAL_InitIrqTable()
468 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_DDC2BI); //d2b_int in HAL_InitIrqTable()
469 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_AUDMA_V2_INT); //AUDMA_V2_INTR in HAL_InitIrqTable()
470 HAL_UpdateIrqTable(E_IRQ_25, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
471 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_EMMC_OSP_INT); //emmc_osp_int in HAL_InitIrqTable()
472 HAL_UpdateIrqTable(E_IRQ_27, E_INT_IRQ_SCM); //scm_int in HAL_InitIrqTable()
473 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_VBI); //vbi_int in HAL_InitIrqTable()
474 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_MVD2MIPS); //mvd2mips_int in HAL_InitIrqTable()
475 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_GPD); //gpd_int in HAL_InitIrqTable()
476 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int in HAL_InitIrqTable()
478 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_SVD_HVD); //hvd_int in HAL_InitIrqTable()
479 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB1); //usb_int1 in HAL_InitIrqTable()
480 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC1); //uhc_int1 in HAL_InitIrqTable()
481 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_ERROR_RESP); //error_resp_int in HAL_InitIrqTable()
482 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_USB2); //usb_int2 in HAL_InitIrqTable()
483 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_UHC2); //uhc_int2 in HAL_InitIrqTable()
484 HAL_UpdateIrqTable(E_IRQ_38, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
485 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1 in HAL_InitIrqTable()
486 HAL_UpdateIrqTable(E_IRQ_40, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
487 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_MSPI1); //mspi1_int in HAL_InitIrqTable()
488 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_MIU_SECURITY); //miu_security_int in HAL_InitIrqTable()
489 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_DIPW); //dipw_INT in HAL_InitIrqTable()
490 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_MIIC_INT2); //miic2_int in HAL_InitIrqTable()
491 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_JPD); //jpd_int in HAL_InitIrqTable()
492 HAL_UpdateIrqTable(E_IRQ_46, E_INT_RESERVED); //pm_irq_out (*) in HAL_InitIrqTable()
493 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_MFE); //mfe_int in HAL_InitIrqTable()
495 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA); //int_bdma_merge in HAL_InitIrqTable()
496 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_PAS_PTS_COMBINE_INT); //PAS_PTS_INTRL_COMBINE in HAL_InitIrqTable()
497 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr in HAL_InitIrqTable()
498 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr in HAL_InitIrqTable()
499 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_DVI_HDMI_HDCP); //dvi_hdmi_hdcp_int in HAL_InitIrqTable()
500 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_G3D2MCU); //g3d2mcu_irq_dft in HAL_InitIrqTable()
501 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_PCM); //pcm2mcu_int in HAL_InitIrqTable()
502 HAL_UpdateIrqTable(E_IRQ_55, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
503 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int in HAL_InitIrqTable()
504 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_WADR_ERR); //wadr_err_int in HAL_InitIrqTable()
505 HAL_UpdateIrqTable(E_IRQ_58, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
506 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_SDIO); //sdio_int in HAL_InitIrqTable()
507 HAL_UpdateIrqTable(E_IRQ_60, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
508 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_MIIC_DMA1); //miic1_dma_int in HAL_InitIrqTable()
509 HAL_UpdateIrqTable(E_IRQ_62, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
510 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_MIIC_DMA0); //miic0_dma_int in HAL_InitIrqTable()
512 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0 in HAL_InitIrqTable()
513 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1 in HAL_InitIrqTable()
514 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt in HAL_InitIrqTable()
515 HAL_UpdateIrqTable(E_FIQ_03, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
516 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_AU_SPDIF_TX_CS0);//AU_SPDIF_TX_CS_INT[0] in HAL_InitIrqTable()
517 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_AU_SPDIF_TX_CS1);//AU_SPDIF_TX_CS_INT[1] in HAL_InitIrqTable()
518 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0] in HAL_InitIrqTable()
519 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1] in HAL_InitIrqTable()
520 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_USB); //usb_int in HAL_InitIrqTable()
521 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UHC); //uhc_int in HAL_InitIrqTable()
522 HAL_UpdateIrqTable(E_FIQ_10, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
523 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT in HAL_InitIrqTable()
524 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM);//SPDIF_IN_NON_PCM_INT_OUT in HAL_InitIrqTable()
525 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_EMAC); //lan_esd_int in HAL_InitIrqTable()
526 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr in HAL_InitIrqTable()
527 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int in HAL_InitIrqTable()
529 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr in HAL_InitIrqTable()
530 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr in HAL_InitIrqTable()
531 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr in HAL_InitIrqTable()
532 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int in HAL_InitIrqTable()
533 HAL_UpdateIrqTable(E_FIQ_20, E_INT_FIQ_DMDMCU2HK); //dmdmcu2hk_int in HAL_InitIrqTable()
534 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_IR_IN); //ir_in in HAL_InitIrqTable()
535 HAL_UpdateIrqTable(E_FIQ_22, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
536 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_VDMCU2HK); //vdmcu2hk_int in HAL_InitIrqTable()
537 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_LDM_DMA0); //ldm_dma_done_int0 in HAL_InitIrqTable()
538 HAL_UpdateIrqTable(E_FIQ_25, E_INT_FIQ_LDM_DMA1); //ldm_dma_done_int1 in HAL_InitIrqTable()
539 HAL_UpdateIrqTable(E_FIQ_26, E_INT_FIQ_PM_SD_CDZ0); //PM_SD_CDZ_int in HAL_InitIrqTable()
540 HAL_UpdateIrqTable(E_FIQ_27, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
541 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AFEC_VSYNC); //AFEC_VSYNC in HAL_InitIrqTable()
542 HAL_UpdateIrqTable(E_FIQ_29, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
543 HAL_UpdateIrqTable(E_FIQ_30, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
544 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT in HAL_InitIrqTable()
546 HAL_UpdateIrqTable(E_FIQ_32, E_INT_RESERVED); //Reserved in HAL_InitIrqTable()
547 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE in HAL_InitIrqTable()
548 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_IR); //ir_int_rc | ir_int in HAL_InitIrqTable()
549 HAL_UpdateIrqTable(E_FIQ_35, E_INT_FIQ_PM_SD_CDZ1); //PM_SD_CDZ1_int in HAL_InitIrqTable()
550 HAL_UpdateIrqTable(E_FIQ_36, E_INT_FIQ_8051_TO_AEON); //reg_hst0to3_int in HAL_InitIrqTable()
551 HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_MIPS_VPE1); //reg_hst0to2_int in HAL_InitIrqTable()
552 HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_BEON); //reg_hst0to1_int in HAL_InitIrqTable()
553 HAL_UpdateIrqTable(E_FIQ_39, E_INT_FIQ_GPIO0); //ext_gpio_int[0] in HAL_InitIrqTable()
554 HAL_UpdateIrqTable(E_FIQ_40, E_INT_FIQ_BEON_TO_AEON); //reg_hst1to3_int in HAL_InitIrqTable()
555 HAL_UpdateIrqTable(E_FIQ_41, E_INT_RESERVED); //ca9_SCUEVABORT_INTR (*) in HAL_InitIrqTable()
556 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_BEON_TO_8051); //reg_hst1to0_int in HAL_InitIrqTable()
557 HAL_UpdateIrqTable(E_FIQ_43, E_INT_FIQ_GPIO1); //ext_gpio_int[1] in HAL_InitIrqTable()
558 HAL_UpdateIrqTable(E_FIQ_44, E_INT_FIQ_MIPS_VPE1_TO_AEON); //reg_hst2to3_int in HAL_InitIrqTable()
559 HAL_UpdateIrqTable(E_FIQ_45, E_INT_IRQ_TIMER2); //int_timer2 in HAL_InitIrqTable()
560 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_MIPS_VPE1_TO_8051); //reg_hst2to0_int in HAL_InitIrqTable()
561 HAL_UpdateIrqTable(E_FIQ_47, E_INT_FIQ_GPIO2); //ext_gpio_int[2] in HAL_InitIrqTable()
563 HAL_UpdateIrqTable(E_FIQ_48, E_INT_FIQ_AEON_TO_MIPS_VPE1); //reg_hst3to2_int in HAL_InitIrqTable()
564 HAL_UpdateIrqTable(E_FIQ_49, E_INT_FIQ_AEON_TO_BEON); //reg_hst3to1_int in HAL_InitIrqTable()
565 HAL_UpdateIrqTable(E_FIQ_50, E_INT_FIQ_AEON_TO_8051); //reg_hst3to0_int in HAL_InitIrqTable()
566 HAL_UpdateIrqTable(E_FIQ_51, E_INT_FIQ_USB1); //usb_int1 in HAL_InitIrqTable()
567 HAL_UpdateIrqTable(E_FIQ_52, E_INT_FIQ_UHC1); //uhc_int1 in HAL_InitIrqTable()
568 HAL_UpdateIrqTable(E_FIQ_53, E_INT_FIQ_USB2); //usb_int2 in HAL_InitIrqTable()
569 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_UHC2); //uhc_int2 in HAL_InitIrqTable()
570 HAL_UpdateIrqTable(E_FIQ_55, E_INT_FIQ_GPIO3); //ext_gpio_int[3] in HAL_InitIrqTable()
571 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_GPIO4); //ext_gpio_int[4] in HAL_InitIrqTable()
572 HAL_UpdateIrqTable(E_FIQ_57, E_INT_FIQ_GPIO5); //ext_gpio_int[5] in HAL_InitIrqTable()
573 HAL_UpdateIrqTable(E_FIQ_58, E_INT_FIQ_GPIO6); //ext_gpio_int[6] in HAL_InitIrqTable()
574 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_PWM_RP_L); //pwm_rp_l_int in HAL_InitIrqTable()
575 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_PWM_FP_L); //pwm_fp_l_int in HAL_InitIrqTable()
576 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_PWM_RP_R); //pwm_rp_r_int in HAL_InitIrqTable()
577 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_PWM_FP_R); //pwm_fp_r_int in HAL_InitIrqTable()
578 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_GPIO7); //ext_gpio_int[7] in HAL_InitIrqTable()