Lines Matching refs:E_IRQEXPH_START
281 #define IRQEXPH_BDMA0 (0x01 << (E_IRQ_48 - E_IRQEXPH_START))
282 #define IRQEXPH_BDMA1 (0x01 << (E_IRQ_49 - E_IRQEXPH_START))
283 #define IRQEXPH_UART2MCU (0x01 << (E_IRQ_50 - E_IRQEXPH_START))
284 #define IRQEXPH_URDMA2MCU (0x01 << (E_IRQ_51 - E_IRQEXPH_START))
285 #define IRQEXPH_DVI_HDMI_HDCP (0x01 << (E_IRQ_52 - E_IRQEXPH_START))
286 #define IRQEXPH_EXT_GPIO6 (0x01 << (E_IRQ_53 - E_IRQEXPH_START))
287 #define IRQEXPH_CEC (0x01 << (E_IRQ_54 - E_IRQEXPH_START))
288 #define IRQEXPH_HDCP_IIC (0x01 << (E_IRQ_55 - E_IRQEXPH_START))
289 #define IRQEXPH_HDCP_X74 (0x01 << (E_IRQ_56 - E_IRQEXPH_START))
290 #define IRQEXPH_WADR_ERR (0x01 << (E_IRQ_57 - E_IRQEXPH_START))
291 #define IRQEXPH_UHC2 (0x01 << (E_IRQ_58 - E_IRQEXPH_START))
292 #define IRQEXPH_GE (0x01 << (E_IRQ_59 - E_IRQEXPH_START))
293 #define IRQEXPH_MIIC_DMA2 (0x01 << (E_IRQ_60 - E_IRQEXPH_START))
294 #define IRQEXPH_MIIC_DMA1 (0x01 << (E_IRQ_61 - E_IRQEXPH_START))
295 #define IRQEXPH_MIIC_DMA0 (0x01 << (E_IRQ_62 - E_IRQEXPH_START))
296 #define IRQEXPH_EXT_GPIO7 (0x01 << (E_IRQ_63 - E_IRQEXPH_START))