Lines Matching refs:MOD_W2BYTEMSK
2537 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, BIT(15), BIT(15)); in MHal_PNL_HWLVDSReservedtoLRFlag()
2541 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
2548 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, BIT(13), BIT(13)); in MHal_PNL_HWLVDSReservedtoLRFlag()
2552 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, BIT(12), BIT(12)); in MHal_PNL_HWLVDSReservedtoLRFlag()
2558 …MOD_W2BYTEMSK(REG_MOD_BK00_54_L, BIT(10), BIT(10)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1… in MHal_PNL_HWLVDSReservedtoLRFlag()
2563 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); in MHal_PNL_HWLVDSReservedtoLRFlag()
2567 …MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x00, BIT(10)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: t… in MHal_PNL_HWLVDSReservedtoLRFlag()
2970 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2978 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2981 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
3237 … MOD_W2BYTEMSK(REG_MOD_BK00_52_L, 0x0000, 0xC000); //[15]:reg_abswitch_l [14]:reg_abswitch_r in MHal_PNL_SetOutputType()
3238 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, 0x0000, BIT(1)); in MHal_PNL_SetOutputType()
3267 … MOD_W2BYTEMSK(REG_MOD_BK00_52_L, 0x0000, 0xC000); //[15]:reg_abswitch_l [14]:reg_abswitch_r in MHal_PNL_SetOutputType()
3268 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, 0x0000, BIT(1)); in MHal_PNL_SetOutputType()
3297 … MOD_W2BYTEMSK(REG_MOD_BK00_52_L, 0x0000, 0xC000); //[15]:reg_abswitch_l [14]:reg_abswitch_r in MHal_PNL_SetOutputType()
3298 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, 0x0000, BIT(1)); in MHal_PNL_SetOutputType()
3335 MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(14) ); in MHal_PNL_SetOutputType()
3336 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L, BIT(10), BIT(10) ); in MHal_PNL_SetOutputType()
3337 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, 0x0000, BIT(12) ); in MHal_PNL_SetOutputType()
3338 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, 0x0000, BIT(0) ); in MHal_PNL_SetOutputType()
3339 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, (BIT(2)|BIT(3)|BIT(4)) ); in MHal_PNL_SetOutputType()
3391 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L, 0x3F00, 0x3F00); in MHal_PNL_SetOutputType()
3392 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x003F, 0x003F); in MHal_PNL_SetOutputType()
3394 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L, 0x0000, 0x3F00); in MHal_PNL_SetOutputType()
3704 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(1)) )<<14, (BIT(15)) ); in MHal_PNL_Init_MOD()
3706 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(2)) )<<12, (BIT(14)) ); in MHal_PNL_Init_MOD()
3708 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(3)) )<<10, (BIT(13)) ); in MHal_PNL_Init_MOD()
3710 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(4)) )<<8 , (BIT(12)) ); in MHal_PNL_Init_MOD()
3712 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(5)) )<<6 , (BIT(11)) ); in MHal_PNL_Init_MOD()
3714 …MOD_W2BYTEMSK(REG_MOD_BK00_51_L, ( pstPanelInitData->u16MOD_CTRL0 & (BIT(7)) )>>5, (BIT(2)) ); //r… in MHal_PNL_Init_MOD()
3721 MOD_W2BYTEMSK(REG_MOD_BK00_3C_L, 0x0000, 0xFFFF); in MHal_PNL_Init_MOD()
3731 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x5000, 0xF000); in MHal_PNL_Init_MOD()
3741 MOD_W2BYTEMSK(REG_MOD_BK00_0F_L, 0xF800, 0xFF00 ); //reg_rsclk_testmd in MHal_PNL_Init_MOD()
3745 MOD_W2BYTEMSK(REG_MOD_BK00_0F_L, 0xD800, 0xFF00 ); //reg_rsclk_testmd in MHal_PNL_Init_MOD()
3750 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, ( BIT(15)|BIT(13) ), 0xFFFF); in MHal_PNL_Init_MOD()
3753 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|B… in MHal_PNL_Init_MOD()
3758 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(14), BIT(14)); in MHal_PNL_Init_MOD()
3762 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x0000, BIT(14)); in MHal_PNL_Init_MOD()
3769 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(9), BIT(9)); in MHal_PNL_Init_MOD()
3770 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
3774 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, 0x0000, BIT(9)); in MHal_PNL_Init_MOD()
3775 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
3793 … MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(12)); //[12]reg_vbi_en:vbi information on lvds enable in MHal_PNL_Init_MOD()
3794 … MOD_W2BYTEMSK(REG_MOD_BK00_54_L, BIT(13), BIT(13)); //[13]reg_vfde_mask:mask vfde AND de in MHal_PNL_Init_MOD()
3801 … MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(12)); //[12]reg_vbi_en:vbi information on lvds enable in MHal_PNL_Init_MOD()
3802 MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(13)); //[13]reg_vfde_mask:mask vfde AND de in MHal_PNL_Init_MOD()
3808 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(14), BIT(14)); // [14] enable 8ch vx1 mode in MHal_PNL_Init_MOD()
3812 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x0000, BIT(14)); // [14] enable 8ch vx1 mode in MHal_PNL_Init_MOD()
3831 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(14)); // [14] enable 8ch vx1 mode in MHal_PNL_Init_MOD()
3856 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (BIT(15)|BIT(13)|BIT(12)|BIT(10)), 0xFF00); in MHal_PNL_Init_MOD()
3859 MOD_W2BYTEMSK(REG_MOD_BK00_3A_L, BIT(7), BIT(7)); in MHal_PNL_Init_MOD()
3868 MOD_W2BYTEMSK(REG_MOD_BK00_79_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
3869 MOD_W2BYTEMSK(REG_MOD_BK00_77_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
3874 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, (BIT(14)|BIT(13)) , (BIT(15)|BIT(14)|BIT(13)) ); in MHal_PNL_Init_MOD()
3881 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x0003 , 0xFF0F); in MHal_PNL_Init_MOD()
3890 MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x0000, 0xF000); in MHal_PNL_Init_MOD()
3896 MOD_W2BYTEMSK(REG_MOD_BK00_0F_L, 0xE400, 0xFF00 ); //reg_rsclk_testmd in MHal_PNL_Init_MOD()
3900 MOD_W2BYTEMSK(REG_MOD_BK00_0F_L, 0xF800, 0xFF00 ); //reg_rsclk_testmd in MHal_PNL_Init_MOD()
3906 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, 0x0000, BIT(9)); in MHal_PNL_Init_MOD()
3907 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
3911 …MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(7)|BIT(6)))<<8 , (BIT(15)|… in MHal_PNL_Init_MOD()
3912 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(8) )<<5 , BIT(13)); in MHal_PNL_Init_MOD()
3913 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(9) )<<3 , BIT(12)); in MHal_PNL_Init_MOD()
3926 …MOD_W2BYTEMSK(REG_MOD_BK00_05_L, (pstPanelInitData->u16MOD_CTRLA & BIT(4))>>3 , BIT(1));// PANEL_I… in MHal_PNL_Init_MOD()
3927 …MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRLA & BIT(12))>>7, BIT(5));// PANEL_I… in MHal_PNL_Init_MOD()
3928 …MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRLA & BIT(3))<<3, BIT(6)); // PANEL_I… in MHal_PNL_Init_MOD()
3929 …MOD_W2BYTEMSK(REG_MOD_BK00_00_L, (pstPanelInitData->u16MOD_CTRLA & BIT(2))<<5, BIT(7)); // PANEL_I… in MHal_PNL_Init_MOD()
3931 …MOD_W2BYTEMSK(REG_MOD_BK00_05_L, (pstPanelInitData->u8MOD_CTRLB & (BIT(0)|BIT(1)))<<2, (BIT(2)|BIT… in MHal_PNL_Init_MOD()
3932 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, BIT(13), BIT(13)); // for LVDS: reg_pdp_10bit in MHal_PNL_Init_MOD()
4068 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8)); in MHal_PNL_DumpMODReg()
4072 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask); in MHal_PNL_DumpMODReg()
4311 MOD_W2BYTEMSK(REG_MOD_A_BK00_78_L, 0x00, BIT(15)); // Disable calibration function in msModCurrentCalibration()
4344 MOD_W2BYTEMSK(REG_MOD_A_BK00_78_L, u8Cab, 0x07); in MHal_PNL_MOD_Calibration()
4484 MOD_W2BYTEMSK(REG_MOD_BK00_69_L, u16Red , 0x03FF); in MHal_PNL_SetOutputPattern()
4485 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, u16Green , 0x03FF); in MHal_PNL_SetOutputPattern()
4486 MOD_W2BYTEMSK(REG_MOD_BK00_6B_L, u16Blue , 0x03FF); in MHal_PNL_SetOutputPattern()
4488 MOD_W2BYTEMSK(REG_MOD_BK00_68_L, BIT(12) , BIT(12)); in MHal_PNL_SetOutputPattern()
4492 MOD_W2BYTEMSK(REG_MOD_BK00_68_L, DISABLE , BIT(12)); in MHal_PNL_SetOutputPattern()
4546 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11)); in MHal_PNL_VBY1_Handshake()
4547 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_Handshake()
4550 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
4551 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
4552 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
4553 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
4634 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
4635 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
4639 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
4640 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
4641 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
4642 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
4702 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, BIT(12), BIT(12)); in MHal_PNL_SetOutputInterlaceTiming()
4703 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, BIT(2), BIT(2)); in MHal_PNL_SetOutputInterlaceTiming()
4705 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, BIT(3), BIT(3)); in MHal_PNL_SetOutputInterlaceTiming()
4711 MOD_W2BYTEMSK(REG_MOD_BK00_05_L, 0x0000, BIT(12)); in MHal_PNL_SetOutputInterlaceTiming()
4712 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, BIT(2)); in MHal_PNL_SetOutputInterlaceTiming()
4714 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, BIT(3)); in MHal_PNL_SetOutputInterlaceTiming()
4842 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L, BIT(10), BIT(10)); //[10]enable osd lvds path in MHal_PNL_SetOSDCOutputType()
4843 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); //sw reset in MHal_PNL_SetOSDCOutputType()
4844 MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(14)); in MHal_PNL_SetOSDCOutputType()
4845 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, (BIT(2)|BIT(3)|BIT(4)) ); in MHal_PNL_SetOSDCOutputType()
4875 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, BIT(0), BIT(0)); in MHal_PNL_SetOSDCOutputType()
4888 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L, 0x0000, BIT(10)); //[10]enable osd lvds path in MHal_PNL_SetOSDCOutputType()
4889 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); //sw reset in MHal_PNL_SetOSDCOutputType()
4890 MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(14)); in MHal_PNL_SetOSDCOutputType()
4891 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, (BIT(2)|BIT(3)|BIT(4)) ); in MHal_PNL_SetOSDCOutputType()
4900 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, (BIT(14)|BIT(13)) , (BIT(15)|BIT(14)|BIT(13)) ); in MHal_PNL_SetOSDCOutputType()
4907 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x0003 , 0xFF0F); in MHal_PNL_SetOSDCOutputType()
4918 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0xa260 , 0xFFE0); in MHal_PNL_SetOSDCOutputType()
4933 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0xa240 , 0xFFE0); in MHal_PNL_SetOSDCOutputType()
4940 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x0000, BIT(10)); in MHal_PNL_SetOSDCOutputType()
4944 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, BIT(10), BIT(10)); in MHal_PNL_SetOSDCOutputType()
4949 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x0000, BIT(10)); in MHal_PNL_SetOSDCOutputType()
5183 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, 0x0000, BIT(0)); //sw reset in MHal_PNL_TCON_Patch()
5184 MOD_W2BYTEMSK(REG_MOD_BK00_2E_L, 0x0000, BIT(10)); //[10]enable osd lvds path in MHal_PNL_TCON_Patch()
5185 MOD_W2BYTEMSK(REG_MOD_BK00_54_L, 0x0000, BIT(14)); in MHal_PNL_TCON_Patch()
5186 MOD_W2BYTEMSK(REG_MOD_BK00_51_L, 0x0000, (BIT(2)|BIT(3)|BIT(4)) ); in MHal_PNL_TCON_Patch()
5188 MOD_W2BYTEMSK(REG_MOD_BK00_00_L, BIT(0), BIT(0)); //sw reset in MHal_PNL_TCON_Patch()
5224 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, BIT(11), 0xF800); in _Hal_MOD_VB1_CH_SWICH()
5228 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, BIT(14), 0xF800); in _Hal_MOD_VB1_CH_SWICH()
5232 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, BIT(15), 0xF800); in _Hal_MOD_VB1_CH_SWICH()
5236 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x0000, 0xF800); in _Hal_MOD_VB1_CH_SWICH()