Lines Matching refs:MOD_A_W2BYTEMSK
1026 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x00, BIT(4)); //reg_ck1x_4dig_phsel_path2 in MHal_MOD_PowerOn()
1033 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, BIT(1) , BIT(1)); //reg_gcr_en_reg: enable clk tree pwr in MHal_MOD_PowerOn()
1034 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00 , BIT(0)); //reg_pd_ib_mod: power down mod atop in MHal_MOD_PowerOn()
1047 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u16ChannelClk_En, 0x001F); in MHal_MOD_PowerOn()
1052 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0400, 0x0FFF); in MHal_MOD_PowerOn()
1053 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0444, 0x0FFF); in MHal_MOD_PowerOn()
1058 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1059 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1063 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1064 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1072 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1073 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1079 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0044, 0x0FFF); in MHal_MOD_PowerOn()
1080 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0400, 0x0FFF); in MHal_MOD_PowerOn()
1084 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1085 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1093 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(4), BIT(4));// reg_ck1x_4dig_phsel_path2: test phase in MHal_MOD_PowerOn()
1096 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: p… in MHal_MOD_PowerOn()
1097 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00, BIT(1)); //reg_gcr_en_reg: enable clk tree pwr in MHal_MOD_PowerOn()
1100 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0000, 0x001F); //enable ib, enabl… in MHal_MOD_PowerOn()
1103 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0100, 0x0FFF); in MHal_MOD_PowerOn()
1104 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0111, 0x0FFF); in MHal_MOD_PowerOn()
1108 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_MOD_PowerOn()
1112 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_MOD_PowerOn()
1147 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
1152 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
1162 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
2516 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, 0, BIT(15)); //software reset, 0:reset in MHal_PNL_PreSetModeOn()
2520 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(15), BIT(15)); in MHal_PNL_PreSetModeOn()
2828 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0, BIT(15)); in MHal_PNL_MOD_Control_Out_Swing()
2914 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_22_L, in MHal_PNL_MOD_PECurrent_Setting()
2924 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_23_L, in MHal_PNL_MOD_PECurrent_Setting()
2934 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_24_L, in MHal_PNL_MOD_PECurrent_Setting()
2944 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_25_L, in MHal_PNL_MOD_PECurrent_Setting()
2963 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0A_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2965 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2969 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2974 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2977 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2980 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
3046 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0, BIT(15)); in msSetVBY1RconValue()
3087 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3091 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3094 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x0000,0x0FF0); in MHal_PNL_SetOutputType()
3095 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3102 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, (BIT(3)|BIT(2)), (BIT(3)|BIT(2))); // TTL skew: G in MHal_PNL_SetOutputType()
3103 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, (BIT(5)|BIT(4)), (BIT(5)|BIT(4))); // TTL skew: B in MHal_PNL_SetOutputType()
3127 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x03F0,0x0FF0); in MHal_PNL_SetOutputType()
3128 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3155 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3159 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3331 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F , 0x001F); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
3332 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOutputType()
3341 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(0), BIT(0)); //[15]sw_rst in MHal_PNL_SetOutputType()
3342 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x0C00 , 0x1F00); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
3351 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3355 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3366 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
3368 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
3370 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_62_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
3372 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_60_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
3375 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
3378 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
3381 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_62_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3384 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_60_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3400 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0, 0xF000); in MHal_PNL_SetOutputType()
3408 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3413 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00, BIT(0)); in MHal_PNL_SetOutputType()
3441 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x03F0,0x0FF0);// LVDS output enable, [5:4] Output enable: PA… in MHal_PNL_SetOutputType()
3442 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3444 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3449 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000, (BIT(3)|BIT(2))); // TTL skew: G in MHal_PNL_SetOutputType()
3450 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000, (BIT(5)|BIT(4))); // TTL skew: B in MHal_PNL_SetOutputType()
3842 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_04_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch: Differential output pr… in MHal_PNL_Init_MOD()
3843 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch: enable double termin… in MHal_PNL_Init_MOD()
3844 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0xFFFF, 0xFFFF); //vby1 channel enable: vby1 channel enable in MHal_PNL_Init_MOD()
3903 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0x0000, 0xFFFF); //vby1 channel enable: vby1 channel enable in MHal_PNL_Init_MOD()
3945 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x0000 , 0x1F00); //bank selection for skew clock in MHal_PNL_Init_MOD()
3959 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_02_L, 0xFFFF, 0xFFFF); in MHal_PNL_Init_MOD()
4200 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, BIT(15), BIT(15)); in msModCurrentCalibration()
4207 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x0500, 0x0F00); in msModCurrentCalibration()
4210 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_78_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(… in msModCurrentCalibration()
4217 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_78_L, BIT(15), BIT(15)); // Enable calibration function in msModCurrentCalibration()
4223 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(15), BIT(15)); in msModCurrentCalibration()
4256 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x0000, BIT(15)); in msModCurrentCalibration()
4258 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, u16ICONtempCH0_1, 0xFFFF); in msModCurrentCalibration()
4259 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, u16ICONtempCH2_3, 0xFFFF); in msModCurrentCalibration()
4260 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, u16ICONtempCH4_5, 0xFFFF); in msModCurrentCalibration()
4261 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_33_L, u16ICONtempCH6_7, 0xFFFF); in msModCurrentCalibration()
4262 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, u16ICONtempCH8_9, 0xFFFF); in msModCurrentCalibration()
4263 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_35_L, u16ICONtempCH10_11, 0xFFFF); in msModCurrentCalibration()
4264 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_36_L, u16ICONtempCH12_13, 0xFFFF); in msModCurrentCalibration()
4265 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_37_L, u16ICONtempCH14_15, 0xFFFF); in msModCurrentCalibration()
4278 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x00, BIT(15)); in msModCurrentCalibration()
4281 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4282 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4283 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4284 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_33_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4285 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4286 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_35_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4287 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_36_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4288 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_37_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4847 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(0), BIT(0)); //[0]sw_rst in MHal_PNL_SetOSDCOutputType()
4852 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(10), BIT(10)); in MHal_PNL_SetOSDCOutputType()
4858 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0444, 0x0FFF); in MHal_PNL_SetOSDCOutputType()
4884 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
4893 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
4922 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
5795 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x1F, 0x1F); //open all clk in _MHal_PNL_Set_Clk()
5897 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u8Clk, 0x1F); in _MHal_PNL_Set_Clk()
5905 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x000F, 0x001F); in _MHal_PNL_Set_Clk()
5912 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0003, 0x001F); in _MHal_PNL_Set_Clk()
5916 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0003, 0x001F); in _MHal_PNL_Set_Clk()
5922 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0001, 0x001F); in _MHal_PNL_Set_Clk()
5927 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0001, 0x001F); in _MHal_PNL_Set_Clk()
5931 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F, 0x001F); in _MHal_PNL_Set_Clk()
5935 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F, 0x001F); in _MHal_PNL_Set_Clk()