Lines Matching refs:MOD_W2BYTEMSK
256 …MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LV… in MHal_Shift_LVDS_Pair()
258 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); in MHal_Shift_LVDS_Pair()
1138 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1142 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1149 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1153 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1160 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); in MHal_PNL_HWLVDSReservedtoLRFlag()
1485 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1488 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1496 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1499 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
1605 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair in MHal_PNL_SetOutputType()
1612 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000); in MHal_PNL_SetOutputType()
1617 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
1624 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path in MHal_PNL_SetOutputType()
1674 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F); in MHal_PNL_SetOutputType()
1676 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00); in MHal_PNL_SetOutputType()
1678 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00); in MHal_PNL_SetOutputType()
1730 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F); in MHal_PNL_SetOutputType()
1735 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
1753 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair in MHal_PNL_MISC_Control()
1828 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK); in MHal_PNL_Init_MOD()
1865 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07); in MHal_PNL_Init_MOD()
1874 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
1922 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8)); in MHal_PNL_DumpMODReg()
1926 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask); in MHal_PNL_DumpMODReg()
2333 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07); in MHal_PNL_MOD_Calibration()
2471 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF); in MHal_PNL_SetOutputPattern()
2472 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF); in MHal_PNL_SetOutputPattern()
2473 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF); in MHal_PNL_SetOutputPattern()
2475 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15)); in MHal_PNL_SetOutputPattern()
2479 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15)); in MHal_PNL_SetOutputPattern()
2533 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11)); in MHal_PNL_VBY1_Handshake()
2534 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_Handshake()
2537 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
2538 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
2539 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
2540 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
2621 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
2622 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
2626 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
2627 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
2628 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
2629 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
2689 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
2691 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
2696 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
2697 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()