Lines Matching refs:MOD_A_W2BYTEMSK
1022 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x00, BIT(4)); //reg_ck1x_4dig_phsel_path2 in MHal_MOD_PowerOn()
1029 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, BIT(1) , BIT(1)); //reg_gcr_en_reg: enable clk tree pwr in MHal_MOD_PowerOn()
1030 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00 , BIT(0)); //reg_pd_ib_mod: power down mod atop in MHal_MOD_PowerOn()
1043 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u16ChannelClk_En, 0x001F); in MHal_MOD_PowerOn()
1048 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0400, 0x0FFF); in MHal_MOD_PowerOn()
1049 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0444, 0x0FFF); in MHal_MOD_PowerOn()
1054 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1055 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1059 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1060 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1068 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1069 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1075 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0044, 0x0FFF); in MHal_MOD_PowerOn()
1076 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0400, 0x0FFF); in MHal_MOD_PowerOn()
1080 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1081 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0000, 0x0FFF); in MHal_MOD_PowerOn()
1089 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(4), BIT(4));// reg_ck1x_4dig_phsel_path2: test phase in MHal_MOD_PowerOn()
1092 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, BIT(0), BIT(0)); //analog MOD power down. 1: power down, 0: p… in MHal_MOD_PowerOn()
1093 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00, BIT(1)); //reg_gcr_en_reg: enable clk tree pwr in MHal_MOD_PowerOn()
1096 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0000, 0x001F); //enable ib, enabl… in MHal_MOD_PowerOn()
1099 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_76_L, 0x0100, 0x0FFF); in MHal_MOD_PowerOn()
1100 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0111, 0x0FFF); in MHal_MOD_PowerOn()
1104 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_MOD_PowerOn()
1108 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_MOD_PowerOn()
1143 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
1148 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
1158 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0x5550, 0xFFF0); in MHal_Output_LVDS_Pair_Setting()
2512 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, 0, BIT(15)); //software reset, 0:reset in MHal_PNL_PreSetModeOn()
2516 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(15), BIT(15)); in MHal_PNL_PreSetModeOn()
2824 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0, BIT(15)); in MHal_PNL_MOD_Control_Out_Swing()
2887 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_22_L, in MHal_PNL_MOD_PECurrent_Setting()
2897 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_23_L, in MHal_PNL_MOD_PECurrent_Setting()
2907 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_24_L, in MHal_PNL_MOD_PECurrent_Setting()
2917 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_25_L, in MHal_PNL_MOD_PECurrent_Setting()
2936 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_0A_L, 0xFFFF, 0xFFFF); //Enable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2938 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0xFFFF, 0xFFFF); //GCR_EN_RINT (internal termination open) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2942 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0xFFFF, 0xFFFF); //Disable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2947 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, 0x0000, 0xFFFF); //Disable TTL low-power mode in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2950 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0x0000, 0xFFFF); //GCR_EN_RINT (internal termination close) in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2953 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0x0000, 0xFFFF); //Enable DRIVER BIAS OP in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
3019 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0, BIT(15)); in msSetVBY1RconValue()
3060 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3064 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3067 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x0000,0x0FF0); in MHal_PNL_SetOutputType()
3068 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3075 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, (BIT(3)|BIT(2)), (BIT(3)|BIT(2))); // TTL skew: G in MHal_PNL_SetOutputType()
3076 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, (BIT(5)|BIT(4)), (BIT(5)|BIT(4))); // TTL skew: B in MHal_PNL_SetOutputType()
3100 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x03F0,0x0FF0); in MHal_PNL_SetOutputType()
3101 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3128 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3132 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3304 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F , 0x001F); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
3305 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOutputType()
3314 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(0), BIT(0)); //[15]sw_rst in MHal_PNL_SetOutputType()
3315 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x0C00 , 0x1F00); // enable clk_dot_mini_pre_osd & clk_dot_mi… in MHal_PNL_SetOutputType()
3324 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x2000,0x2000); in MHal_PNL_SetOutputType()
3328 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x0000,0x2000); in MHal_PNL_SetOutputType()
3339 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
3341 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0x0FFF, 0x0FFF); in MHal_PNL_SetOutputType()
3343 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_62_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
3345 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_60_L, 0x0000, 0x0FFF); in MHal_PNL_SetOutputType()
3348 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
3351 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0xF000, 0xF000); in MHal_PNL_SetOutputType()
3354 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_62_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3357 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_60_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3373 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_18_L, 0, 0xF000); in MHal_PNL_SetOutputType()
3381 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_68_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3386 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_01_L, 0x00, BIT(0)); in MHal_PNL_SetOutputType()
3414 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6B_L, 0x03F0,0x0FF0);// LVDS output enable, [5:4] Output enable: PA… in MHal_PNL_SetOutputType()
3415 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000,0xFF00); in MHal_PNL_SetOutputType()
3417 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_66_L, 0x0000, 0xF000); in MHal_PNL_SetOutputType()
3422 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000, (BIT(3)|BIT(2))); // TTL skew: G in MHal_PNL_SetOutputType()
3423 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_74_L, 0x0000, (BIT(5)|BIT(4))); // TTL skew: B in MHal_PNL_SetOutputType()
3815 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_04_L, 0xFFFF, 0xFFFF); //reg_gcr_pe_en_ch: Differential output pr… in MHal_PNL_Init_MOD()
3816 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_06_L, 0x0000, 0xFFFF); //reg_gcr_en_rint_ch: enable double termin… in MHal_PNL_Init_MOD()
3817 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0xFFFF, 0xFFFF); //vby1 channel enable: vby1 channel enable in MHal_PNL_Init_MOD()
3876 … MOD_A_W2BYTEMSK(REG_MOD_A_BK00_08_L, 0x0000, 0xFFFF); //vby1 channel enable: vby1 channel enable in MHal_PNL_Init_MOD()
3918 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, 0x0000 , 0x1F00); //bank selection for skew clock in MHal_PNL_Init_MOD()
3932 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_02_L, 0xFFFF, 0xFFFF); in MHal_PNL_Init_MOD()
4173 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, BIT(15), BIT(15)); in msModCurrentCalibration()
4180 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x0500, 0x0F00); in msModCurrentCalibration()
4183 …MOD_A_W2BYTEMSK(REG_MOD_A_BK00_78_L, pPNLResourcePrivate->sthalPNL._u8MOD_CALI_TARGET, BIT(2)|BIT(… in msModCurrentCalibration()
4190 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_78_L, BIT(15), BIT(15)); // Enable calibration function in msModCurrentCalibration()
4196 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_79_L, BIT(15), BIT(15)); in msModCurrentCalibration()
4229 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x0000, BIT(15)); in msModCurrentCalibration()
4231 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, u16ICONtempCH0_1, 0xFFFF); in msModCurrentCalibration()
4232 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, u16ICONtempCH2_3, 0xFFFF); in msModCurrentCalibration()
4233 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, u16ICONtempCH4_5, 0xFFFF); in msModCurrentCalibration()
4234 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_33_L, u16ICONtempCH6_7, 0xFFFF); in msModCurrentCalibration()
4235 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, u16ICONtempCH8_9, 0xFFFF); in msModCurrentCalibration()
4236 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_35_L, u16ICONtempCH10_11, 0xFFFF); in msModCurrentCalibration()
4237 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_36_L, u16ICONtempCH12_13, 0xFFFF); in msModCurrentCalibration()
4238 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_37_L, u16ICONtempCH14_15, 0xFFFF); in msModCurrentCalibration()
4251 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_7A_L, 0x00, BIT(15)); in msModCurrentCalibration()
4254 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_30_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4255 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_31_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4256 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_32_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4257 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_33_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4258 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_34_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4259 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_35_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4260 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_36_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4261 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_37_L, u16ICONtempDefault, 0xFFFF); in msModCurrentCalibration()
4820 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_77_L, BIT(0), BIT(0)); //[0]sw_rst in MHal_PNL_SetOSDCOutputType()
4825 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(10), BIT(10)); in MHal_PNL_SetOSDCOutputType()
4831 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_6F_L, 0x0444, 0x0FFF); in MHal_PNL_SetOSDCOutputType()
4854 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
4863 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
4892 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_10_L, BIT(13),BIT(13)); in MHal_PNL_SetOSDCOutputType()
5745 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x1F, 0x1F); //open all clk in _MHal_PNL_Set_Clk()
5847 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u8Clk, 0x1F); in _MHal_PNL_Set_Clk()
5855 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x000F, 0x001F); in _MHal_PNL_Set_Clk()
5862 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0003, 0x001F); in _MHal_PNL_Set_Clk()
5866 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0003, 0x001F); in _MHal_PNL_Set_Clk()
5872 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0001, 0x001F); in _MHal_PNL_Set_Clk()
5877 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x0001, 0x001F); in _MHal_PNL_Set_Clk()
5881 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F, 0x001F); in _MHal_PNL_Set_Clk()
5885 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, 0x001F, 0x001F); in _MHal_PNL_Set_Clk()