Lines Matching refs:MOD_W2BYTEMSK
258 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0008, 0x0008); // reg_fix_cnt_clr in MHal_MOD_PowerOn()
259 MOD_W2BYTEMSK(REG_MOD_BK00_5B_L, 0x0000, 0x0008); in MHal_MOD_PowerOn()
261 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0080, 0x0080); // reg_proc_st_clr in MHal_MOD_PowerOn()
262 MOD_W2BYTEMSK(REG_MOD_BK00_7D_L, 0x0000, 0x0080); in MHal_MOD_PowerOn()
264 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0080, 0x0080); // reg_unlock_cnt_clr in MHal_MOD_PowerOn()
265 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x0080); in MHal_MOD_PowerOn()
267 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x0000, 0x8000); in MHal_MOD_PowerOn()
268 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x8000, 0x8000); in MHal_MOD_PowerOn()
314 …MOD_W2BYTEMSK(REG_MOD_BK00_42_L, (BIT(7) | BIT(6)), (BIT(7) | BIT(6))); // shift_lvds_pair, set LV… in MHal_Shift_LVDS_Pair()
316 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); in MHal_Shift_LVDS_Pair()
1831 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(15), BIT(15)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1835 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(14), BIT(14)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1842 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(13), BIT(13)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1846 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, BIT(12), BIT(12)); in MHal_PNL_HWLVDSReservedtoLRFlag()
1852 …MOD_W2BYTEMSK(REG_MOD_BK00_30_L, BIT(14), BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1… in MHal_PNL_HWLVDSReservedtoLRFlag()
1857 MOD_W2BYTEMSK(REG_MOD_BK00_5A_L, 0x0000, (BIT(15) | BIT(14) | BIT(13) | BIT(12))); in MHal_PNL_HWLVDSReservedtoLRFlag()
1861 …MOD_W2BYTEMSK(REG_MOD_BK00_30_L, 0x00, BIT(14)); //reg_sel_ext_bit: sel extend bit, 0: osd_de 1: t… in MHal_PNL_HWLVDSReservedtoLRFlag()
2264 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2267 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x003F, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2275 MOD_W2BYTEMSK(REG_MOD_BK00_76_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2278 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x003F); in MHal_PNL_MOD_Control_Out_TTL_Resistor_OP()
2389 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0x0000, (BIT(7) | BIT(6))); // shift_lvds_pair in MHal_PNL_SetOutputType()
2396 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0xE000); in MHal_PNL_SetOutputType()
2400 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0001, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_SetOutputType()
2405 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, BIT(8), BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
2411 MOD_W2BYTEMSK(REG_MOD_BK00_34_L, 0xF000, 0xF000); //[15:14]datax[13:12]data_format3,2 in MHal_PNL_SetOutputType()
2551 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(3), 0xFFFF ); // enable osd lvds path in MHal_PNL_SetOutputType()
2602 MOD_W2BYTEMSK(REG_MOD_BK00_7C_L, 0x3F3F, 0x3F3F); in MHal_PNL_SetOutputType()
2604 MOD_W2BYTEMSK(REG_MOD_BK00_7A_L, 0x0000, 0x3F00); in MHal_PNL_SetOutputType()
2606 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFC00); in MHal_PNL_SetOutputType()
2658 MOD_W2BYTEMSK(REG_MOD_BK00_7E_L, 0x0000, 0x000F); in MHal_PNL_SetOutputType()
2663 MOD_W2BYTEMSK(REG_MOD_BK00_4A_L, 0x0, BIT(8)); // GPO gating in MHal_PNL_SetOutputType()
2681 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(7), BIT(7)); // shift LVDS pair in MHal_PNL_MISC_Control()
2867 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, pstPanelInitData->u16MOD_CTRL0, LBMASK); in MHal_PNL_Init_MOD()
2876 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0xAC40, 0xFDCF); //[15]proc_st[13:12]byte_mode 4 byte mode[6]4ch_… in MHal_PNL_Init_MOD()
2878 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(6))<<3, BIT(9)); in MHal_PNL_Init_MOD()
2879 …MOD_W2BYTEMSK(REG_MOD_BK00_62_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(12)|BIT(11)))>>7, BIT(5)|B… in MHal_PNL_Init_MOD()
2887 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0002, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2889 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x1002, 0xFFFF); //[11:0]reg_dly_value in MHal_PNL_Init_MOD()
2890 MOD_W2BYTEMSK(REG_MOD_BK00_22_L, 0x0F00, 0xFFFF); //[12:0]reg_hsize in MHal_PNL_Init_MOD()
2891 MOD_W2BYTEMSK(REG_MOD_BK00_26_L, 0x0780, 0xFFFF); //[12:0]reg_div_len in MHal_PNL_Init_MOD()
2892 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0002, 0xFFFF); //[2:0]reg_sram_usage in MHal_PNL_Init_MOD()
2893 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x4000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2897 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007);//[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2903 MOD_W2BYTEMSK(REG_MOD_BK00_21_L, 0x0000, 0xFFFF); //[11:0]reg_dly_value in MHal_PNL_Init_MOD()
2904 MOD_W2BYTEMSK(REG_MOD_BK00_20_L, 0x0000, 0x0007); //[2:0]reg_mft_mode in MHal_PNL_Init_MOD()
2905 MOD_W2BYTEMSK(REG_MOD_BK00_7F_L, 0x0000, 0xFFFF); //[2:0]reg_sram_usage in MHal_PNL_Init_MOD()
2906 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, 0x0000, 0xFFFF); //[14]reg_vfde_mask in MHal_PNL_Init_MOD()
2909 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(14), BIT(14)); //[14]:reg_lockn_to_acq in MHal_PNL_Init_MOD()
2910 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0003, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_Init_MOD()
2913 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2915 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(6), BIT(6)); //[6]4ch_vby1 in MHal_PNL_Init_MOD()
2920 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & BIT(7))<<6, BIT(13)); in MHal_PNL_Init_MOD()
2921 …MOD_W2BYTEMSK(REG_MOD_BK00_63_L, (pstPanelInitData->u16MOD_CTRL9 & (BIT(14)|BIT(13)))>>3, BIT(11)|… in MHal_PNL_Init_MOD()
2925 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(12), BIT(12)); // [12] enable 8ch vx1 mode : 1 in MHal_PNL_Init_MOD()
2930 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, BIT(11), BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2935 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(11)); // [11:10]reg_vby1_pair_mirror2 in MHal_PNL_Init_MOD()
2940 MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x00, BIT(12)); // [12] enable 8ch vx1 mode : 0 in MHal_PNL_Init_MOD()
2979 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x80E8, 0xFFFF); //[0]:reg_vby1_8v4o_mode in MHal_PNL_Init_MOD()
2988 MOD_W2BYTEMSK(REG_MOD_BK00_5C_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
2989 MOD_W2BYTEMSK(REG_MOD_BK00_5E_L,0x8142,0xFFFF); in MHal_PNL_Init_MOD()
3022 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x7, 0x07); in MHal_PNL_Init_MOD()
3089 MOD_W2BYTEMSK(REG_MOD_BK00_53_L, BIT(0), BIT(0)); in MHal_PNL_Init_MOD()
3166 MOD_W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8)); in MHal_PNL_DumpMODReg()
3170 MOD_W2BYTEMSK(u32Addr, u16Value, u16Mask); in MHal_PNL_DumpMODReg()
3369 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, 0x00, BIT(7)); // Disable calibration function in msModCurrentCalibration()
3402 MOD_W2BYTEMSK(REG_MOD_A_BK00_70_L, u8Cab, 0x07); in MHal_PNL_MOD_Calibration()
3546 MOD_W2BYTEMSK(REG_MOD_BK00_02_L, u16Red , 0x03FF); in MHal_PNL_SetOutputPattern()
3547 MOD_W2BYTEMSK(REG_MOD_BK00_03_L, u16Green , 0x03FF); in MHal_PNL_SetOutputPattern()
3548 MOD_W2BYTEMSK(REG_MOD_BK00_04_L, u16Blue , 0x03FF); in MHal_PNL_SetOutputPattern()
3550 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, BIT(15) , BIT(15)); in MHal_PNL_SetOutputPattern()
3554 MOD_W2BYTEMSK(REG_MOD_BK00_01_L, DISABLE , BIT(15)); in MHal_PNL_SetOutputPattern()
3608 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(11)); in MHal_PNL_VBY1_Handshake()
3609 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_Handshake()
3612 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_Handshake()
3613 … MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_Handshake()
3614 …MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_Handshake()
3615 MOD_W2BYTEMSK(REG_MOD_BK00_60_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_Handshake()
3696 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, 0x00, BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
3697 MOD_W2BYTEMSK(REG_MOD_BK00_66_L, BIT(11), BIT(11)); in MHal_PNL_VBY1_OC_Handshake()
3701 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xD6, 0x00FF); // after power on go to stand-by in MHal_PNL_VBY1_OC_Handshake()
3702 … MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0x96, 0x00FF); // connection is established, go to Acquisition in MHal_PNL_VBY1_OC_Handshake()
3703 …MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xB6, 0x00FF); // when internal clock is stable, got to CDR train… in MHal_PNL_VBY1_OC_Handshake()
3704 MOD_W2BYTEMSK(REG_MOD_BK00_64_L, 0xBE, 0x00FF); // enable encoder for DC blance in MHal_PNL_VBY1_OC_Handshake()
3764 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, BIT(4) | BIT(7), BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3766 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, BIT(10)|BIT(11), BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3771 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0, BIT(4) | BIT(7)); in MHal_PNL_SetOutputInterlaceTiming()
3772 MOD_W2BYTEMSK(REG_MOD_BK00_42_L, 0, BIT(10)|BIT(11)); in MHal_PNL_SetOutputInterlaceTiming()
3901 MOD_W2BYTEMSK(REG_MOD_BK00_62_L, 0x00, BIT(14)); //[14]:reg_lockn_to_acq in MHal_PNL_SetOSDCOutputType()
3902 MOD_W2BYTEMSK(REG_MOD_BK00_45_L, 0x0000, 0x0003); //[1]:reg_vby1_vs_inv, [0]:reg_vby1_hs_inv in MHal_PNL_SetOSDCOutputType()
3907 MOD_W2BYTEMSK(REG_MOD_BK00_67_L, 0x0001, 0x0001); //[0]:reg_vby1_8v4o_mode in MHal_PNL_SetOSDCOutputType()
3979 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()
3983 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, BIT(1), BIT(1)); in MHal_PNL_SetOSDCOutputType()
3988 MOD_W2BYTEMSK(REG_MOD_BK00_6A_L, 0, BIT(1)); in MHal_PNL_SetOSDCOutputType()