Lines Matching refs:MDrv_WriteRegBit

723 …      MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_INVERT);               // Not Invert  in MDrv_XC_EnableCLK_for_SUB()
724 …    MDrv_WriteRegBit(REG_CKG_FICLK_F1, DISABLE, CKG_FICLK_F1_GATED);                // Enable clock  in MDrv_XC_EnableCLK_for_SUB()
727 …      MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_INVERT);                   // Not Invert  in MDrv_XC_EnableCLK_for_SUB()
728 …    MDrv_WriteRegBit(REG_CKG_IDCLK1, DISABLE, CKG_IDCLK1_GATED);                    // Enable clock  in MDrv_XC_EnableCLK_for_SUB()
732         MDrv_WriteRegBit(REG_CKG_SIDCLK1, DISABLE, CKG_SIDCLK1_INVERT);  in MDrv_XC_EnableCLK_for_SUB()
733         MDrv_WriteRegBit(REG_CKG_SIDCLK1, DISABLE, CKG_SIDCLK1_GATED);  in MDrv_XC_EnableCLK_for_SUB()
739         MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_INVERT);               // Not Invert  in MDrv_XC_EnableCLK_for_SUB()
740 …     MDrv_WriteRegBit(REG_CKG_FICLK_F1, ENABLE, CKG_FICLK_F1_GATED);                // Enable clock  in MDrv_XC_EnableCLK_for_SUB()
743         MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_INVERT);                   // Not Invert  in MDrv_XC_EnableCLK_for_SUB()
744 …     MDrv_WriteRegBit(REG_CKG_IDCLK1, ENABLE, CKG_IDCLK1_GATED);                    // Enable clock  in MDrv_XC_EnableCLK_for_SUB()
748         MDrv_WriteRegBit(REG_CKG_SIDCLK1, ENABLE, CKG_SIDCLK1_INVERT);  in MDrv_XC_EnableCLK_for_SUB()
749         MDrv_WriteRegBit(REG_CKG_SIDCLK1, ENABLE, CKG_SIDCLK1_GATED);  in MDrv_XC_EnableCLK_for_SUB()