Lines Matching refs:_BIT4
1766 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1806 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
1811 msWriteBit(RFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic in msVifAdcInitial()
1816 msWriteBit(IFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic in msVifAdcInitial()
1855 … msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir in msVifSetIfFreq()
1866 …msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1871 …msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1876 …msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1881 …msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1886 …msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1891 …msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_… in msVifSetIfFreq()
1899 …msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej… in msVifSetIfFreq()
3013 …msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be… in msVifInitial()
3019 …msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be… in msVifInitial()
3027 msWriteBit(AGC_DBB_AVGA_SEL, 0, _BIT4); // Avga gain force x1 in msVifInitial()
3069 …msWriteBit(CR_JTRDET_IN_SEL, 1, _BIT4); // carrier jitter detector input s… in msVifInitial()
3081 msWriteBit(CR_LPF_SEL, VIFInitialIn_inst.VifCrLpfSel, _BIT4); // CR LPF 0: FIR LPF; 1: IIR LPF in msVifInitial()
3157 msWriteBit(BYPASS_CO_A_REJ, 0, _BIT4); // CO_A_REJ not bypass in msVifInitial()
3166 msWriteBit(BYPASS_SOS31, 0, _BIT4); // SOS31 not bypass in msVifInitial()
3323 msWriteBit(LEVLE_SENSE_MOD_TYPE, 0, _BIT4); // 0: negedge; 1: posedge in msVifInitial()
3325 msWriteBit(LEVEL_SENSE_VGA_OREN, 0, _BIT4); in msVifInitial()
3328 msWriteBit(LEVEL_SENSE_DVGA_OREN_SEL, 1 , _BIT4); // 0: SW; 1: HW in msVifInitial()
3352 … msWriteByteMask(AGC_HUM_CNT_MAX , _BIT5 , _BIT4|_BIT5|_BIT6); // 0->128 ,1->256, 2->512 samples in msVifInitial()
3358 …msWriteBit(CR_INV2_EN , 0 , _BIT4); //0:disable… in msVifInitial()
3360 msWriteByteMask(CR_KI_SPEED, _BIT6 , _BIT4|_BIT5|_BIT6|_BIT7); in msVifInitial()
3365 msWriteBit(VIF_ADC_48M, 0, _BIT4); // 0:144MHz , 1:48MHz in msVifInitial()
3368 msWriteBit(VIF_DECI_COEF_SEL, 0, _BIT4); // 0:old, 1:new in msVifInitial()
3370 msWriteBit(HALVIFDBG2_BIT, 0, _BIT4); // 0:144MHz, 1:48MHz in msVifInitial()
3375 msWriteBit(VIF_ADC_48M, 1, _BIT4); // 0:144MHz , 1:48MHz in msVifInitial()
3378 msWriteBit(VIF_DECI_COEF_SEL, 1, _BIT4); // 0:old, 1:new in msVifInitial()
3380 msWriteBit(HALVIFDBG2_BIT, 1, _BIT4); // 0:144MHz, 1:48MHz in msVifInitial()
3470 RIU_WriteRegBit(IFAGC_ENABLE, 0, _BIT4); in msVifExit()
3917 msWriteBit(CR_STATUS_LATCH_EN, 1, _BIT4); // latch CR loop-filter in msVifCrKpKiAutoAdjust()
3925 msWriteBit(CR_STATUS_LATCH_EN, 0, _BIT4); // un-latch CR loop-filter status in msVifCrKpKiAutoAdjust()
4022 RIU_WriteRegBit(0x120A0L, 0, _BIT4); // 0:FIR, 1:IIR in msVifLoadEQCoeff()
4044 RIU_WriteRegBit(0x120A0L, 1, _BIT4); // 0:FIR, 1:IIR in msVifLoadEQCoeff()